downstream cells of cell 2 are fault free. Cell 2 is so called the lower bound and these downstream cells are called Full Confidence Cells (FCCs). FCCs are ...
4th 4th IEEE IEEE International International Symposium Symposium on on Electronic Electronic Design, Design, Test Test & & Applications Application
Adaptive Diagnostic Pattern Generation for Scan Chains*
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Fei Wang1, 2, Yu Hu1 and Xiaowei Li1* Key Laboratory of Computer System and Architecture, Institute of Computing Technology Chinese Academy of Science, Beijing, China 2 Graduate University of Chinese Academy of Sciences, Beijing, China {wang_fei, huyu,lxw}@ict.ac.cn
Abstract Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to adaptively generate patterns to diagnose stuck-at faults in scan chains. Experimental results on ISCAS'89 benchmark circuits show that the proposed method can dramatically reduce the number of diagnostic patterns while obtain high diagnosis resolution.
1. Introduction The use of scan design is a wildly accepted Designfor-Testability (DFT) industrial practice. It is reported that the amount of die area consumed by scan chains and scan control signals can range from 15% to 30% [1]. Moreover, scan chain failure can account for almost 50% of chip failures [2]. Therefore, rapidly identify root causes of failures is vital to guide the failure analysis process for yield improvement. Scan chain diagnosis techniques generally fall into three categories: tester-based solutions, hardware-based solutions and software-based solutions. In the category of the tester-based solutions, people use PFA (Physical Failure Analysis) equipments to observe defective responses at different locations to identify a failing scan cell [2-3]. In the category of the hardware-based solutions, such as [4-5], either custom-designed scan cells or extra signal lines are added into the circuit to improve the controllability or observability. Hardware-based *To whom correspondence should be addressed. This paper is supported in part by National Natural Science Foundation of China (NSFC) under grant No. 60633060, 60776031, 90607010, 60606008, and in part by National Basic Research Program of China (973) under grant No. 2005CB321604, 2005CB321605.
0-7695-3110-5/08 $25.00 © 2008 IEEE DOI 10.1109/DELTA.2008.45
solutions may guarantee the diagnosis quality at the price of area overhead or routing overhead, what is worse; the hardware-based solutions may change the conventional test flow. The other category of scan chain fault diagnosis is software-based solutions, which do not need any modification over the basic scan design. The softwarebased solutions use algorithms to identify failing scan cells. E.g. the algorithm proposed in [6] or in [7], to score the injected faults by comparing the response from the CUD with the response from the ATE (Automatic Test Equipment). The highest score indicates the most possible fault position. In this paper a SAT-based adaptive pattern generation method is proposed. To the best of our knowledge this is the first work that maps the scan chain diagnosis problem to the Boolean-Satisfiability (SAT) problem. The rest of the paper is organized as follows. Section 2 introduces the related work. Section 3 introduces the diagnostic flow. Experimental results are shown in Section 4. Section 5 concludes the paper.
2. Background In this paper, we use the same definition of the upstream scan cell and the downstream scan cell as [6]. All of the scan cells in a scan chain are indexed in descending order from the scan input to the scan output. For a given scan cell i, the cells that are indexed higher than i are upstream to cell i. Similarly, the cells that are indexed lower than i are downstream to cell i. Recently, some SAT-based methods are proposed to diagnose the faults in combinational circuits, such as [89]. However the existing solution is unsuitable for diagnosing faults in scan chains because a faulty scan cell distorts the contents of other good scan cells and leads to excessive fault candidates. Some prior work such as [10] uses conventional ATPG patterns to diagnose scan chain faults. These techniques are efficient at the early stage of scan chain
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diagnosis where most of fault candidates are dumped, however, the remaining faults are hard faults and the remaining faults are hard to be diagnosed if simply increasing the number of patterns. To tackle this problem, Kundu proposed a technique [1] to try to propagate a non-SA value to the data-input of a scan cell, at the same time, constrained the values from the candidate faulty scan cell to the lowest downstream scan cell to the SA value, and run the sequential ATPG to generate a pattern. Li [12] applied a single-excitation (SE) pattern strategy in which only one bit was flipped in the presence of chain faults. Therefore, all values that were to be loaded in the faulty chain can be inferred. However, because only one transition was applied, it might degrade the diagnosis resolution. The diagnostic test sequence in [13] was a functional sequence which brought the state sequence of DFFs in CUD as random as possible, and then an algorithm is employed to compare the expected signal-1 or signal-0 frequency of each flip-flop with observed singal-1 or signal-0 frequency on ATE. This technique was not a deterministic pattern generation method.
failure patterns. Then CFD figures out all possible fault candidates in terms of failure patterns. Step 2: Faults Differentiator (FD) generates a pattern to distinguish candidate fault pairs reported by CFD or by the responses of ATE in Step 3. Step 3: The generated pattern is applied to both the faulty chip on the ATE and the CUD to drop some suspect faults. The responses of ATE are feedback to Step 2 until the objective resolution is achieved.
3.2 Candidate Fault Detector 3.2.1.
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3.1. Diagnosis Flow Overview Circuit netlist
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Candidate Faults Detector (CFD) State Constrictions Most Confident Upper Bound Fault candidates Faults Differentiator (FD) Pattern Geration Candidate List
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Figure 1. Overall Pattern Generation Flow As shown in Figure 1, the overall diagnostic pattern generation flow can be divided into three steps. Step 1: Candidate Faults Detector (CFD) generates fault candidates for Fault Differentiator (FD). CFD builds a SAT model according to the circuit netlist and
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3. Proposed Diagnosis Method A SAT-based pattern generation method is proposed in this paper. This method can roughly be divided into two stages: the early stage and the post stage. At the early stage, most of fault candidates are dumped according to the failure pattern. At the post stage, the pattern is generated to distinguish the remaining faults and is applied to the ATE to observe the response.
Basic Idea
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Figure 2. Example of figuring out candidate faults CFD is responsible for pointing out all possible faults locations. Assume a circuit has seven scan cells and one of them has a SA1 fault shown in Figure 2. If logic 0 can be observed at cell 2 after the unloading, the downstream cells of cell 2 are fault free. Cell 2 is so called the lower bound and these downstream cells are called Full Confidence Cells (FCCs). FCCs are assigned to logic 1 in the launch cycle, then PIs, POs and ChUNDs are assigned to the observed values. Secondly, CFD builds a search space for the SAT engine. Afterwards, Iterations are carried on. For each of iterations, if the solver finds a solution then the solution is reported to FD and deleted from the search space. This process ends when no solutions can be found. 3.2.2. Add state constraints to the SAT engine. All of the downstream cells to the fault cell will be set to SA value during the loading process. Then, the downstream cells to the suspect positions are all assigned to the SA value and the upstream cells to the suspect faulty positions are all assigned to expected values. As shown in Figure 3 (a), each of AND gate stands for a fault candidate. Each downstream cell of the candidate fault cell drives one input of the AND gate. Each of the
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output of the AND gates drives an input of an OR gate. The output of the OR gate is set to one. That is to say, if there is an SA1, the output of the AND gate should be one because all the downstream cells of the fault cell are distorted to the SA value. Then the output of the OR gate should be logic 1. When SAT engine finds a solution, the corresponding AND gate is deleted. The process will go on until no solution can be found. SFP
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3.4 Symptoms Observing Strategy
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SF P: Suspect Faulty Position L B: L ow er Bo und (b) S A 0 (a) SA 1
Figure 3. State constrictions
3.3 Faults Differentiator The basic idea of Faults Differentiator (FD) is to generate patterns to distinguish a fault pair. When a pattern is applied to the CUD, the difference either on POs or on PPOs can be observed. PPOs POs Candidate A Pattern
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Figure 4. Basic model for differentiating fault pair
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represents that the pattern applied to A and B is the same pattern. Afterwards constrictions for PPI are added to ?. As shown in Figure 5, the candidate fault cell of A is cell 5 while the candidate fault cell of B is cell 2. The downstream cells of suspect cells are both set to the SA value. Both outputs of the XOR gates are 0. Please notice the scan cells between the suspect cell of A and the suspect cell of B are constriction free because if cell 5 has a real fault, no matter what loaded in cell 5 to cell 3, the fault distorts it to one.
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4. Experimental Results SO
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Let us explain the symptoms observing strategy with an example. Assume there are four candidates named A, B, C, D, which corresponds to a suspect scan cell in 7, 5, 3 and 1 respectively. And we assume the candidate C is the right answer. Firstly, the suspect faulty positions are arranged in the descent order. Assume a pattern can be generated successfully to distinguish A and B. When applying the pattern from the ATE to the failing chip, we find the fault is not in A. Moreover, because the values of downstream cells of cell 5 are all SA values, B, C and D are undistinguished by this pattern. Secondly, FD finds B and C are undistinguishable while B and D are distinguishable. Then FD adaptively makes an adjustment to generate a pattern to distinguish B and D, and then the pattern is applied to ATE. However, the observed outputs are unmatched with the expected pattern when the pattern is applied to the CUD, because fault in cell 3 distorts the pattern. Therefore, the fault is in C. In particular, as cell 3 distorts the pattern, a match may occur and indicates the fault is in D. In this case, FD adaptively generates an extra pattern to distinguish C and D. Notice B and D are distinguishable now, while C and D are also distinguishable.
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Figure 5. Constrictions for PPI Without losing of generality, we assume there are two candidate faults A and B as shown in Figure 4. The POs and PPOs of each circuit model are bit-XORed respectively and drive an OR gate. Thereafter, if there exits any difference, then the output of the OR gate should be one. PIs of A and B are XORed to drive the XOR. The output of the XOR gate is set to zero, which
Experiments are performed on ISCAS’89 benchmark circuits. Each of ISCAS’89 benchmarks is assumed to have only one scan chain. SA faults are injected into every DFFs then the failing outputs are taken from failure patterns and fed into our adaptive diagnostic pattern generation system. Table 1 compares the number of patterns needed to achieve the objective resolution. Best results are marked with bold face. We use the same definition of average resolution used in [10], that is, average number of faulty scan cells identified among all scan cells in a circuit. Data in the second column and in the third column are all obtained form [10]. The objective resolutions shown in the second column and in the third column are 10 while the objective resolution of our method shown in
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the last column is around 1. Actually, more patterns are needed to achieve the maximum resolution for [6] and [10], because the rest of the faults are hard faults.
is still increased. What is more, the proposed method does not use sequential ATPG, which shortens the CPU time of generating diagnostic patterns.
Table 1. The number of patterns to achieve objective
6. References
resolutions
CUD s5378 s9234 s13207 s15850 s38584
[1] S. Kundu, “Diagnosing Scan Chain Faults”, IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol.2, No.4, 1994, pp. 512-516. [2] J Hirase, N shindou, k.Akahori, "Scan Chain Diagnosis Using IDDQ Current Measurement", Proc. of ATS, 1999, pp. 153-157. [3] P Song, F Stellari, T Xia, A.Wegger, "A Novel Scan Chain Diagnostic Technique Based on Light Emission from Leakage Current", Proc of ITC, 2004, pp. 140-147. [4] J. L. Schafer, F. A Policastri, R J McNulty, "Partner SRLs for Improved Shift Register Diagnostics", Proc.of ITC, 1992, pp. 198-201. [5] S Edirisooriya, G Edirisooriya, "Diagnosis of scan path failures", Proc. of VTS, 1995, pp. 250-255. [6] R. Guo, S. Venkataraman, "A Technique for Fault Diagnosis of Defects in Scan Chains", Proc. of ITC, 2001, pp. 268-277. [7] K.Stanley, "High-accuracy flush-and-scan software diagnostic", IEEE Trans. Design & Test of Computers, Vol.18, 2001, pp.56-62. [8] A. G. Veneris, I. N. Hajj, S. Venkataraman, W. K Fuchs, “Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits”, Proc. of VTS , 1999, pp. 58-63. [9] Y-C Lin, F. Lu, K-T Chen, “Multiple-Fault Diagnosis Based on Adaptive Diagnosis Test Pattern Generation”, IEEE Trans. VLSI Systems, Vol. 26, 2007, pp. 932-942. [10] Y.-L. K, W. -S. Chuang, J. C.-M Li, "Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis", Proc. of ITC, 2006, pp. 1-9. [11] J.-J. Hsu, S.-Y. Huang, C.-W. Tzeng, “A new robust paradigm for diagnosing hold-time faults in scan chains,” Proc. of VLSI-DAT, 2006, pp. 171-174. [12] J C -M Li, "Diagnosis of single stuck-at faults and multiple timing faults in scan chains", IEEE Trans. VLSI Systems, Vol.13, 2005, pp.708-718. [13] J-S Yang, S-Y Huang, "Quick scan chain diagnosis using signal profiling", Proc. of ICCD, 2005, pp. 157-160. [14] Y. Huang, W. -T. Cheng, S. M. Reddy, C. -J. Hsieh, Y. T. Huang, "Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault", Proc. of ITC, 2003, pp. 319-328. [15] Y, Huang, “Dynamic Learning Based Scan Chain Diagnosis”, Proc. of DATE, 2007, pp. 510-515.
Resolution / Number of patterns [6] [10] Our work 10/100.2 10/1.7 1.2/1.8 10/110.4 10/2.3 1.3/1.9 10/204.8 10/1.7 1.3/1.9 10/122.6 10/1.3 1.2/1.9 10/108.0 10/1.7 1.1/2.0
Table 2 compares the CPU time when achieving maximum resolutions. As sequential ATPG is employed to achieve maximum resolution in [1] and [12] while our method takes the advantage of only using launch-capture process so it has the shortest CPU time. Table 2. CPU time to achieve maximum resolutions CUD s5378 s9234 s15850 s38584
CPU Time (second) [1] [12] Our work 18.68 11.09 4.32 91.73 393.84 8.95 360.27 1655.79 24.17 3409.70 31122.91 46.56
Table 3 compares the maximum diagnostic resolution of each listed method. The proposed method uses only one scan chain for each benchmarks circuits while [10] uses two scan chains. That is to say, for the proposed method, when the number of scan chains is doubled, the suspect scan cells are reduced by one half and more PPOs are available to observe the fault effect.
5. Conculusions This paper proposed an adaptive diagnostic pattern generation method for scan chain faults. The proposed method can diagnose faulty scan chains precisely and efficiently. Experimental results on ISCAS'89 benchmark circuits show that much fewer patterns are needed to diagnose faults and the diagnostic resolution
Table 3. Comparisons of Diagnostic resolution CUD s5378 s9234 s13207 s15850 s38584
[10] SA0 1.0 1.1 1.2 1.1 1.0
[12] SA1 1.0 1.1 1.2 1.1 1.0
SA0 4.3 15.4 NA 2.7 4.1
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SA1 2.5 5.7 NA 2.1 4.6
Our work SA0 SA1 1.1 1.3 1.3 1.3 1.3 1.3 1.2 1.2 1.1 1.1
