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Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing Yi-Hua Li, Wei-Cheng Lien, Student Member, IEEE, Ing-Chao Lin, Member, IEEE, Kuen-Jong Lee, Member, IEEE
Abstract—During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS’89 and ITC’99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss. Index Terms—At-speed testing, low capture power testing, scan-based testing, transition fault.
I. Introduction CAN-BASED testing is the most widely used design for test (DFT) methodology due to its simple structure, high fault coverage, and strong diagnostic support [20]. However, the test power of scan tests may be significantly higher than normal functional power because circuits may enter nonfunctional states during testing [29]. The test power required to load or unload test data with shift clock control is called
S
Manuscript received April 3, 2013; revised June 29, 2013 and August 13, 2013; accepted August 17, 2013. Date of current version December 16, 2013. This work was supported by the National Science Council of Taiwan, under Grant NSC 100-2221-E-006-177, Grant NSC 102-2221-E-006 -281, and Grant NSC102-2221-E-006-266-MY3. This paper was recommended by Associate Editor X. Wen. Y.-H. Li is with Storart Technology Co., Ltd., Taiwan (e-mail:
[email protected]). I.-C. Lin is with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail:
[email protected]). W.-C. Lien and K.-J. Lee are with the Department of Electronic Engineering, National Cheng Kung University, Tainan 701 Taiwan (e-mail:
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2013.2282281
shift power, and the power required to capture test responses with an at-speed clock rate is called capture power. Excessive shift power can lead to high temperatures that can damage the circuit under test (CUT) and may reduce the circuit’s reliability. Excessive capture power induced by test patterns may lead to large current demand and induce a supply voltage drop, known as the IR-drop problem [12]. This would cause a normal circuit to slow down and eventually fail the test, thereby inducing unnecessary yield loss. To estimate shift power and capture power, several metrics have been proposed. Among these metrics, the one employing the circuit level simulation may be the most accurate one [1]. However, this method is time consuming and memory intensive. Thus, most previous works use simpler metrics. The toggle count metric considers the state changes of nodes (FFs or gates) and the weighted switching activity (WSA) [7], [9], [10], [26] metric considers both node state changes and fanouts of nodes. Metrics that consider paths are also proposed. The critical capture transition (CCT) metric assesses launch switching activities around critical paths [24], and the critical area targeted (CAT) metric estimates launch switching activities caused by test patterns around the longest sensitized path [3]. In this paper, we will employ the WSA metric as it is highly correlated to the real capture power and has been used in most related work to determine power-safe test patterns [7], [9], [10], [26]. Also we will focus on the capture-power-safe patterns. To address the capture-safe-power problem, numerous methods have been proposed. These methods can generally be classified into hardware- and software-based methods. The hardware-based methods [1]–[5], [11], [13], [14] attempt to reduce test power by modifying the circuit/clock in test structures or by adding some additional hardware to the CUT. In [5] and [11], scan chain segmentation methods are proposed to reduce both shift and capture power. In [14], a partial launchon-capture (LOC) scheme is proposed to reduce the capture power, which allows only partial scan cells to be activated during the capture cycle. Some clock gating schemes have also been proposed to limit the test power consumption [1], [4], [13]. In general, the hardware-based methods effectively reduce test power. However, they may increase circuit area and degrade circuit performance, and may be incompatible with existing design flows. The software-based methods attempt to generate powersafe test patterns that will not consume excess power during testing by modifying the traditional automatic test pattern
c 2014 IEEE 0278-0070
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generation (ATPG) procedure [17], [18], [23] or by modifying predetermined test sets. These methods are generally based on the X-filling technique to assign fixed logic values to don’t care bits (X-bits) in test patterns to minimize test power dissipation. Devanathan et al. [17] and Wu et al. [18] modified the PODEM-based ATPG procedure by adding some power constraints to the backtrace and dynamic compaction processes to directly generate power-safe test sets. In [23], a low-capturepower (LCP) X-filling method is proposed and incorporated into the dynamic compaction process of the test generation flow to reduce the capture power. Although these methods can achieve a large reduction in capture power, they often increase the test data volume in comparison with that produced by conventional at-speed scan test methods due to the fact that during the dynamic compaction process, many X-bits that can be assigned to detect more faults are reserved to reduce capture power. Instead of modifying the ATPG procedure, some post-ATPG methods modify a given test set by using X-filling to reduce as much test power as possible [7], [10], [16] or to satisfy the power constraints [6], [21], [26]. Butler et al. [16] propose a method, named adjacency fill, which assigns deterministic values to the X-bits in line with the adjacent bit values to reduce shift power. For example, given the test pattern (1, X, X, 1, 0), the X-bits in this pattern are filled as (1, 1, 1, 1, 0). Remersaro et al. [10] proposes preferred fill to reduce the capture power. This method fills X-bits according to the signal probability of pseudo primary outputs (PPOs). In this approach, the X-bits in primary inputs (PIs) and pseudo primary inputs (PPIs) are first randomly filled with the oneprobability of 0.5. The output signal probability of each gate is then calculated and propagated to the PPOs. The logic values for X-bits in PPIs are then updated to 0 if zero has higher possibility in the corresponding PPOs; otherwise, they are set to one. All of the X-bits in PPIs are updated only once to achieve high scalability. Another method to reduce the capture power is to use the circuit’s steady states to fill X-bits [7]. This method, called ACF in [7], first fills X-bit randomly. Then, it applies a number of functional clock cycles starting from the scan-in state of a test vector to obtain the final states and uses these states to fill the X-bits to get more realistic patterns. Although both the Preferred Fill and the ACF methods can quickly assign the X-bits in PPI, they cannot ensure capture power safety because they do not consider the power constraint of the circuit. Another problem with the above two methods is that they try to assign values to all X-bits in all test patterns to reduce test power as much as possible. However, not all of the test patterns are power-risky [19]. For patterns that are power-safe, it is not necessary to reduce their capture power. Li et al. [6] proposed iFill to reduce both shift and capture power. This method tries to fill as few X-bits as possible to maintain the capture power within the power constraint. The remaining X-bits are then filled to reduce the shift power as much as possible. However, since power-risky patterns often have a small amount of X-bits, as illustrated below, the consumed power may be still higher than the capture power constraint even after X-filling.
Some other post-ATPG methods [21], [26] combine X-filling with X-identification [8] to reduce the capture power of fully-specified test sets. The X-identification process is conducted to identify the bits in power-risky patterns that can be arbitrarily assigned without degrading the fault coverage. These bits are then filled by using X-filling to reduce the capture power. These methods can reduce the capture power of power-risky patterns. However, similar to iFill, power-risky patterns tend to contain only a smaller number of X-bits, and thus, the efficiency of filling the X-bits of these patterns may not be significant. A. Overview of the Proposed Method Unlike previous methods that reduce the capture power by modifying power-risky patterns, this paper proposes modifying only power-safe patterns to address this issue. The rationale behind this strategy is illustrated in Fig. 1. Fig. 1(a) shows the relationship between the X-bit ratio and the switching activities, and Fig. 1(b) shows the relationship between the X-bit ratio and the detected fault count (in a log scale). It can be seen that the patterns that can detect more faults normally have larger switching activity and lower X-bit ratios, and the number of detected faults decreases drastically with increasing X-bit ratio. Hence, filling X-bits in power-risky patterns may not be efficient as they tend to have lower X-bit ratios. In contrast, power-safe patterns usually have higher X-bit ratios and many unused X-bits. Therefore, using the X-bits in powersafe patterns to detect faults within the power constraints may be more efficient than using those in power-risky patterns. Based on the above observation, this paper proposes a novel test pattern determination procedure to determine a powersafe test set with the LOC clocking scheme. The proposed procedure contains two processes, namely, test pattern refinement and low-power test pattern regeneration. Given a pregenerated compacted partially-specified test set without any power constraints, the power-risky patterns are all dropped. This will make faults that were detected only by the powerrisky patterns become undetected. The test pattern refinement process then tries to properly fill the X-bits in the powersafe patterns such that the power-risky faults can be detected with the power constraint still being satisfied. If some powerrisky faults remain undetected after this process, the low-power test pattern regeneration process is employed to generate more power-safe test patterns for these faults. B. Paper Contribution The contributions of this paper can be summarized as follows. 1) To the best of our knowledge, this is the first work that refines the power-safe patterns rather than powerrisky ones to address the capture power problem. The experimental results show that more than 75% of powerrisky faults can be detected by refining the power-safe patterns. 2) The required test data volume is less than the original test data volume in most cases. This is because our proposed procedure discards power-risky patterns and
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At-speed scan testing with LOC scheme.
II. Preliminaries This section first describes the LOC clocking scheme, which is widely used to detect transition faults in scan-based designs and the capture power problem. Then, it introduces the power metrics employed in this paper to verify the effectiveness of the proposed procedure. Fig. 1. Relationship between X-bit ratio, detected fault count, and switching activity for s38417 test patterns. The patterns are filled with ACF. (a) Relationship between X-bit ratio and switching activities. (b) Relationship between X-bit ratio and detected fault count.
does not require many new patterns to detect powerrisky faults. Experimental results show that the test data volume can be reduced by 12.76% on average under some power constraints. A few cases with strict power constraint have a slight test data volume increase (0.57% increase on average). 3) The capture power reduction ratio of the proposed procedure is not influenced significantly by the X-bit ratio in the patterns. This is because instead of filling X-bits in the power-risky patterns to reduce capture power, powerrisky patterns are discarded and power-safe patterns are refined to detect power-risky faults. Experimental results show the peak capture power is 27.7% to 53% less than that of ACF. 4) Extensive experiments are conducted to evaluate the effectiveness of the proposed procedure. Experiments with various power thresholds of 15% and 20% of the maximum weighted switching activity (WSA) as well as the functional peak WSA are conducted. Experimental results show that the proposed procedure can effectively address the capture power issue with little or no loss of fault coverage. The rest of this paper is organized as follows. Section II provides the preliminaries. Section III presents the main idea of this paper and the details of the proposed test pattern determination procedure. Experimental results and comparisons are given in Section IV. Finally, conclusions are given in Section IV.F.
A. Capture Power Problem in Scan-Based At-Speed Testing The architecture of the scan-based design and the LOC clocking scheme are shown in Fig. 2. Depending on the scan enable signal, the circuit operates in either shift mode or capture mode during testing. In shift mode, where SE is one, the test pattern is shifted into scan cells by a series of low-speed test clock pulses to initialize the circuit state. Once the pattern is shifted in, the circuit operates in capture mode, where SE is 0. One clock pulse is then applied to the circuit to create the transition for the target faults, and another clock pulse is then used to capture the test response from the combinational logic of the circuit using the at-speed functional clock. These two consecutive clock pulses include a launch cycle (L) and a capture (C) cycle, as shown in Fig. 2. Finally, the test response in the scan cells is shifted out for observation with SE asserted, and the next test pattern is shifted into the scan cells at the same time. During the LOC tests, the test pattern may cause excessive switching activity at the launch cycle, leading to large current demand and increased IR-drop. Increased IR-drop may increase the gate delay and lead to an incorrect test response being captured at the capture cycle. An incorrect response will cause the circuit to be identified as defective, which results in test-induced yield loss and increased cost. Therefore, to prevent such test-induced yield loss, it is important to ensure capture power safety during the launch cycle. B. Capture-Power Calculation and Safety-Checking As mentioned before, in this paper the WSA metric is used to calculate the circuit’s switching activity. The WSA of a gate is the number of capture transitions (t i ) at the gate multiplied
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by (gate’s fanout + 1). If a transition (0 to 1 or 1 to 0) occurs at gate i, t i is set to 1; otherwise t i is set to 0. If the gate is connected directly to a primary output, then its fanout is set to 0. The WSA of whole circuit for one test pattern is the sum of the WSA for each gate in the circuit, shown as follows: ti ×(fanouti + 1). WSA = ∀gatei
This WSA is called the maximum WSA, since all of the gates in the circuit transit in the launch. Note that when calculating the capture power of partiallyspecified test patterns, it is necessary to estimate the number of transitions caused by the X-bits at the internal gates. A simple method is to assign a weight to the transition (t i ) of each X-bit to calculate the switching activity with the previously mentioned power metrics. However, it is difficult to determine a proper weight for an X-bit. If the weight of X-bits is too large, then a power-safe pattern may be incorrectly regarded as a power-risky pattern, and vice versa. Another method is to fill the X-bits with 0 or 1 and then to calculate the capture power of patterns. There has been extensive research on X-filling techniques, as mentioned in Section I. In this paper, the ACF X-filling technique is used to temporarily fill the X-bits and calculate the capture power of partially-specified test patterns. The reason to choose the ACF X-filling technique is that the obtained capture power is lower than most other X-filling techniques [7], and thus, is a good candidate to calculate the capture power of partially specified patterns before using our proposed technique. III. Capture-Power-Safe Test Pattern Determination This section first uses a simple example to illustrate the main idea of the proposed procedure. Then, it describes the overall flow and its details. A. Main Idea The main idea of this paper is to utilize the X-bits in power-safe patterns to detect as many faults that are previously detected only by power-risky patterns as possible. If there are still undetected faults, then a low-power pattern generation process is used to generate patterns to detect the remaining faults. The following is an example to illustrate the main idea. Considering the circuit in Fig. 3, three transition faults, f 1 , f 2 , and f 3 , are detected by two pattern pairs P1 = < v1 ,v2 > = < (X, X, 1, 0, 1, 0), (X, X, 1, 1, 0, 0) > and P2 = < v3 , v4 > = < (0, X, 1, X, X, X), (1, X, 1, X, X, X) > . When pattern P1 is applied to the circuit, the output values of gates N2 , N4 , N6 , and N7 will switch and faults f 2 and f 3 can be detected by P1 . When pattern P2 is applied to the circuit, the output values of gate N5 will switch and fault f1 can be detected by P2 . The capture powers of P1 and P2 calculated using WSA are 6 (=2 + 2 + 1 + 1) and 1 (because gate N5 , N6 , and N7 are each connected to an output directly, and their fanouts are set to 0), respectively. If the power threshold Pth of this circuit is set to five and all of the wires with an X-signal have no transitions, the WSA
Fig. 3. Example of two partially-specified pattern pairs in the original ATPG test set to detect the faults f 1 (N5 slow-to-rise), f 2 (N7 slow-to-fall) and f 3 (N2 slow-to-rise). (a) Partially-specified pattern pair P1 detects f 2 and f 3 . (b) Partially-specified pattern pair P2 detects f 1 .
of P1 is higher than Pth , and the WSA of P2 is lower than Pth . Then, P1 is a power-risky pattern and P2 is a power-safe pattern. Based on our main idea, pattern P1 is dropped since its WSA is higher than Pth . Now, f2 and f3 become undetected. To avoid fault coverage loss, the power-safe pattern P2 is refined to detect more faults. If the refined P2 < (0, X, 1, X, 1, 0), (1, X, 1, X, 0, 1) > can detect f 2 , as shown in Fig. 4(a), the WSA of the refined P2 becomes 4 (=1 + 2 + 1). Now, the refined P2 can detect both f 1 and f 2 without violating the power threshold. It should be noted that the capture power of the refined power-safe pattern also increases because the power-safe pattern detects more faults (the WSA of P2 is 1 in Fig. 3(b), but the WSA of the refined P2 in Fig. 4(a) is 4). Therefore, to ensure that the WSA of the refined pattern does not exceed the power threshold, it must be calculated and checked again. Since f 3 remains undetected, the fault coverage is still less than the original. In order to recover the fault coverage loss, another power-safe pattern, P3 = < v5 , v6 > = < (X, X, 1, 0, X, X), (X, X, 1, 1, X, X) > , can be generated to detect f 3 , as shown in Fig. 4(b). By using the two power-safe pattern pairs, refined P2 (WSA = 4) and P3 (WSA = 3), all three faults can be detected without test data inflation, loss of fault coverage, and capture power issues. B. Overall Flow of Proposed Procedure Based on the main idea, a technique is proposed to determine a test set such that the power constraint is satisfied and the test data inflation is minimized. Fig. 5 shows an overview of the proposed capture-power-safe test pattern determination
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Fig. 4. Two new pattern pairs detect the faults f 1 (N5 slow-to-rise), f 2 (N7 slow-to-fall), and f 3 (N2 slow-to-rise). (a) Refined P2 that detects f 1 and f 2 . (b) New pattern pair P3 that detects f 3 . Fig. 5. Overview of proposed capture-power-safe test pattern determination procedure.
procedure. The inputs to this procedure include a pregenerated partially specified test set T for the LOC test, a list F of transition faults that are detected by T, and a predefined power threshold Pth to determine whether a pattern is power-risky. In order to obtain the power-safe patterns T s and the powerrisky fault list F r , at step , the capture power of each pattern in T is calculated and compared with Pth . The power-risky fault list F r is the list of faults that are only detected by power-risky patterns. To get a deterministic capture power of the partially specified pattern, the X-bits must be temporarily filled with zero or one. In the proposed procedure, the ACF technique is used to fill these X-bits temporarily to calculate capture power. If the pattern’s capture power is less than Pth , the pattern is added into T s ; otherwise, the pattern is dropped. The faults that are only detected by the power-risky patterns are identified by fault simulation using T s and F. These powerrisky faults are added into F r . Note that there may exist some power-safe patterns that can detect power-risky faults in F r but are not part of the original test set. Thus it can only be said that these faults are detected only by power-risky patterns in the original test set. The obtained power-safe test set T s and power-risky fault list F r will then serve as the inputs to the test pattern refinement process (step ). In the test pattern refinement process, values are assigned to X-bits of power-safe patterns in T s under the Pth limitation to detect as many power-risky faults in F r as possible. After this step, a fully specified power-safe test set T ms and an undetected fault list F u are determined. If the refined powersafe test set (T ms ) detects all of the power-risky faults, the pattern determination procedure is complete. Otherwise, the
low-power test pattern generation (step ) is conducted to generate new power-safe test patterns to detect these faults. The newly generated power-safe test patterns are stored in T ns . The power-risky faults that still cannot be handled by the proposed procedure are considered as unresolved and are put into an unresolved fault list F ur . With the above processes, a power-safe test set, including the refined power-safe test set T ms and newly generated test set T ns , can be determined. The details of these processes are described below. C. Algorithm for Test Pattern Refinement Process The goal of the test pattern refinement process is to utilize the X-bits in power-safe patterns to detect as many powerrisky faults as possible. This process ends when there are no remaining faults in F r or all the power-safe patterns in T s have been refined. The pseudo code is shown in Fig. 6. In each iteration, an unrefined power-safe pattern is selected as sel− pt (line 2). Then, the X-filling is applied to sel− pt for detecting power-risky faults (line 3). In this step, a commercial ATPG tool is configured to keep the specified bits of sel− pt, and the ATPG tool generates a partially specified test set called candidate test set T c for power-risky faults. For example, if sel− pt is (1, 0, X, X, 1), the candidate test set T c may include P1 = (1, 0, 0, 0, 1) and P2 = (1, 0, X, 0, 1), but not P3 = (0, 0, X, X, 0) because the values of some specified bits of P3 are different from those of sel− pt. The capture power of each test pattern in T c is then calculated by using the power metrics discussed in Section II (line 4). After the capture power of each candidate pattern is obtained, the patterns with capture power higher than Pth are
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Fig. 7.
Fig. 6.
Pseudo code for test pattern refinement process.
removed from T c (line 5). If T c is not empty, a fully specified pattern that detects the most faults in F r is chosen as max− pt, and the faults detected by max− pt are dropped from F r (line 7–8). The pattern max− pt is then copied to sel− pt, and sel− pt becomes fully specified and is marked as refined (line 9– 11). The fault list F r is checked if it has any power-risky faults. If F r is empty, the remaining unrefined power-safe patterns in T s are replaced with the corresponding prefilled patterns in Step 1 these patterns are added to T ms . Then, the refinement process is terminated. Otherwise, the next pattern will be selected for modification (line 12–14). If some power-risky faults still remain undetected after the while loop, these faults will be put in the undetected fault list F u (line 17–19), which will be processed by the low-power test pattern generation process, which is discussed in the next section. In summary, after the test pattern refinement process, a refined fully specified power-safe test set T ms is obtained. D. Algorithm for Low Power Test Generation Process The low-power test generation process attempts to generate a new power-safe test set to detect all the undetected faults and minimize the test data inflation at the same time. In
Pseudo code for low-power test pattern regeneration process.
order to achieve this goal, this process uses a dynamic data compression flow [20]. The pseudo code is shown in Fig. 7. In this process, a commercial ATPG tool is first used to generate a compact partially specified test set T tmp for F u (line 2). After the capture power of each pattern in T tmp is calculated, the patterns with capture power greater than Pth are removed from T tmp (line 3–4). Similar to the refinement process, the pattern which detects most faults is selected as max− pt if T tmp is not empty (line 5–6). Then max− pt is refined by the test pattern refinement process in an attempt to increase its detected faults (line 7). These detected faults are dropped from F u and max− pt is added to the test set T ns (line 8–9). Note that at this moment the generated power-safe patterns may be unable to detect all faults in F u (line 10) because the generated patterns may only have a small number of X-bits due to dynamic data compression in ATPG. Therefore, the following steps consider only a small fraction of undetected faults for pattern generation based on the observation that the patterns generated for a smaller number of faults tend to have a larger number of X-bits and hence a higher chance to be power-safe. In the experiment, 10% of undetected faults are randomly selected from F u as F tmp (line 11–12). The ATPG tool then generates a partially specified test set T tmp and the capture power of each patterns in T tmp is calculated. The patterns with capture power higher than Pth are removed from T tmp (line 13–14).
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TABLE I
TABLE II
Information of ISCAS’89 and ITC’99 Circuits
Power-risky faults reduction With Test Pattern Refinement Only on ISCAS’89 Benchmark
If ATPG cannot generate any power-safe pattern for the current F tmp , the faults in F tmp will be added to an unresolved fault list F ur and removed from F u (line 16–18); otherwise, this process goes to line 6 to process the power-safe patterns generated for F tmp (line 15). This procedure is repeated until there are no faults in F u . Then, a newly generated power-safe test set T ns and unresolved faults F ur are obtained.
IV. Experimental Results The proposed procedure was implemented in the C language and a commercial ATPG tool was used in the procedure to generate test patterns. In order to quickly calculate the WSAs of patterns, an event-driven power calculator was implemented. The experiments were conducted on ISCAS’89 and ITC’99 benchmark circuits using a 2.5-GHz Intel Xeon CPU with 16 GB of memory on a Linux platform. These circuits were synthesized using a commercial DFT compiler. The statistics of these circuits are listed in Table I, where the columns |sc| and |F| list the number of scan cells and uncollapsed testable transition faults, respectively. The columns |T atpg | and X-bits% show the number of partially specified test patterns and the average percentage of X-bits in the initial test set T atpg , respectively. The column max WSA lists the circuit’s theoretical maximum WSA, which is obtained by assuming that all gates in the circuit are switched simultaneously. The fault list F and the initial test set T atpg were generated by a commercial ATPG tool. A. Test Pattern Refinement The effectiveness of the test pattern refinement process was investigated for power thresholds of 15% and 20% of max WSA [26]. The results for reducing the number of powerrisky faults by the test pattern refinement process are listed in Tables II and III. The columns |T s | and |F r | provide the initial number of power-safe patterns and the number of power-risky faults which are only detected by the power-risky patterns. The number of remaining power-risky faults after the process is shown in column |F u |. The reduction ratio of the number of power-risky faults in column |F r | Red (%) is calculated by (|F r | – |F u |) / |F r |*100.
From Table II, it can be seen that the number of powerrisky faults was reduced by 64.55% and 76.7% on average with the test pattern refinement process for power thresholds of 15% and 20% of max WSA, respectively. This means that refining the power-safe patterns can significantly increase the detection of power-risky faults given the power constraints. In Table II, the power-risky fault reduction ratios of many circuits are even higher than 90%. In particular, the reduction ratio for s13207 is 100% when the threshold is 20%, which means that refined power-safe patterns can detect all power-risky faults, and thus there is no need to generate new low-power patterns for this circuit. However, it can also be seen that for some cases the method is inefficient. For example, test cases s1423 and s35932 have very low reduction ratios (only 9.74% and 2.27% for 15% threshold, respectively). This is due to the initial numbers of power-safe patterns in s1423 and s35932 being extremely small; fewer than ten power-safe patterns can be used in these cases. Therefore, the refined power-safe test patterns cannot detect many power-risky faults. From Table II, it can also be seen that when the power threshold is increased, the number of power-safe patterns increases and thus more power-risky faults can be detected by refining power-safe patterns. The results for the ITC’99 benchmark are similar to those for ISCAS’89 benchmark, as shown in Table III. The average reduction ratios of power-risky faults are 67.04% and 79.83% for 15% and 20% of max WSA, respectively. In cases b17 to b19, it can be seen that power-risky fault reduction ratios are higher than 97%. The ratio reaches 100% when Pth is 20% of WSA. In cases b20 to b22, the power-risky fault reduction ratios are 26.9% to 39.6% when Pth is 15%, and 56.7% to 62.5% when Pth is 20%. This is also due to these cases having fewer power-safe patterns under the same power threshold. B. Low-Power Test Pattern Regeneration The effectiveness of the low-power test pattern regeneration process was examined next. This process is used to generate patterns to detect the undetected power-risky faults, F u . The newly detected faults are removed from F u and the patterns detecting these faults are added into T ns . The remaining faults are unresolved faults. Table IV shows the experimental results.
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TABLE III
TABLE IV
Power-Risky Faults Reduction With Test Pattern Refinement Only on ITC’99 Benchmar
Experimental Result of Low-Power Test Pattern Regeneration
The column |F ur | lists the number of unresolved faults that cannot be solved using the proposed low-power test pattern regeneration for a given Pth . The column |T ns | lists the number of newly generated power-safe patterns and the column |T all | lists the number of final power-safe patterns which is the sum of |T s | and |T ns |. The column # of PT (%) shows the ratio of the pattern number difference between Tall and Tatpg over |Tatpg |, i.e., (|Tall |-|Tatpg |)/|Tatpg |*100%. It can be seen that for most cases the proposed test pattern regeneration process can effectively detect power-risky faults in F u (F u for ISCAS’89 and ITC’99 are listed in Table II and III). This is likely due to most power-risky faults having been detected by the test refinement process and only a small number of power-risky faults being left. However, test cases s1423 and s35932 still have many power-risky faults after test pattern regeneration. This is because the power threshold setting for these two cases are too strict and thus many powerrisky patterns exist (96.8% and 98.4% of patterns are powerrisky for s1423 and s35932 when Pth is 15% of max WSA as shown in Table II). In the next section, we will discuss how to determine a more reasonable power threshold. Another special case is s38417. The final test pattern number |Tall | of case s38417 is 48.26% higher than |Tatpg |. The reason is that the regenerated patterns for this case have a quite high WSA. Therefore, each regenerated pattern cannot detect many faults, and more regenerated patterns are needed to achieve high fault coverage. When Pth is set at 20% of max WSA, the final pattern numbers, |Tall |, of all cases other than cases s1423 and s35932 are less than the initial pattern numbers, |Tatpg |. On average, Tall is respectively 9.65% and 6.27% less than Tatpg in ISCAS’89 and ITC’99, respectively, and almost no powerrisky faults are left. This is again due to the fact that many power-risky faults are detected by the test pattern refinement process and only a few power-risky faults are left. When Pth is 15% of max WSA, the final pattern number is larger than that obtained with Pth of 20% of max WSA, and in some cases is even higher than the initial pattern number. This is because when the power threshold is lower, more X-bits need to be specified for power reduction, which reduces the detectability of these patterns. Therefore, more power-safe patterns need to be generated to detect power-risky faults.
Fortunately, the total pattern numbers are just slightly larger than the original values in these circuits. C. Functional Peak Power Threshold In Section IV-B, the ISCAS’89 benchmark has two special cases (s1423 and s35932) with very small numbers of powersafe patterns that can be used to detect power-risky faults. This is because the power thresholds for these cases are too strict and the proposed procedure does not have sufficient power-safe patterns to detect power-risky faults. Therefore, how to properly choose the power threshold was explored. Wen et al. [21] indicated that the appropriate power threshold can be obtained by simulating the functional peak power of the circuit. We thus simulate one million functional patterns for each circuit. The peak capture power of each functional pattern, called functional peak WSA, was calculated. The results are shown in Table V. Table V compares 15% of max WSA, 20% of max WSA, average WSA, and functional peak WSA. It can been seen that both functional peak WSA and average WSA are larger than or close to 20% of max WSA for most cases. Therefore, setting the power threshold as 20% of max WSA may be too low and may result in many power-risky patterns. If the power threshold is set too low, the number of power-safe patterns may be insufficient to detect many power-risky faults. Also, s1423 and s35932 are two special cases that have high functional peak power and few power-safe patterns. Therefore, it is difficult to generate power-safe patterns to detect the power-risky faults with 15% and 20% of max WSA. This explains why both cases still have many remaining powerrisky faults. Note that test cases s5378 and s38584 also have functional peak WSA values larger than 20% of max WSA but only few power-risky patterns are left. This is because functional peak WSA of both cases only occurs on few patterns and most patterns are still power-safe (in s5378, 65.2% of patterns
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TABLE V
TABLE VII
Comparison Between Different WSAs
Power-Risky Fault Reduction of ACF and Test Refinement Process Only
TABLE VI Experimental Results When P th Is Functional Peak WSA
TABLE VIII Test Data Volume and Fault Coverage of ACF and Proposed Procedure Under Various P th When using WSA Power Metric
are power-safe and in s38384, 94.2% of patterns are powersafe when Pth is 20% of max WSA). Therefore, the proposed procedure can still detect most power-risky faults in these two circuits. Table VI shows the experimental results when the power threshold was set to functional peak WSA. It can be seen that all the power-risky faults were detected with the proposed procedure in all cases. The test data volume was reduced by 12.76% on average. The results show that setting an appropriate power threshold can provide sufficient power-safe patterns to eliminate all power-risky faults and reduce the test data volume at the same time. D. Comparison of Proposed Procedure and ACF The section compares the power-risky fault reduction ratio, test data volume and fault coverage of ACF[7] and the proposed procedure. First, ACF is compared to the proposed test pattern refinement process in Table VII. Next, ACF is compared to both proposed test pattern refinement and test pattern regeneration in Table VIII. From Table VII, ACF can reduce power-risky faults by 33.32% and 42.94% on average under the two power thresholds for the ISCAS’89 benchmark, and the proposed test pattern refinement process can reduce power-risky faults by 64.55% and 76.62%, which are 31.23% and 33.68% higher, respectively. Similarly, in the ITC’99 benchmark, the proposed test pattern refinement process can reduce power-risky faults
by 67.04% and 79.83% when the Pth is 15% and 20% of max WSA, which are 21.18% and 27.7% higher than those for ACF, respectively. This is expected because ACF fills the X-bits only to reduce the capture power of both power-safe and powerrisky patterns. Since some patterns are already power-safe, it is not necessary to reduce their capture power. In the proposed refinement process, only power-safe patterns are refined to detect power-risky faults. Therefore, more power-risky faults are reduced. Table VIII compares test data volume and fault coverage of ACF and the proposed procedure (which includes both test pattern refinement and test pattern regeneration) under two
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TABLE IX Peak Capture Power (WSA) Reduction Ratio. The Reduction ratio Is Compared to Random Fill
power thresholds. Note that the term fault coverage here refers to the percentage of detectable faults that are detected, which is often called test efficiency in the literature. The column FC % lists the fault coverage of T all , and the column |T all | % lists the reduction ratio of the proposed procedure compared to the |T all | obtained using ACF. It can be seen that the fault coverage of the proposed procedures is similar to that of ACF. However, the test data volumes for the proposed procedure are 20.16% and 21.63% less than those of ACF on average for the ISCAS’89 benchmark when Pth is 15% and 20% of max WSA. Clearly, the test data volume reduction ratio is closely related to the number of power-risky patterns. If there are fewer power-risky patterns, the test data volume reduction ratio will be less. This can be seen from the experimental results of the ITC’99 benchmark, where the test data volume are reduced by only 5.59% and 4.10% since the test cases in this benchmark have fewer power-risky patterns.
E. Peak Capture Power reduction In the proposed procedure, power-risky patterns are discarded and power-safe patterns are used to detect powerrisky faults. Since power-risky patterns are discarded, the peak capture WSA of the procedure is significantly reduced. Table IX compares the peak capture power of random fill, ACF, and the proposed procedure. The peak capture power is measured in WSA and the reduction ratio is compared to random fill. It can be seen that ACF can reduce peak capture power by 15.57% on average in the ISCAS’89 benchmark. The proposed procedure can reduce peak capture power by 68.6% and 58.18% under the two power thresholds, which are 53.03% and 42.61% higher. For ACF, if the patterns that cause the peak capture power have only a few X-bits, only a small ratio of capture power can be reduced. For example, ACF does not reduce the peak
capture WSA of case s35932. This is because the pattern that generates the peak capture WSA does not contain any X-bits. However, the proposed procedure does not have this problem because it removes power-risky patterns. Therefore, the proposed procedure produces a much greater reduction in peak capture power. Another significant result is that since ACF does not consider the power threshold, it does not guarantee that its results can meet the power budget in real circuits. From Tables V and IX, it can be seen that after ACF, the peak capture WSA was still higher than the functional peak power. The last three columns list the runtime in hours, how many times the ATPG tool runs and the fraction of time spent in the ATPG tool. The proposed procedure under different power thresholds had different runtimes, but only the largest one is listed. The runtime of ACF is about several minutes because it attempts to reduce capture power by X-filling and does not consider the power threshold. It can be seen that the overall runtime of our procedure ranges from 10 minutes to 2.17 days. The long running time is because our implementation has to invoke a commercial ATPG tool many times to perform all Xfilling and fault simulation processes. As shown in Table IX, on average more than 90% of time is spent on the ATPG process. As we are unable to incorporate our procedure into the commercial ATPG tool, the most time-consuming part is on the file I/O and data structure reconstruction for the ATPG tool, which typically consume more than 85% of the ATPG time in our experiments. The run time can be significantly reduced if our proposed method is integrated in the ATPG tool or a more efficient ATPG tool is used. Nevertheless, since this is a one-time job, once the power-safe patterns are determined, there is no need to execute the proposed procedure again. F. Pattern Size Table X compares the number of partially specified and fully specified patterns generated by the commercial ATPG tool
LI et al.: CAPTURE-POWER-SAFE TEST PATTERN DETERMINATION FOR AT-SPEED SCAN-BASED TESTING
TABLE X Pattern Number Comparison
used in our experiment. The column |Tatpg | shows the number of the original partially specified test pattern and the column |Trand | random fill shows the number of fully specified test patterns when the random fill technique is used. Our pattern number |Tatpg | is larger than the pattern number |Trand | random fill because our patterns contain X-bits, but the differences are not significant in most cases. We also show the number of safe patterns generated by our method in the column |Tall | when 20% of max WSA is used (from Table VIII). It can be seen that |Tall | is quite close to |Trand |. In some cases |Tall | are even smaller than |Trand |. We do find that that for b17, b18, and b19, |Tatpg | is much larger than |Trand |, This is because the X-bit ratios of these circuits are quite large (over 91%) and most patterns in |Tatpg | are safe patterns. Since all safe patterns will be included in Tall , our method does not reduce the number of patterns well. If the number of X-bits can be reduced when generating Tatpg , then |Tall | can also be reduced. Another way to deal with this problem is to explore the detectability of a safe pattern on not only the faults detected by risky-patterns, but also on those faults detected by other safe patterns. By this way, we can do some test compaction among the safe patterns and may further reduce the number of safe patterns. V. Conclusion This paper proposed a novel capture-power-safe test pattern determination procedure to address the capture power problem. Unlike previous methods, the test pattern refinement process in the proposed procedure refines power-safe patterns to detect the power-risky faults and discards the power-risky patterns to ensure the capture power safety. The capture power of newly generated patterns is also guaranteed to be under the power constraints. The experimental results show that more than 75% of power-risky faults can be detected by refining the powersafe patterns, and that the required test data volumes can be reduced by 12.76% on average under the appropriate power constraints without fault coverage loss. References [1] N. Ahmed, M. Tehranipoor, and V. Jayaram, “Transition delay fault test pattern generation considering supply voltage noise in a SOC design,” in Proc. Design Autom. Conf., 2007, pp. 533–538
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[26] M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, and H. Wunderlich, “SAT-based capture-power reduction for atspeed broadcast-scan-based test compression architectures,” in Proc. Int. Symp. Low Power Electr. Design, 2011, pp. 33–38. [27] X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. A. Kochte, S. Kajihara, P. Girard, and M. Tehranipoor, “Power-aware test generation with guaranteed launch safety for at-speed scan testing,” in Proc. VLSI Test Symp., 2011, pp. 166–171. [28] Y. Yamato, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara, “A GA-based method for high-quality X-filling to reduce launch switching activity in at-speed scan testing,” in Proc. Pacific Rim Int. Symp. Dependable Comp., 2009, pp. 81–86. [29] Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. VLSI Test Symp., 1993, pp. 4–9.
Yi-Hua Li received the B.S. degree in computer science from Chang Gung University, Taoyuan, Taiwan, in 2010, and M.S. degree in computer science and information engineering from National Cheng Kung University, Tainan, Taiwan, in 2013. She is currently with Storart Technology Co., Ltd., Hsinchu, Taiwan. Her current research interests include CAD for very large-scale integration (VLSI) and low power testing.
Wei-Cheng Lien (S’10) received the B.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 2007, where he is currently pursuing the Ph.D. degree in electrical engineering. His current research interests include design for testability, diagnosis, test compaction, and logic BIST.
Ing-Chao Lin (M’09) received the M.S. degree in computer science from National Taiwan University, Taipei, Taiwan, and the Ph.D. degree from the Computer Science and Engineering Department, Pennsylvania State University, University Park, PA, USA, in 2007. From 2007 to 2009, he was with Real Intent, Inc., where he was engaged in automatic timing exception verifier, and since 2009, he has been with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan, where he is currently an Assistant Professor. His current research interests include very large-scale integration (VLSI) design and computer-aided design for nanoscale silicon, low power testing, and computer architecture.
Kuen-Jong Lee (S’84–M’91) received the B.S., M.S., and Ph.D. degrees from National Taiwan University, Tainan, Taiwan, University of Iowa, Iowa City, IA, USA, and the University of Southern California, Los Angeles, CA, USA, respectively. He was with the Faculty of National Cheng Kung University (NCKU), Tainan, Taiwan, in 1991, where he is currently a Professor with the Department of Electrical Engineering. He served as the Director of the NCKU SOC Research Center from 2008 to 2010 and was elected as the fourth President of the Taiwan Integrated Circuit Design Society. He holds six ROC and five U.S. patents. His current research interests include SOC testing/debugging, scan-based design, and electronic system level design and test. Dr. Lee has served on technical program and organization committees of several professional conferences, including Program Chairs and General Chairs of Asian Test Symposium, VLSI Design, Automation and Test Symposium and VLSI Test Technology Workshop. He also served as the first Chairman of the IEEE Circuits and Systems Tainan Chapter. He received the Exceptional Contribution Award from the National Applied Research Laboratory in 2007 and the Best Project Achievement Award from the National Science Council of Taiwan in 2007 and 2013. He has also won the Golden Medal of the Golden Silicon Award in 2013 and the Best Paper Awards of the 2011 VLSI-CAD Symposium and the 2012 VLSI Test Technology Workshop. He has worked on many aspects of the design and test of VLSI circuits.
