The aging sensor is based on a new flip-flop with built-in logic that predicts the errors by monitoring long-term performance degradation of CMOS digital systems ...
Adaptive Error-Prediction Aging Sensor for On-Line Monitoring of Performance Errors C. V. Martins, J. Pachito, J. Semião
I. C. Teixeira, J. P. Teixeira
Univ. of Algarve / INESC-ID Lisbon Faro, Portugal {cvmartins, a38318, jsemiao}@ualg.pt
INESC-ID Lisbon / IST-UTL Lisbon, Portugal {isabel.teixeira, paulo.teixeira}@ist.utl.pt
Abstract—This paper presents a new aging sensor architecture for error prediction of performance errors in synchronous digital circuits. The aging sensor is based on a new flip-flop with built-in logic that predicts the errors by monitoring long-term performance degradation of CMOS digital systems. The main advantage is that the sensor’s long-term degradation effects increase its sensitivity to performance error prediction. Moreover, the reduction of the power-supply voltage (V) and the increase of the temperature (T) also make the sensor to increase its sensitivity, making the sensor to adapt its monitoring capability with aging and VT variations. Performance failure prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, or even by a worst-case operating condition (namely, V and/or T). Extensive SPICE simulations allowed achieving a new flip-flop with additional aging sensor capability, however with negligible performance degradation, because the sensing circuitry is out of the signal path. Simulation results are presented for two CMOS technologies (65nm and 22nm), using Berkeley Predictive Technology Models (PTM). It is shown that PVTA (Process, power supply Voltage, Temperature and Aging) variations on the sensor enhance error prediction capability. Keywords-aging sensor; performance failure prediction; NBTI; on-line monitoring.
I.
INTRODUCTION
In nanometer technologies, variability is becoming one of the leading causes for chip failures and delayed schedules [1], and causes increasing uncertainty in system behavior, namely on its performance. Hence, lower circuit’s dependability and reliability [2][6] are to be expected, when moving to low nanometer range. Clearly, PVTA variations degrade circuit’s dependability. Conservative approaches, with wider relative circuits’ time slacks, are required when technology is down scaled [7]. Semiconductor aging [4] causes long-term performance degradation, and may activate physical defects latent in production. NBTI has been identified as the dominant longterm effect in nanometer CMOS technologies [5][8][9]. It primarily affects PMOS transistors, increasing |VthP| along the time. This will ultimately cause a delay fault. For safety-critical (e.g., automotive) and mission-critical applications (e.g., space), this must not occur. However, these products are designed to operate in harsh environments and for long life
cycles (e.g., 10 years for cars, 15 years for trucks, typically). Hence, performance failure prediction must be implemented, and long-term performance drifts must be constantly monitored (especially if a worst-case VT scenario exists when cumulative aging effects are presented). The purpose of this paper is to present an adaptive error prediction aging sensor, to be used in a performance failure prediction methodology, for safety-critical, high-performance systems. Key flip-flops (FF) are selected and replaced with the new Adaptive Error Prediction Flip-flop (AEP-FF), to include the error prediction functionality and locally monitor FF data input late transitions, reducing to a minimum the global interconnections for aging sensor insertion. The observation (or guard-band) interval, tg, at the end of the clock cycle, is defined by design, so the time period in which abnormal delays are observable is user’s defined. However, its sensitivity (measured by tg) increases with its PVTA variations, and the sensor FF will adapt and increase the guard-band, as circuit variability increases with aging and worst-case VT operation. Preliminary results are also shown for a novel proprietary tool, AgincCalc, that calculates the probabilities of transistors’ workload for a given target library. Using previous works on NBTI effects ([10][11][22][23]), this tool calculates the PMOS threshold voltage degradation, ΔVthP, and generates a spice description file with the corresponding NBTI prediction effect, for a given aging time. The paper is organized as follows. Section II briefly reviews previous work. In section III, the proposed aging sensor architecture is presented. Section IV describes the methodology, including sensor characteristics, sensor insertion and sensor activation. In section V, simulation results are presented. Finally, conclusions are summarized in section VI. II.
PREVIOUS WORK
Solutions to enhance tolerance to VthP degradation have been presented in [4][11], and [8] shows how design optimization can restrict NBTI performance degradation. Moreover, various aging sensor topologies have been presented, to globally detect circuit’s performance degradation ([12][13][14][15]), or to locally anticipate system failure before it really occurs ([7][16][17][18][19]). Nevertheless, the proposed solutions to locally anticipate system failure have limitations, namely: (1) sensors must have
better performance and lower sensitivity to PVT variations than the CUT (Circuit Under Test); (2) or the methodology is based in monitoring time interval (guard-band) that needs to be synchronous with the clock; (3) or the sensors are active in predefined periods during which the CUT critical paths may not be activated. The present paper presents a novel FF architecture with built-in aging sensor, based on the previous work done in [18]. However, a different approach is used, in order to deal with the reported limitations of previous aging sensors topologies. The new aging sensor is based on a new flip-flop architecture, which includes the aging sensor functionality. The robustness of the new flip-flop and sensor is also evaluated. III.
B. The Adaptive Error-Prediction Flip-flop The topology of the proposed Adaptive Error-Prediction Flip-flop (AEP-FF) is shown in Fig. 2. The Delay Element (DE) delays data signals captured at the Master Latch output, during CLK low state. The Stability Checker (SC) analyzes data transitions during CLK high state. This way, the DE propagation delay is the effective observation (or guard-band) interval, tg, used by the sensor (tg = τDE). Late transitions at FF data input (propagated to the Master Latch output) will be identified by the SC. As it will be shown later, SC has on-state retention logic, to discard the use of an additional latch to store the aging sensor output signal (AS_OUT).
ADAPTIVE ERROR-PREDICTION AGING SENSOR
The maximum CUT clock frequency is limit by WCC (Worst Case Condition), as there is a need to insert a time slack, τslack, to guarantee CUT correct operation under the different design corners. Consequently, an aging sensor must monitor performance degradation locally, at key FF (Critical Memory Elements, CME), where synchronization errors start to occur. Aging sensor functionality must be integrated in these FF terminating critical or near-critical paths (CP). The sensor monitors late transitions at the FF’s data input, and uncover abnormal delays, regardless of their origin, e.g., caused by aging effects, or by physical defects activated by long-term operation, or even by a worst-case PVTA scenario. This is definitely an advantage for safety-critical systems. A. Error Prediction Procedure As mentioned, the purpose of the sensor is to monitor late transients in the data input of FF that terminate critical and near-critical paths. In previous works like [18], a guard-band time is defined at the end of the clock cycle, defining when FF data input transients are signalized as an error prediction (late transients). In this work, there is no signal explicitly defining a guard-band time. However, a virtual guard-band time, tg, exists, defined by the propagation delay time of a Delay Element, τDE. In fact, by placing the Delay Element (DE) inside the FF, at the end of the critical path, we obtain tg = τDE. PVTA variations induce increased delays in the CUT, increasing τ0, and in the DE, increasing tg (see Fig. 1-a). When a WCC produces a timing degradation such that τ0 + tg exceeds the clock period (TCLK), an abnormal propagation delay time is spotted as an unsafe delay, although not large enough to induce malfunction if τ0 < TCLK (see Fig. 1-b).
(a)
(b) Figure 1. Error-Prediction and sensor operation: (a) Nominal PVTA conditions, with no error predicted; (b) PVTA WCC and an error prediction.
Figure 2. Adaptive Error-Prediction Flip-flop topology.
Using the flip-flop data signal at the output of the Master Latch to drive the DE, instead of the FF input data signal, D, as in previous aging sensor architectures [16][17], simplifies DE design. Basically, the new delay element is a simple buffer that introduces a delay to create a virtual guard-band where late transitions at FF data input are signalized. Moreover, if PVTA variations occur in DE, this virtual guard-band will increase accordingly. It is possible to create a power-on state for the DE, and activate it in short periods, restricting power consumption and aging effects of the aging sensor. However, even when the sensing operation is always ON, the increased workload of the DE will cause sensor´s guard-band to increase as aging effects cumulatively degrade DE performance. This way, the sensor’s sensitivity is adapted with the cumulative aging degradation of the circuit. Another advantage is that the guard-band signal does not need to be distributed as a second balanced clock to the sensing FFs, as in [16][17]. The loading effect of the sensor is inside the FF; hence, it does not explicitly impact the signal path. In fact, experiments were carried out to determine the best location, inside the master latch, to connect the aging sensor (AS) circuitry. The best solution was connecting the AS circuitry at node Z (see Fig. 2), when compared with connections at nodes X or Y (the setup and hold times measured, tSU + tH, for connections at nodes X, Y and Z were, respectively, 55ps, 53ps and 52ps). C. The Delay Element Consider τDE as the propagation delay of the DE. Hence, tg = τDE Fig. 3 presents three typical DE architectures. These buffers have different delay capability and different aging performance degradations. The DE architecture should be chosen according to following factors: the clock frequency, the
τslack/TCLK ratio, the technology, and the sensor’s sensitivity (or the PVTA WCC where the sensor starts to flag a late transition). As an example, considering τslack/TCLK=30% and a 65nm Berkeley PTM technology, typically architecture (a) can be used for frequencies above 1GHz, (b) from 400MHz to 1GHz, and (c) bellow 400MHz. Moreover, as changing W/L transistors ratios also change the sensor’s effective guard-band, tg, the DE can be optimized by designed. Note that, unlike in [17][18][19], tg is not programmable, it is defined at design time. However, tg is adaptive with PVTA variations, enhancing sensor’s detection sensitivity. We refer it as a virtual guardband because there is no signal explicitly representing the observation interval. Each sensing FF will have its own unique PVTA-dependent guard-band (each local DE may age differently).
signal is triggering the beginning of the observation interval, tg. The end of the guard-band interval is ultimately limited by half the clock cycle (when CLK signal is high).
Figure 4. Stability checker architecture with on-retention logic.
IV. (a)
(b)
(c) Figure 3. Delay element typical architectures: (a) Low delay; (b) Medium delay; (c) High delay, .
D. The Stability Checker The novel Stability Checker (Fig. 4) is implemented with dynamic CMOS logic and has built-in on-retention logic. During CLK low state, and considering that AS_out signal is low, X and Y nodes are pulled up (making AS_out to stay low). When CLK signal changes to high state, M3 and M4 are OFF, and according to Delayed_DATA signal, one of the nodes X or Y changes to low. If, during the high state of the CLK, a transition in Delayed_DATA occurs, the high X or Y node is pulled down by transistor M2 or M5, respectively, driving AS_out to go high. From now on, M9 transistor is OFF. Hence, X and Y nodes are not pulled up during CLK low state, unless the active low RESET signal is active. X and Y nodes remain low, helped by transistors’ M3 and M4 activation during AS_out high state. For the RESET signal to restore the cell’s sensing capability, it must be active, at least during the low state of one clock period. The proposed SC architecture, with the on-retention logic implemented with transistors M3, M4, M8 and M9, does not need an additional latch to retain the SC output signal when it’s active. However, additional research must be pursued to analyze the SC operation in the presence of cross-talk noise, especially when CLK signal is activated, as false-positive errors may be signalized. Moreover, only FF’s internal clock
METHODOLOGY
The aging sensor methodology comprises (1) aging sensors (AS) characteristics, (2) sensor insertion technique, and (3) sensor activation. A. Aging Sensor Characteristics Valued AS characteristics are: low power consumption, low area overhead, low performance degradation, and sensitivity to PVTA variations (increasing tg as variability increases). Due to DE input location (at the Master Latch output), the performance degradation of the AEP-FF is negligible. Moreover, the design of the DE and the selection of which DE to use is crucial for the AS methodology. Therefore, the DE design and selection should be tuned during silicon validation, according to the clock frequency chosen and the expected AS characteristics. B. Sensor Insertion The sensor insertion technique should define a limited set of CME in the CUT where the FF input data should be monitored. In order to have a cost-effective delay monitoring, only signal paths with long propagation delay times will eventually be flagged as unsafe transitions. Hence, only critical paths (CP) or near-CP need to be monitored. Due to PVTA variability, a user’s defined safety margin (αsafe) is used as an AS insertion variable. AS insertion requires a preliminary analysis of the CUT’s propagation delay times with a Static Timing Analysis (STA) tool (e.g., PrimeTime™). Then, a DyDA tool [3] generates the CUTs delay map, identifying the critical paths ending the logic cones of each ME, and ranking them from the slowest to the fastest. However, the aging process may affect differently each path, and a near-critical path may become critical when the long-term effects degrade CUTs timing response. A second proprietary tool is used, AgingCalc, to calculate the probabilities of the workload for each PMOS transistor in the circuit, and predict the new VthP value for a given aging time (and for each PMOS transistor).
C. Sensor Activation In the proposed methodology, we assume that the overall DfT (Design for Testability) strategy will not be modified, just up-graded to include the on-line BIST technique materialized by AS insertion. Sensor insertion in selected CME can be viewed as a Test Point Insertion technique [24]. It enhances on-line performance observability. During normal circuit operation in product lifetime, as the sensor is always ON, there is an increased probability of critical path activation. However, this may not be the case. Hence, in the design phase, a set of test vectors must be generated, to validate the design, and the ability of the AS to detect unsafe delays. Design validation requires a functional test. Performance test (to activate the long signal paths, in order to verify if their delay should be signalized as unsafe) requires a structural test, namely a Path Delay Fault (PDF)-oriented test targeting the subset of long signal paths [24]. Automatic test generation for PDF detection on that limited set of signal paths can be carried out by a commercial ATPG tool. Functional and structural test can be merged. V.
SIMULATION RESULTS
Simulation results are presented for CUT1 (inverter chain creating a CP example) (figure 5) (PTM 65nm) and CUT2 (PM, Pipeline Multiplier) (PTM 65nm and 22nm [20]). For 65nm technology, a 1V nominal VDD is considered, with variations from 1.2V to 0.8V. For 22nm technology, a 0.8V nominal VDD is considered, with variations from 0.96V to 0.64V. T variations are restricted from 27ºC to 150ºC. WC (worst case) VT conditions are VDD=0.8V, T=150ºC for 65nm, and VDD=0.64V, T=150ºC for 22nm. Aging fault injection, by VthP modification, is performed by Spice VTHO parameter modulation. For CUT1 and CUT2 with 65nm technology, NBTI aging is assumed to equally degrade VthP of all PMOS transistors. For CUT2 with 22nm technology, VthP is modulated according to PMOS transistors workload probabilities, calculated with proprietary AgingCalc tool. 40 inverters Data_in
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Figure 5. CUT1 (40 inverters’ chain, creating a typical CP example).
Considering 65nm PTM CUT1 simulations with HSPICE, the propagation delay time of CUT1 CP at nominal conditions (NC) leads to 328ps (L-H transition). WC VT conditions lead to tpLH=805ps, which represents a serious degradation, as compared to nominal tpLH. The clock period is defined as Tclk=τ0+τslack, where τ0=tpLH+tSU, and tSU is the FF set-up time, namely tSU=39ps. Hence, τ0= 844ps. In order to accommodate process variations, a time slack was set as 30% of τ0. Therefore, Tclk = 1.1ns will guarantee correct operation under worst case PVT conditions. Simulations were carried out to compute propagation delay degradation due to NBTI-induced aging. The impact of up to 30% variations in |VthP| of the PMOS in the CUT on % variations of tpLH and tpHL was evaluated (Fig. 6): 30% VthP variation of leads to ΔtpLH= 16% at VT NC. Worst case VT scenario leads to higher delay degradation (35%). CP propagation delay degradation (%)
Spice simulations can then be performed to evaluate how aging can affect the selected paths. A second AS insertion variable is used, αcritical, to define the critical paths with more probability of inducing delay errors in the presence of PVTA variations. This second user’s defined safety margin (αcritical) determines which registers must be transformed into CME, by AS insertion (or FF automatic reconfiguration, using DyDA tool). In this work, we assume αsafe=80% and αcritical=90%, but these values should be tuned for each circuit implementation during silicon validation, to define the safe paths (with propagation delays in nominal conditions below αsafe×τ0) and the monitored paths (with propagation delays in PVTA WCC above αcritical×τ0).
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Figure 6. CP’s propagation delay variations (ΔtpLH and ΔtpHL) in CUT1 with aging (ΔVthP), for nominal (NC) and worst-case (WC) conditions.
For CUT1, AS insertion was carried out, with selective AEP-FF insertion, implemented with the DE shown in fig. 3-a) (with minimum-size PMOS transistors). The AEP_FF performance degradation was evaluated: only 5% set-up time degradation was measured (tSU_AEP_FF = 41ps) for WC conditions (when compared to TCLK, it’s irrelevant), while no hold-time degradation was measured (tHold_AEP_FF = 9ps). Error-prediction by the AEP-FF starts to occur for 10% degradation in VthP and for 9% degradation in the critical path propagation delay (L-H transition). The sensor continues its error-prediction until the error occurs (when tslack is violated). The sensor’s effective virtual guard-band, tg, was computed under VT variations (Fig. 7) (only L-H transition is shown, as H-L transitions’ results are similar) and under VthP aging variations (Fig. 8). Moreover, when analyzing tg variation with VTA variations (Figs. 7 and 8), unlike in [16][17], our proposed sensor increases the guard-band interval as variability in the circuit increases with V reduction and T and |VthP| increase. This is an important result, because VthP aging degradation, or V depletion, or T increase, unlike other aging sensor solutions, work in favor of the error-prediction methodology. In fact, the AS becomes more sensitive to CUT delay variations, as VTA variability increases. Previous works [16][17] put a heavy burden on AS design, to guarantee that the AS sensitivity to VTA variations does not reduce significantly the detectability window of the sensor. Furthermore, in [16][17][18] SC operation significantly reduces the effective tg of the sensor. In high performance circuits, the SC must also react fast to maintain the predictive
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error detection capability. In the proposed AEP-FF, the data signal that drives the SC is always stable, due to the fact that Delayed_DATA signal is analyzed at the output of the master latch of the FF. Hence, there is no limitation imposed by the eventually slow operation of the SC.
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Figure 7. AS effective guard-band variation (L-H transition). (a) under temperature variations; (b) under power-supply voltage variations. tg_HL( VDD=1V, T=27ºC) tg_LH( VDD=1V, T=27ºC)
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Figure 8. AS effective guard-band variation (L-H and H-L transitions) with aging (VthP variation), for nominal and WC conditions in CUT1.
CUT2 is a 2-stage, 4-bit Pipeline Multiplier (PM). PM is a 36 FF, 52 gate structure, 9 (8 data, 1 CLK) inputs, 8 outputs. Considering αsafe=80%, 9 CME are reported and 80 critical and near-critical paths are reported. Using as a first approximation that all the paths age equally, αcritical=90% is defined and 5 CME are needed. Note that more than one large delay path converge to the same FF. In fact, in this case, 23 long signal paths converge in 5 CME of the 20 FF at the end of pipeline stage 1. Fig. 9 depicts the WC propagation delay variation with NBTI-induced aging for the 5 most critical memory elements in CUT2 Pipeline Multiplier, implemented with 65nm PTM. After PM circuit reconfiguration, replacing the 5 CME with the AEP-FF, HSPICE simulations were performed with Tclk=780ps, where 60% corresponds to the propagation delay of the CP under WC conditions, with τslack=40%Tclk to accommodate WC PVT variations. Fig. 10 shows, for PM
For safety-critical applications, the sensor must provide reliable operation also in the presence of P (Process) variations. Monte Carlo (MC) simulations under WC VT conditions were carried out. In all MC simulations, a Gaussian distribution with +/-3σ variation of +/-10% of the nominal values is assumed [21] for 3 MOSFET parameters: Leff, tox and Vth. MC simulations were run varying MOSFET parameters in the CUT and in the sensor’s transistors. For each set of MC simulations, 30 runs were performed. Under P variations, detection on fast samples requires high VthP degradation. We define the Detection Probability (DP) as the percentage of the 30 MC runs that detect the abnormal delay. Fig. 11 presents MC results for DP in the 5 CME of CUT1. Monte Carlo Results for Detection Probability (DP) 100% Detection Probability (%)
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Figure 11. Monte Carlo statistic results for first detections at the 5 CME for percent variations of VthP degradation variations, in CUT2 under WC VT conditions.
Using a 22nm PTM technology implementation of CUT2, HSPICE simulations were carried out to obtain the impact on circuit’s critical paths delays of the AgingCalc aging prediction. Based on transistors’ workload probabilities, a ΔVth value was obtained for each PMOS transistor, for each year.
Preliminary results presented in Fig. 12 show that there is no significant difference on the aging of the critical paths of each CME (in this case, using an equal VthP modulation for the transistors is a good approximation). Moreover, the delays of the CPs have small degradation with aging, due to transistors with low ON probability. However, these assumptions are dependent on circuit’s topology and functionality.
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VI.
CONCLUSIONS
In this paper, a new Adaptive Error-Prediction Aging Sensor was presented. It was shown that sensor’s sensitivity increases with VDD depletion, T increase and NBTI-induced aging. A new flip-flop was also proposed, an Adaptive ErrorPrediction Flip-flop (AEP-FF), to include the AS functionality and perform the local monitoring of late transients at FF data input signal. The AEP-FF includes new DE and a new SC architecture with on-retention logic feature. The AEP-FF architecture reduces the performance degradation overhead due to sensor insertion, as compared to previous solutions. Moreover, SC operation does not limit the effective detection window of the sensor, as in previous AS topologies. As sensors age, sensor’s performance degradation works in favor of the predictive error detection. A new aging prediction tool was also presented, AgingCalc, to calculate the transistors’ workload probabilities of a circuit and predict their Vth variation according to the aging time. Simulation results demonstrate the sensor robustness on detecting late transients at FF input data signal, even in the presence of its own aging. Future work includes cell library design, for complete methodology automatic insertion, analysis of sensor’s robustness in the presence of cross-talk noise and more extensive MC analysis to account for process variations, and will be reported in the future. ACKNOWLEDGMENT The work has been partially supported by ENIAC SE2A Project, and by FCT (INESC-ID multiannual funding) through the PIDDAC Program.
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