Aliasing-Free Space Compaction in VLSI with

International Journal of Research and Reviews in Computer Science (IJRRCS) Vol. 3, No. 1, February 2012, ISSN: 2079-2557 © Science Academy Publisher, United Kingdom www.sciacademypublisher.com

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Aliasing-Free Space Compaction in VLSI with Cascade of TwoInput OR/NOR Logic Sunil R. Das1,2, Satyendra N. Biswas3, Voicu Groza2, and Mansour H. Assaf4 1

Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103 USA School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada 3 School of Engineering and Computer Science, Independent University, Dhaka 1329, Bangladesh 4 Faculty of Science and Technology, University of South Pacific (USP), Suva, Fiji 2

Abstract – The synthesis of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper develops a new approach for realizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input OR/NOR logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems (ISCAS 85) combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments. Keywords – Aliasing-free space compaction, Built-In Self-Testing, Fault Detection compatibility, Conditional Fault Detection compatibility, System-On-Chips

1.

Introduction

An enormous amount of complexity has been brought into the test generation process of Integrated Circuits (ICs) due to Very Large-Scale Integration (VLSI). With an unprecedented growth of the electronics industry, the integration densities besides system complexities enormously increased and hence, the need for superior and more effective methods of testing to assure reliable operation of chips, the mainstay of today’s many sophisticated devices and products was intensely felt [1]–[21]. The concept of testing generally has a broad applicability and finding highly efficient testing techniques that ensure correct system performance is of great practical significance. The conventional testing procedures of digital systems require application of test input patterns generated by a Test Pattern Generator (TPG) to the Circuit Under Test (CUT) and comparing the responses with known correct responses. For VLSI systems, because of higher storage requirements for the fault-free responses, the standard test processes become highly expensive and thus, alternate approaches are sought at minimizing the amount of needed storage [1]–[21]. Built-In Self-Testing (BIST) is a design philosophy that has the capability of solving many of the problems otherwise encountered in testing digital systems. It combines the concepts of Built-In Test (BIT) and Self-Test (ST) in one, termed BIST. In BIST, test generation, test application and response verification are all accomplished through built-in hardware. This allows different parts of an IC chip to be tested in parallel, thereby reducing the required testing time

besides eliminating the need for external test equipment. A typical BIST architecture, shown in Figure 1, uses a TPG that sends its outputs to a CUT and output streams from the CUT are fed into a test data analyzer. A fault is detected if the test sequence is different from the response of the faultfree circuit. The test data analyzer is comprised of a Response Compaction Unit (RCU), storage for the fault-free response of the CUT and a comparator.

Figure 1. Typical BIST environment.

In order to reduce the amount of data represented by the

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fault-free and faulty CUT responses, data compression is used to create signatures (short binary sequences) from the CUT and its corresponding fault-free circuit. BIST techniques use pseudo-exhaustive or exhaustive test patterns or on-chip storing of reduced or compact test sets. The RCU can be divided into two parts: a space compaction unit followed by a time compressor. In general, P input sequences coming from a CUT are fed into a space compressor, providing L output streams of bits such that L  P; most often, test responses are compressed into only one sequence (L = 1). Space compression brings a solution to the problem of achieving high quality BIST of complex circuit chips without the necessity of monitoring a large number of internal test points, reducing testing time and area overhead by merging test sequences coming from these internal test points into a single stream of bits. This single bit stream of length H is eventually fed into a time compactor, yielding a shorter sequence of length B (B  H) at the output. The extra logic representing the compression network, however, must be as simple as possible, to be easily embedded within the CUT and should not introduce signal delays to affect either the test execution time or normal functionality of the unit being tested. Further, signatures derived from faulty output responses and their corresponding fault-free signatures should not be the same, which unfortunately is not always the case. A fundamental problem with compression techniques is error masking or aliasing [12], which occurs when the signatures from faulty output responses map into the faultfree signatures. Aliasing causes loss of information, which in turn affects the test quality of BIST and reduces the Fault Coverage (FC). Several approaches have been suggested in the literature for computing the aliasing probability of which the exact computation is known to be NP-hard [12]. The subject paper proposes a new technique for implementing aliasing-free BIST space support hardware targeting specifically embedded cores-based System-OnChips (SOCs) [1]–[3], [11], extending some well-known concept of conventional switching theory, viz. that of compatibility relation as employed in the minimization of incomplete sequential machines, based on pairwise sequence mergeability, for detectable single stuck-line faults of the CUT, using pseudorandom and compact test sets. A major challenge in realizing aliasing-free space compaction in BIST is the development of techniques that are simple, suitable for on-chip ST, require low area overhead and have little adverse impact on the CUT performance. Taking advantage of mathematically sound selection criteria of aliasing-free merger of a pair of response outputs of the CUT by two-input OR/NOR logic, the paper achieves maximal compaction in the design, as is evident from extensive simulation runs conducted on the International Symposium on Circuits And Systems (ISCAS) 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using fault simulation programs ATALANTA and FSIM, though, only some partial results on simulation on ISCAS 85 combinational benchmark circuits using ATALANTA and FSIM are provided.

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2.

Implementing Aliasing-Free Space Compaction–Mathematical Basis

The mathematical basis underlying the realization of the proposed aliasing-free space compression is briefly outlined in the following. Property 1: Let A and B represent two of the outputs of an n-input m-output CUT. Let these CUT outputs be merged by a gate of the logic family OR/NOR and let the gate output be z1. Then, we might envisage the undernoted possible scenarios. Case 1: Fault-free (FF) outputs = Faulty (F) outputs (outputs subject to the condition of CUT having faults), viz. FF = F  Outputs A and B of the CUT do not detect any faults and faults are hence not detectable at z1. Case 2: Only the faults that occur at A and B (subject to the condition of CUT having faults) are detectable at z 1  FF  F. Case 3: Faults occur at A and B but either all or some are not detectable at z1  FF  F. In this case, the faults missed at z1 are detected additionally at other outputs of the CUT besides A and B. Now assume that the fault situation at the two outputs A, B of CUT conforms to conditions of Cases 1 and 2 as discussed above (but not of Case 3). If the CUT outputs A, B are now merged by an OR/NOR gate, we define output lines A, B to be strongly OR/NOR Fault Detection (FD) compatible, written as (AB) s-OR/NOR FD compatible. However, if the fault situation at the two outputs A, B conforms to conditions of Case 3 (but not of Cases 1 and 2) and the CUT outputs A, B are now merged by an OR/NOR gate, we define output lines A, B to be weakly OR/NOR FD compatible, written as (AB) w-OR/NOR FD compatible. On the other hand, if the fault situation at the two outputs A, B conforms to none of the conditions specified by Cases 1–3 and the CUT outputs A, B are now merged by an OR/NOR gate, we define output lines A, B to be OR/NOR FD incompatible, written as (AB) OR/NOR FD incompatible. Finally, when the fault situation at the two outputs A, B conforms to one of the three conditions as specified by Cases 1–3 but unknown to us and the CUT outputs A, B are merged under these conditions by an OR/NOR gate, then we define the output lines A, B to be OR/NOR FD compatible, written as (AB) OR/NOR FD compatible (neither strong nor weak). The concept of strong compatibility as developed above is of immense importance in the context of generalized sequence mergeability [13]–[15], but of no particular relevance in pairwise sequence mergeability as used in the present paper. The detection of strong compatibility in response output pairs in real experimentations is somewhat difficult; as such, we may not know which of the conditions specified by Cases 1–3 as discussed the merged outputs (using OR/NOR gates) will conform to and hence, we normally will have to deal exclusively with the case of outputs being either just FD compatible or FD incompatible. However, an approach to the solution of the problem utilizing the concept of fault grading has been recently proposed, which renders the developed mathematical basis underlying the notion of strong and weak compatibilities rather meaningful in relation to generalized sequence merge-

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ability [14]. Under normal circumstances, since there is no way of knowing if any CUT output pair is s-OR/NOR or wOR/NOR FD compatible, the gate output needs to be actually tested through proper experimentation to determine that. In addition, there was yet another major hurdle that had to be overcome in using generalized sequence mergeability, where previously developed design algorithms by the authors involved computation of FD Maximal Compatibility Classes (MCCs) [22] corresponding to the appropriate logic being used in merger (AND/NAND, OR/NOR, XOR/XNOR logic families were used in those cases) at every stage of the compaction process in constructing the compression network [13]–15], [21]. The very finding of the MCCs is in itself an NP-complete problem in general [12]. Also, there were heuristics involved during merger based on choice of the MCC class, since it was not known if the class chosen is a strong FD MCC class for the logic used. In this paper, the problem of generation of FD MCCs for the logic from the pairs of FD compatibles or FD incompatibles was completely eliminated by using an entirely different kind of solution approach. Instead of using AND/NAND, OR/NOR, XOR/XNOR logic with any numbers of inputs, we restrict ourselves in our procedure here to using only two-input OR/NOR logic. The mathematical basis of the method is outlined below with appropriate definition and theorem. Definition 1: Let A, B, C, ... be the different outputs of an n-input m-output CUT. Let the faults detected at the CUT outputs A, B, C, … be , where  , the total number of detectable faults at the CUT outputs when subjected to a compacted set of deterministic tests ,   2n,  might not be a minimal or non-minimal but complete set of tests, or to pseudorandom tests. Assume that the fault situation at the outputs A, B conforms to one of the conditions of Cases 1–3 as discussed. After merger of the CUT outputs A, B by a two-input OR/NOR gate so that (AB) is OR/NOR FD compatible, if the CUT outputs C, D are now merged by a two-input OR/NOR gate so that (CD) is also OR/NOR FD compatible, we define the output lines (CD) to be conditionally OR/NOR FD compatible, subject to the outputs (AB) being FD compatible, written as (CD)-OR/NOR conditionally FD compatible. Based on the notion of OR/NOR FD compatibility and conditional FD compatibility, optimal pairs of lines can be selected at the outputs of the original CUT and at subsequent stages of the compaction procedure. The process of merger has to be continued until all output lines or as many as possible are exhausted at each compression stage, eventually obtaining an aliasing-free compactor, preferably with a single output line. Appropriate algorithms for the selection of a maximal number of two-input OR/NOR logic at each stage of compaction based on the concept of FD compatibility and conditional FD compatibility are provided in the paper. But, before we discuss the details of our proposed algorithms, we first give the undernoted theorem that sets the upper and lower bounds on the number of compactor stages. Theorem 1: For an n-input m-output CUT, the lower bound on the number of stages in the aliasing-free compression network with a single output after merger in the last stage is TL = log2m, where TL is the least integer

1363 greater than or equal to log2m, whereas the upper bound on the number of stages is TU = m–1. Proof: Since the number of outputs of the CUT is m, the number of inputs to the compressor in the 1 st stage is m. The number of inputs to the compressor at the 2 nd stage is obviously m/2, since merger is done by two-input OR/NOR gates, where m/2 represents the least integer greater than or equal to m/2, depending on whether the number m is odd or even. Again, the number of inputs to the compressor in the 3rd stage is m/22, where m/22 is the least integer greater than or equal to m/22, depending on if the number m/22 is odd or even. Proceeding this way, the number of inputs to the compressor at the r th stage is m/2r– 1 , where m/2r–1 is the least integer greater than or equal to m/2r–1, depending on the number being odd or even. If the r th stage is the last stage, then m/2r–1 = 2. Hence, the number m/2r–1 (integer or fraction) is less than or equal to () 2 but greater than () 1, or 2r–1  m  2r. Therefore, r = number of compactor stages = log2m. To prove the upper bound, we note that at every stage we merge two CUT output lines by a two-input OR/NOR gate, thereby reducing the number of CUT output lines by one; to reduce m–1 output lines, we need evidently m–1 compaction stages.

3.

Development of Algorithms

3.1. Algorithm A The first stage of the proposed compression network is designed by carrying out the undernoted steps (Figure 2). Step 1: For an m-output CUT, find the output pair aiaj from the set of all pairs a1a2, a1a3, …, a1am; a2a3, a2a4, …, a2am; …, am–1am, where the subscripts i and j in pair aiaj (i ≠ j) are minimum values such that the output pair is FD compatible. Step 2: Merge the output pair aiaj with two-input OR/NOR gate resulting in output b1. Step 3: Rename m–1 outputs of the new CUT from the top as: c1, c2, …, cm–1. Step 4: Go to Step1and find the first pair cicj, where the subscripts i and j in pair cicj (i ≠ j) are again minimum values such that the output pair is FD compatible. (The output pair cicj is defined to be conditionally FD compatible subject to the pair aiaj being FD compatible). Step 5: Merge the output pair cicj with two-input OR/NOR gate resulting in output d1. Step 6: Rename m–2 outputs of the new CUT from the top as: e1, e2, …, em–2. Step 7: Go to Step1 and again find the first pair eiej, where the subscripts i and j in pair eiej (i ≠ j) are minimum values such that the output pair is FD compatible (conditionally FD compatible). Step 8: Merge the output pair eiej with two-input OR/NOR gate resulting in output f1. Step 9: Rename m–3 outputs of the new CUT from the top as: g1, g2, …, gm–3. Step 10: Follow through the process in this manner until no more pairs of FD compatible outputs (conditionally FD compatible) are found.

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1364 compatible (conditionally FD compatible). Go on as far as possible to ensure that maximum numbers of pairs are merged at the kth compression stage. Step 2: Continue this way to merge the output pairs of the newly generated CUT at every stage of compaction until a single output or a minimal number of outputs is finally produced with all circuit faults detected. Figure 4 demonstrates the implementation fundamentals of the Algorithms through an example.

Figure 2. First stage of compaction.

For a CUT with m output lines, the maximum possible mergers based on FD compatibility and conditional FD compatibility is m/2, if m is even; if m is odd, the maximum possible mergers is (m–1)/2 with one output line excluded. In general, however, it is expected to be less based on the nature of the CUT and also on the selection criteria being used (different from as used here). 3.2. Algorithm B By following an identical procedure as outlined in Algorithm A for first stage, the second and subsequent stages of the compaction network are designed as follows (Figure 3).

Figure 3. Second and subsequent stages of compaction.

Step 1: At the kth compaction stage, k  2, merge the output pairs yhcyhd, yieyif, yjgyjh, …. , where the subscripts hc, hd, ie, if, jg, jh, … in the pairs (hc ≠ hd, ie ≠ if, jg ≠ jh, …) are minimum values such that the output pairs are FD

4.

Simulation Experiments

To demonstrate the feasibility of the proposed aliasingfree space compression technique, extensive simulations were conducted on different ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits (the results on ISCAS 89 sequential circuits are not included here though). In the design experimentation, we used ATALANTA [23] (fault simulation program developed at the Virginia Polytechnic Institute and State University) as out test generation tool to generate the fault-free output sequences required to construct the space compressor circuits and to test the benchmark circuits using reduced test sets, accompanied with a random test session with FSIM fault simulation program [24] that produces the necessary pseudorandom test vectors that detect most detectable single stuck-line faults for all the benchmark circuits. For each of the circuits, we computed the FC before adding the compaction network, fault coverage with the compression circuit, number of applied test vectors, simulation CPU time, estimates of hardware overhead and maximal compaction ratio. For designing the first stage of the compactor, Algorithm A is run first on the original CUT to generate an FD compatible pair and then conditional FD compatible pairs of output lines for merger with two-input OR/NOR logic. As demonstrated in Figure 4, after generating the second and subsequent stages of the compression network, by following Algorithm B, the process of merger has to be continued until either a single output or a minimal number of outputs is eventually obtained. The results presented in Figures 5 through 9 provide number of outputs of the CUT, number of test vectors, number of injected faults, FC and compaction ratio, besides estimates of hardware overhead for ISCAS 85 combinational benchmark circuits using simulation programs ATALANTA and FSIM.

Figure 4. An example of an ideal implementation circuit.

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Figure 5. Fault coverage of ISCAS 85 combinational benchmark circuits using FSIM without space compactors.

Figure 6. Fault coverage of ISCAS 85 combinational benchmark circuits using FSIM with space compactors.

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Figure 8. Fault coverage of ISCAS 85 combinational benchmark circuits using ATALANTA with space compactors.

Figure 9. Area overhead of added compactors of ISCAS 85 combinational benchmark circuits.

5.

Figure 7. Fault coverage of ISCAS 85 combinational benchmark circuits using ATALANTA without space compactors.

Conclusions

A new approach to the design of aliasing-free space compactors targeted specifically towards embedded coresbased SOCs is proposed in the paper. In the development of the methodology for the selection of logic for the merger of output bit streams from the CUT, use is made of some wellknown concept of conventional switching theory, viz. that of compatibility relation as utilized in the minimization of incompletely specified sequential machines. As the test data demonstrate, the resulting area overhead of the compressors is consistent with regard to the complexity of the CUT. With successful implementation of the methodology, it might be possible to automate the overall design process used for the compressors. This could eventually lead to the use of smaller circuits, possibly using even nano-components. Besides, reliable automation tools could facilitate testing and design of compactors of larger and more complex digital circuits as well. An improvement in these sectors of computing could go a long way in influencing a widespread impact across the entire discipline.

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Acknowledgment This research was supported in part by the Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103 USA.

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