and Three-Dimensional CMOS Device Structures

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Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures Joris Lacord, Gérard Ghibaudo, and Frédéric Boeuf, Member, IEEE

Abstract—In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations. Index Terms—Analytical model, benchmarking, CMOS, parasitic capacitance.

I. I NTRODUCTION Fig. 1.

D

UE TO THE scaling of advanced CMOS devices, parasitic capacitances become a performance constraint which cannot be neglected. In this paper, we present a unified solution to quickly evaluate the extrinsic and intrinsic capacitance components of various CMOS devices, including the contact level integration scheme, on bulk-Si, FDSOI [1], planar double gate (DG) [2], and FinFET [3] devices. Our models are developed to be accurate and ready to use for the comparison of these architectures and easily adaptable for other structures such as quantum-well-type transistors [4]. In contrast to previous works on planar devices [5]–[10], gate-to-contact capacitance and corner capacitance, bilayer spacer, and raised S/D, faceted or not, are accurately modeled, and the contact scheme (BAR contact versus plug contact) impact on parasitic is studied. In addition, inner-fringe capacitance screening is physically implemented. Concerning FinFET [11]–[13], all specific parasitic components have been modeled. Finally, all analytical models, including FinFET, have been validated with 2-D (FlexPDE software [14]) and 3-D (Raphael software [15]) simulations and were used to evaluate parasitic impact following ITRS-roadmap requirement.

Conformal mapping coordinate system.

II. F RINGE C APACITANCE M ODELING M ETHODOLOGY A fringe capacitance is a capacitance due to two electrodes which are not parallel, separated by an insulator. In the modeling of parasitic capacitances on CMOS devices, we mainly met fringe capacitances which are composed of two perpendicular electrodes, separated by an insulator. A common example is the outer-fringe capacitance which is the capacitance between the gate sidewall and the source or the drain. Contrary to a parallel-plate capacitance, electric field lines are not linear but elliptical. Some works treated this question by making the hypothesis of circular electrical field lines [6]–[8]. By this way, an analytical expression of fringe capacitance can be easily obtained. However, this method is not very accurate, and keeping elliptical shape is mandatory for accuracy. As done in some previous works [9], [10], we choose to use conformal mapping to perform an accurate fringe modeling. It consists in transforming the initial Cartesian coordinate system (x, y) into an elliptical one (x
, y
) (Fig. 1) by applying the transformation function given in [17] F (x + jy) = (x
+ jy
),

Manuscript received October 26, 2011; accepted February 3, 2012. Date of publication March 6, 2012; date of current version April 25, 2012. The review of this paper was arranged by Editor R. Huang. J. Lacord is with STMicroelectronics, 38926 Crolles, France, and also with the Institute of Microelectronics, Electromagnetism and Photonics (IMEPLAHC), Minatec–INPG, 38016 Grenoble, France (e-mail: joris.lacord@ st.com). G. Ghibaudo is with the Institute of Microelectronics, Electromagnetism and Photonics (IMEP-LAHC), Minatec–INPG, 38016 Grenoble, France (e-mail: [email protected]). F. Boeuf is with STMicroelectronics, 38926 Crolles, France (e-mail: frederic. [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2187454

where F = arcos.

So, x
and y
can be expressed in function of x and y. After some mathematical operations, fringe capacitance can be expressed as a parallel-plate one in the curvilinear coordinate system; if x1 = x2 , it leads to   √  x21 +min(y2 ,x2 )2 +2·y1 min(y2 ,x2 ) −1    sinh |x21 −y12 |  ε  .   C1 = 2     π   −1 x 1  − sinh |x21 −y12 | (1)

0018-9383/$31.00 © 2012 IEEE

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TABLE I D IMENSIONS AND T ECHNOLOGICAL PARAMETERS U SED IN THE M ODEL

Fig. 2. Schematic view of studied planar architectures with their parasitic capacitances. From left to right: Bulk, FDSOI, and planar DG.

Knowing that the use of conformal mapping implies that ellipses are confocal, it is clear that x1 and y1 on one hand and x2 and y2 on the other hand are commutable. However, this equation gives only the capacitance due to elliptical electric field lines. To model the capacitance due to the region x < x1 and y < y1 (gray area in Fig. 1) where electric field lines are neither elliptical nor regular, we use the equation given in [17], which gives a reasonable approximation   πW εox W ln  2 C2 = 0.35 (2) 2π |x1 − y12 | where W is the device width and 0.35 is a fitting parameter determined from numerical simulations. Consequently, the total fringe capacitance is obtained by C = W · C1 + C2 . Finally, if x1 = x2 , the electric field lines are circular, and the methodology in [6]–[8] can be used. III. C APACITANCE M ODELING ON P LANAR A RCHITECTURES Planar architectures are used for the current CMOS device generation (bulk transistors) and are strong candidates for advanced technological node (FDSOI and planar DG [1], [2]). We choose to model parasitic capacitance on the three planar structures shown in Fig. 2. In this section, we first consider that all devices do not feature raised source/drain, but this point will be specifically treated in Section V. We assume that gate-to-contact distance is equal to spacer thickness and spacer is composed of only one material (multilayer case will be treated later in this paper). In Table I, we summarize the dimensions that we have taken into account in the modeling, and we illustrate in Fig. 3 those dimensions and the two contact schemes. A. Overlap Capacitance Cov Overlap capacitance is the capacitance due to the S/D junction overlap under the gate and can be evaluated as a gateto-channel capacitance by only replacing the gate length (Lg ) by the overlap length (dL). As the overlap region is highly doped (commonly, > 1019 cm3 ) and with the same type as S/D junction, this capacitance can be considered as constant with bias. Therefore, in the case of simple gate structure (bulk and FDSOI), we have εox . (3) Cov = W dL EOT

For DG architecture, because of the second gate, this capacitance is twice the one of single gate εox . (4) Cov = 2W dL EOT B. Junction Capacitance Cj /Cbox In the bulk transistor case, the junction capacitance is evaluated with the classical p-n junction capacitance equation, given in [10] 

1 Xj + (CP P − Lg ) Cj = W 2   1 qεSi Nsd Nb  (5) × (Nsd + Nb ) ϕ + V − 2 kT d

ds

q

where Nsd is the LDD doping, Nb is the bulk doping, ϕd is the built-in potential, and Vds is the drain-to-source polarization. For FDSOI and DG devices, junction capacitance is reduced to a BOX capacitance (since S/D junctions are isolated from the bulk by the BOX) either SiO2 for FDSOI (εBOX = 3.9 × 8.85 × 10−12 F/m) or Si3 N4 for the DG structure (εBOX = 7 × 8.85 × 10−12 F/m) Cj = W

(CP P − Lg ) εBOX . 2 TBOX

(6)

C. Outer-Fringe Capacitance Cof The outer-fringe capacitance is the capacitance between the gate sidewall and the S/D junction through the spacer. This capacitance can be evaluated, owing to the methodology described in Section II. In the case of single-gate devices, we

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Fig. 3. Schematic view and characteristic dimensions of the bulk device.

have to set (x1 , y1 , x2 , y2 ) = (0, tox , tsp , Hg ). From (1) and (2), we have Cof =

2 W εspacer sinh−1 π    min(Hg , tsp )2 + 2tox min(Hg , tsp )  ×  tox + 0.35εspacer



W W ln π . π tox

(7)

For DG devices (Fig. 2, right), the total outer-fringe capacitance is composed of two components (one per gate). The first one due to the top gate is identical to the single-gate case and is calculated with (7). The second one due to the bottom gate is quite different. Indeed, the length of the S/D junction is not limited by the contact as in the top gate case but by the shallow trench isolation (STI) which limits the active area. Moreover, the height of the bottom gate (Hgb ) can be different from that of the top gate (Hg ). Consequently, the corresponding outerfringe capacitance components can be calculated in setting (x1 , y1 , x2 , y2 ) = (0, tox , (CP P − Lg )/2, Hgb ) in (1) and (2). For a DG device Cof = Cof top + Cof bottom

(8)

with Cof top 2 = W εspacer sinh−1 π    min(Hg , tsp )2 + 2tox min(Hg , tsp )  × tox

W W + 0.35εspacer ln π (9) π tox Cof bottom 2 = W εspacer sinh−1 π    2      min Hgb , CP P −Lg +2tox min Hgb , CP P −Lg  2 2    ×   tox   + 0.35εspacer



W W ln π . π tox

(10)

Fig. 4. (a) Potential map generated with FlexPDE and different parasitic capacitance components. (b) Model with and without gate height correction versus numerical simulations for gate height variation.

D. Gate-to-Contact Capacitance Cpcca Contact is a critical step in the definition of device architecture. Today, there are two main architectures for contact definition: trench contact [16], where the contact is continuous on the silicon active area width, and the conventional “discreet plug” contacts. The set of equations described in the following is common to the three studied planar architectures. 1) Trench Contact: In this case, the gate-to-contact capacitance is composed of a parallel-plate component between the gate sidewall and the contact (Cpccaflat ), and a fringe one is composed of a parallel-plate component between the top of the gate and the contact (Cpccatop ). For the parallel-plate component, we use the classical parallel-plate capacitor equation Cppcaflat = W Hg

εspacer . tsp

(11)

In order to validate this approach, we performed 2-D numerical simulations with FlexPDE software [14], which is a very flexible partial derivative equation solver. Before running the simulation, we first define our structure, considering only the conductor and insulator region; it is then automatically meshed, and Poisson and Laplace equations are solved using the finite-difference method. Finally, we can extract the total capacitance of the structure. A typical simulation kit is shown in Fig. 4(a). We can see in Fig. 4(b) that accordance of (11) (dashed lines) with simulations (dot) can be improved. From the potential map generated with FlexPDE, we can see that the isopotential lines are not rectilinear from the top of the gate to the gate oxide. Indeed, near the gate oxide, the outerfringe capacitance is prevailing. From those simulations, we estimate that fringe is dominant from gate oxide to tsp /2 along the gate sidewall. Consequently, gate height has to be corrected

LACORD et al.: PARASITIC CAPACITANCE MODELS FOR CMOS DEVICE STRUCTURES

Fig. 5.

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Outer-fringe and gate-to-contact capacitances for (a) spacer thickness variation and (b) gate height variation.

of one side. The modeling of region 1 is the same as in the case of the trench contact. For the capacitance due to one contact, we just have to replace device width W with contact width Lc , therefore yielding Cpccaflat = Lc

Fig. 6. Potential map generated with FlexPDE illustrating the two cases of discreet contact model.

by subtracting the half of spacer thickness in the evaluation of Cpccaflat

tsp εspacer Cpccaflat = W Hg − . (12) 2 tsp This correction done, the model [continuous line in Fig. 4(b)] gives a good agreement with numerical simulations. Cpccatop can be easily evaluated with the methodology described in Section II in setting (x1 , y1 , x2 , y2 ) = (0, tsp , Lg /2, HM 1 ) Cpccatop 2 = W εpmd sinh−1 π    2     Lg Lg min HM 1 , 2 + 2tsp min HM 1 , 2     ×  tsp    L  g W + 0.35εpmd ln π 2 . π tsp

(13)

Fig. 5 shows the good agreement of outer-fringe and gateto-contact capacitance models with 2-D FlexPDE numerical simulations with gate height variation (a) and spacer thickness variation (b). 2) Discreet Contact: This contact scheme is a bit more complex to model. Indeed, there are two kinds of region to take into account (Fig. 6): the one where there is a contact in front of the gate (region 1) and the other one where there is a space between two contacts (region 2). For simplicity, we will consider that contacts are square, with Lc being the dimension



tsp Hg − 2

εspacer tsp

(14)

aCpccatop 2 = Lc εpmd sinh−1 π    2     Lg Lg min HM 1 , 2 + 2tsp min HM 1 , 2     ×  tsp    L  g Lc + 0.35εpmd ln π 2 . π tsp

(15)

For region 2, two cases have to be considered. The first one is when the contact is the first after active edge, as shown in Fig. 6(a). Thus, the capacitance due to region 2 is divided into two fringe components and can be modeled with the methodology in Section II with (x1 , y1 , x2 , y2 ) = (0, tsp , Cs , Lc ) for Cpccafringeedge and (x1 , y1 , x2 , y2 ) = (0, tsp , C2C/2, Lc ) for Cpccafringe Cpccafringe edge 2 = Hg εspacer · sinh−1 π    2 min(CS , LC ) + 2tsp min(CS , LC )  × tsp

Hg Hg + 0.35 · εspacer ln π (16) π tsp aCpccafringe 2 = Hg εspacer · sinh−1 π     min  C2C , L 2 + 2t min  C2C , L  C sp C   2 2 ×  tsp

Hg Hg ln π + 0.35 · εspacer . (17) π tsp

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TABLE II C OMPARISON B ETWEEN M ODEL AND N UMERICAL S IMULATIONS

Fig. 7. Raphael simulation kit.

parasitic values which are, in contrary to Ccorner , proportional to device width. However, in advanced technological nodes, the device width is reduced, and the corner capacitance has a greater impact on the total parasitic capacitance. Consequently, an accurate model is mandatory to perform device benchmarking. Previous work [10] proposed a very simple model; however, the dependence on Wext is not accurately accounted for, and the gate length impact is not taken into account. Indeed, Ccorner can be divided into four components: CcornerSD , which is the capacitance between the gate extension and the S/D junction through the spacer; Ccornercontact , which is the capacitance between the gate extension sidewall and the contact; Ccornercontacttop , which is the capacitance between the top of the gate extension and the contact; and CcornerG , which is the capacitance between the bottom of the gate extension and the bulk, through the STI. Note that the formulation presented here is common to the three studied planar device structures. For Ccornercontact , we can use directly the methodology described in Section II, with (x1 , y1 , x2 , y2 ) = (tsp , Cs , Wext , Cs + Wext ), which gives 2 Hg εspacer π  √ 2

Ccornercontact =

For the second case, shown in Fig. 6(b), region 2 is between two contacts, so the corresponding capacitance is equal to 2 × Cpccafringe . Finally, for Nc contacts, the total gate-to-contact capacitance is given by Cpcca = Nc Cpccaflat + Nc Cpccatop + 2(Nc − 1)Cpccafringe + 2Cpccafringe

edge

.

(18)

In order to validate this model, 3-D simulations were performed using the Raphael software [15], which is a tool designed to numerically evaluate parasitic capacitances. As in 2-D simulations, it automatically meshes the structure that we defined and solves Poisson and Laplace equations by finite-difference method. Finally, it extracts the capacitance between each conductive block. The comparison between numerical simulation and analytical model is summarized in Table II, and Fig. 7 shows a Raphael simulation kit, typical of the 40-nm technology (tsp = 33 nm, C2C = 72 nm, Hg = 80 nm, Cs = 37 nm, and L = 40 nm). It has to be mentioned that in C40 design rules, the space between two contacts (C2C = 72 nm) is roughly twice the distance between the first contact on active and the edge of active (Cs = 37 nm). Therefore, C2C/2 is roughly equal to Cs , leading to Cpccafringe  Cpccafringeedge . Finally, injecting this equality in (18) gives a capacitance that is proportional to the number of contacts. That is the reason why the gate-to-contact capacitance looks proportional to the number of contacts in our simulations. E. Corner Capacitance Ccorner Ccorner is the corner capacitance due to gate extension on STI. A schematic view is given in Fig. 8(a). In past technological nodes, this component was negligible compared to the other



−1  sinh × 

tsp +2(Cs +Wext )Cs +(Cs +Wext )2

√2 t −C 2  sp s 2 √ 2tsp 2 − sinh−1

   . (19) 

tsp −Cs

The component CcornerG can also be modeled with classical conformal mapping, with (x1 , y1 , x2 , y2 ) = (0, tox , Wext , Wext )    2 + 2W t W 2 ext ox ext  CcornerG = LεSTI sinh−1  π tox + 0.35 · εSTI



W W ln π . π tox

(20)

Then, for the two last components, conformal mapping cannot be used directly because electrodes are not in the same plane and are not perpendicular. That is why we adapt conformal mapping. For the CcornerSD component, we divide the gate extension in n slices and apply conformal mapping on each one; after that, we sum up the n elementary capacitances. With Hg /n being the thickness of an elementary slice and in roughly adapting the methodology described in the Section II as ((x1 , y1 , x2 , y2 ) = (iHg /n, tox , Wext , Wext )), we obtain 2 Hg εspacer · sinh−1 π n     2  Hg 2 + 2tox Wext + Wext i n      ×   . (21)  2   Hg 2 i− n − tox

CcornerSD = Σi

Ccornercontacttop can be modeled in a similar way as CconerSD . We choose to cut the gate extension in n slices but,

LACORD et al.: PARASITIC CAPACITANCE MODELS FOR CMOS DEVICE STRUCTURES

Fig. 8.

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(a) Schematic illustration of different Ccorner components. (b) Raphael simulation kit. TABLE III Ccorner A NALYTICAL M ODEL FOR G ATE L ENGTH VARIATION

this time, in the gate extension direction, so the slice thickness will be (Wext /n). Then, we use Pythagoras’ theorem to define Hmineff (i), the shorter length, for a given slice from the contact to the top of the contact and Hmaxeff (i), the effective dimension of the slice. The methodology in Section II can be used with (x1 , y1 , x2 , y2 ) = (0, Hmineff (i), Hmaxeff (i), Hmaxeff (i))

Fig. 9. (a) Inner-fringe capacitance for gate voltage variation. (b) Inner-fringe capacitance 2-D FlexPDE simulation kit.

fringe capacitance modeling, so the methodology in Section II can be used with (x1 , y1 , x2 , y2 ) = (0, tox , Lelec /2, Xj ), which leads to

Ccornercontacttop Cif =

2 Wext εspacer sinh−1 π n    2 H maxeff +2H maxeff H mineff  × H mineff

= Σi 2

aHmaxeff (i)  = (Cs + iWext /n)2 + (tsp + L/2)2 − H min(i) eff

Hmineff (i)  =

Cs + i

Wext n

2 + t2sp .

(22)

A three-dimensional simulation has been performed with Raphael software [15] to validate the model, a simulation kit is shown in Fig. 8(b) (similar to the one used in Section III-D2), and results are summarized in Table III. F. Inner-Fringe Capacitance Cif The inner-fringe capacitance is the capacitance between the gate and the S/D junction through the silicon. In a first approximation, we will consider, as in previous work [10], that Cif is constant, which is equivalent to considering silicon as an insulator with a permittivity that is equal to εSi . Consequently, inner-fringe capacitance modeling is very similar to outer-

2 W εSi sinh−1 π     2   Lelec  Lelec   min 2 , Xj + 2tox min 2 , Xj   ×   tox

W W ln π + 0.35εSi . π tox

(23)

However, other work [18] mentioned that this approximation leads to great errors in the case of circuit simulation. Indeed, Cif is strongly gate bias dependent: It is negligible in inversion and accumulation regime because of charge screening and reaches its maximum in depletion regime. To model this bias dependence, we choose to use the approach in [19], which presents a screening function. In the case of inner-fringe capacitance, it leads to Cif (Vg ) =

2 Cifmax Cox 2 (Cox +Cgc (Vg )−Cmin ) +Cifmax (Cgc (Vg )−Cmin )

(24)

where Vg is the gate voltage, Cox is the gate oxide capacitance, Cgc (Vg ) is the gate-to-channel capacitance, Cmin is the lower value reached by Cgc (Vg ), and Cifmax is the maximum value reached by Cif evaluated with (23). Fig. 9(a) shows the good agreement of the analytical model and 2-D FlexPDE numerical simulation [the kit is shown on Fig. 9(b)].

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the electrical width of the device. For a FinFET Cov = 2Nfin HSi dL

εox . EOT

(25)

For a trigate, the influence of the additional gate has to be accounted for Cov = (2Nfin HSi + Nfin TSi ) dL Fig. 10. Schematic description of 3-D devices. (a) FinFET. (b) Trigate.

Equation (23) gives the value of inner-fringe capacitance for single-gate devices, where Xj has to be replaced by TSi in the case of FDSOI devices. For DG devices, this value has to be multiplied by two.

CHM = Nfin TSi Lg

εHM . Tmask

(27)

B. Inner-Fringe Capacitance: Cif As the overlap capacitance, the inner-fringe capacitance modeling is very similar to the planar case. Only its maximum value Cifmax depends on the architecture. After adapting (23) to FinFET device, we obtain Cifmax =

2 2Nfin HSi εSi sinh−1 π         2   min Lg , TSi + 2tox min Lg , TSi  2 2    ×   tox  

2Nfin HSi HSi + 0.35 εSi ln π . π tox

(28)

For trigate, the third gate has to be accounted for, which leads to 2 Cifmax = 2Nfin HSi εSi sinh−1 π      2     min Lg , TSi +2tox min Lg , TSi  2 2    ×   t ox  

HSi 2Nfin HSi 2 + 0.35 εSi ln π + Nfin TSi εSi sinh−1 π tox π     2      min Lg , HSi +2tox min Lg , HSi  2 2    ×   tox  

A. Overlap and Hard Mask Capacitance: Cov and CHM For a 3-D device, overlap capacitance is exactly the same as that in the planar case, in only replacing the device width with

(26)

Therefore, the overlap capacitance will be higher in the case of a trigate compared to a FinFET. However, the capacitance due to hard mask will be equal to zero for a trigate (because, in this case, there is gate oxide), whereas for a FinFET, there is an additional parasitic capacitance between the fin and the gate, which is equal to

IV. C APACITANCE M ODELING ON 3-D A RCHITECTURES Three-dimensional device structures are the most popular way of fabricating multigate devices, such as DG FinFETs or bulk trigates. Due to the lower footprint at constant electrical width and the better electrostatic immunity compared to single-gate devices, 3-D structures will be used in the next industrial high-performance CMOS technology. Moreover, they are a strong candidates for the low-power technologies at the 14-nm node. Consequently, an accurate model of parasitic capacitances is mandatory to predict the performance of such devices at circuit level. We limit our work to 3-D device processed on SOI substrate. In terms of parasitic modeling, SOI-FinFET and SOI-trigate devices are very similar. Indeed, the only difference between the two structures is located on the top of the fin, under the gate. For FinFET, a thick nitride hard mask layer prevents conduction on the top of the fin to ensure DG configuration. Whereas, in the case of trigate devices, there is a gate oxide layer on the top of the fin to ensure the trigate configuration. The two structures are shown in Fig. 10. Since the device width is discreet, such structures are used in multifinger configuration: Fins are connected to the same gate electrode, and their source and drain are merged, owing to Si epitaxy [3]. The number of fins (Nfin ) depends on the targeted electrical width. Fig. 11 shows two schematics views of a FinFET device and its characteristic dimensions. Finally, Fig. 12 shows the different parasitic capacitance components of a FinFET device, which are similar for a trigate. The set of equation described in the following can easily be adapted to 3-D devices fabricated on bulk substrate, after replacing capacitance due to the BOX by junction capacitances. As in the planar case, we will consider that spacer is composed of only one layer and one material and that gate-toepitaxy distance and gate-to-contact distance are equal to spacer thickness.

εox . EOT

+ 0.35 εSi



TSi Nfin TSi ln π . π tox

(29)

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Fig. 11. Schematic view and dimensions of a 3-D device. (a) Cross section in Lg direction. (b) Top view.

Fig. 12. Schematic view and parasitic’s components of a 3-D device. (a) Three-dimensional view. (b) Cross section in Lg direction. (c) Top view.

C. Gate-to-Fin Capacitance: Cgfin The fin-to-gate capacitance is very similar to the outerfringe capacitance in planar case. It can be divided into four components [see Fig. 12(a)]: Cgfinside , which is the capacitance between the two sidewalls of the fin and the gate; Cgfintop , which is the capacitance between the top of the fin and the gate; Cgfincorner , which is the capacitance between the “corner” of the gate and the fin; and Cgfinbottom , which is the capacitance between the fin and the gate through the BOX. Cgfinside is the same for FinFET and trigate. It can be evaluated, owing to the methodology described in Section II, with (x1 , y1 , x2 , y2 ) = (0, tox , tsp , (F P − TSi )/2) Cgfinside 2 = 2Nfin HSi εspacer ×sinh−1 π      2    min (F P −TSi ) , 2 +2tox min (F P −TSi ) , tsp  2 2    ×   t ox  

HSi HSi + 2Nfin 0.35 εspacer ln π . π tox

(30)

Regarding Cgfintop , the equation is different for FinFET and trigate cases. For FinFET, we use the methodology described in Section II, with (x1 , y1 , x2 , y2 ) = (0, tmask , tsp , Hg ) Cgfintop =

2 Nfin TSi εspacer sinh−1 π    min(tsp , Hg )2 + 2 min(tsp , Hg )tmask  × tmask

TSi TSi εspacer ln π + Nfin 0.35 . (31) π tmask

For trigate, we have to set (x1 , y1 , x2 , y2 ) = (0, tox , tsp , Hg ), which leads to Cgfintop =

2 Nfin TSi εspacer sinh−1 π    2 min(tsp , Hg ) + 2 min(tsp , Hg )tox  × tox

TSi TSi + 2Nfin 0.35 εspacer ln π . (32) π tox

For Cgfincorner , we use a similar method as for the modeling of Ccornercontacttop in the planar case, yielding 2 itsp εspacer sinh−1 Cgfincorner = Σi 2Nfin π div    2 Hmaxeff + 2Hmaxeff Hmaxeff  × Hmineff  Hmaxeff (i) = (i tsp /n)2 + (tox + TSi )2 − Hmineff (i)  Hmineff (i) = (i tsp /n)2 + t2ox . (33) The last component is computed using the method of CcornerG      t2 + 2tsp tox  sp  TSi 2  εbox sinh−1  Cgfinbottom = 2Nfin   π 2 tox

TSi TSi εspacer ln π + 2Nfin 0.35 . 2π 2tox

(34)

Finally, the total gate-to-fin capacitance is given by Cgfin = Cgfintop + Cgfincorner + Cgfinside + Cgfinbottom . (35)

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D. Gate-to-Epitaxy Capacitance: Cgateepi The gate-to-epitaxy capacitance is a parallel-plate capacitance divided into two components: the first one between the fins, from the BOX to the top of the epitaxy Cgateepibetweenfins [Fig. 12(c)], and the second one over the fins, from the top of the fins to the end of the epitaxy Cgateepionfins [Fig. 12(b)]. As shown in Fig. 4(a), the fringe capacitance has to be taken into account to evaluate properly the parallel-plate capacitance. Consequently, in the case of a FinFET device, the Cgateepibetweenfins has to be divided into two components: the first one from the BOX to the top of the fin, which will be corrected in respect to Cgfinside , and the second one from the top of the fin to the end of the epitaxy, which is not impacted by any fringe capacitance. It leads to Cgateepi =

 F P−TSi  −tox min tsp , 2 Nfin HSi FP−TSi − 2tox εspacer 2 betweenfin1

Fig. 13. (a) Three-dimensional Raphael simulation kit for 3-D architecture. (b) Gate-to-fin and gate-to-epitaxy capacitances for spacer thickness variation.

The case of discreet contacts can be treated with an equivalent method. As in Section IV-D, the trigate configuration can be evaluated after replacing tmask with tox . F. Validation

tsp (36)

Cgateepi betweenfin2 Nfin Hepi (F P −TSi − 2tox )εspacer = . tsp

(37)

Similar to the first components of Cgateepibetweenfins , we can evaluate Cgateepionfins with the correction from Cgfintop Cgateepi = Nfin TSi onfin

min(tsp , Hg − tmask ) εspacer × Hepi − tmask − . 2 tsp

(38)

Finally, if (Hepi − tmask − (min(tsp , Hg − tmask )/2) < 0, Cgateepionfin = 0. To model the gate-to-epitaxy capacitance in the trigate configuration, we just have to replace tmask with tox in (38).

We perform 3-D simulation with Raphael software [15] to validate our model. We define a realistic FinFET device according to the work of Kawasaki et al. Fig. 13(a) shows a typical simulation kit of a FinFET device processed on SOI. Fig. 13(b) shows the parasitic capacitance components specific to FinFET: the fin-to-gate and gate-to-epitaxy capacitances for spacer thickness variation. This graph presents a good agreement of model with numerical simulations. Other parasitic capacitances are not shown but are modeled exactly as in the planar case and are validated in Section III. Nevertheless, we can remark that the error between Cgfin analytical model and simulations increases for small spacer thicknesses. In this case, the capacitance is mainly due to the region (x < x1 , y < y1 ) described in Fig. 1, where the capacitance can only be roughly evaluated, owing to (2).

E. Gate-to-Contact Capacitance: Cpcca

V. PARASITIC E VALUATION F OLLOWING ITRS ROADMAP

Gate-to-contact capacitance can be evaluated similarly to planar devices. Therefore, the difficulty is to define the gate height where electric field lines are rectilinear. It leads to

Following ITRS-roadmap projection [20], we evaluate capacitances for bulk, FDSOI, planar DG, and FinFET until 2021 in the low standby power case. It has to be mentioned that ITRS does not distinguish the different types of multigate devices. Thus, FinFET and planar DG are included in the multigate device group. For each year, we build a design rule for each device based on ITRS gate length (L), EOT , Xj /TSi , and M 1 contacted half pitch. Their evolution is shown in Table IV. From simple approximations, we derived the contacted polysilicon pitch (CPP), and transistor full geometry. All parameters needed for parasitic capacitance evaluation are summarized in Table V. Parasitic capacitances are then evaluated for each year. Fig. 14 shows the comparison of total capacitance (Cpar +Cgc , where Cpar = Cov +Cof +Cif +Cpcca +Ccorner ) normalized by Cgc . We can see that parasitic weight and its evolution with scaling are underestimated by the current ITRS methodology. In addition, we compared planar DG to FinFETs in terms of parasitics and found that planar DG presents a better Ctot /Cgc ratio.

Cgatecontact

flat





WfootprintHg −Hepi +tmask =

min tsp ,

Hepi −tmask 2

2

 εspacer

tsp

(39) Cgatecontacttop 2 = Wfootprint εpmd sinh−1 π    2     Lg Lg +2tsp min HM 1 , 2  min HM 1 , 2    ×  tsp    L  g Wfootprint + 0.35 εpmd ln π 2 . π tsp

(40)

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TABLE IV D IMENSIONS G IVEN BY ITRS FOR E ACH Y EAR AND E ACH D EVICE . R ED C ELLS M EAN T HAT ITRS P REDICTS T HAT THE S TRUCTURE W ILL N OT B E D EVELOPED D URING THE C ORRESPONDING Y EAR

Fig. 15. Equivalent structure for model. (a) ε1 < ε2 case. (b) ε1 > ε2 case. TABLE VI S UMMARY OF A NALYTICAL M ODEL V ERSUS N UMERICAL S IMULATION FOR A S PACER C OMPOSED OF T WO L AYERS

TABLE V S UMMARY OF R ELATION B ETWEEN D IMENSIONS G IVEN BY ITRS AND D IMENSIONS N EEDED TO E VALUATE PARASITIC C APACITANCES . G RAY C ELLS R EPRESENT FinFET S PECIFIC D IMENSIONS

that those approximations allowed a good technology benchmarking, we propose in the following some refinements of the models presented in Sections III and IV. A. Two-Layer Spacer

Fig. 14. Comparison of the ratio Ctot /Cgc versus year for ITRS data and our evaluation.

VI. M ODEL R EFINEMENT In the two previous sections, we considered that the spacer was composed of only one material, which is not the case in real devices. Indeed, in a gate-first approach, there is usually a SiO2 etch stop layer between the gate and the nitride spacer. In a gate-last approach, there is a high-κ dielectric layer between the metal gate electrode and the spacer. Moreover, we considered that the planar structure did not feature any raised S/D, which is not the case for high-performance strained technology and also for FDSOI and DG structures. Finally, we made the assumption that the spacer thickness is equal to the gate-to-contact distance and to the epitaxy-to-gate distance. Even if we considered

The modeling of a bilayered structure can be done by defining equivalent structures, which will depend on ε1 and ε2 values. If ε1 > ε2 , the fringe components are confined near the gate and are negligible in the second spacer, whereas if ε1 < ε2 , the fringe component is included in the two layers. It leads to the two equivalent structures shown in Fig. 15. Owing to those two equivalent structures, the outer-fringe capacitance can be evaluated with (7), by using in both cases the permittivity of the first spacer. The gate-to-contact capacitance is equivalent in both cases to two parallel-plate capacitances, respectively defined by ε1 , t1 and ε2 , t2 connected in series. Finally, the gate height corrections are determined from 2-D FlexPDE simulations and are shown in Fig. 15. The capacitance evaluation is done using (14). The comparison between our analytical model and 2-D FlexPDE numerical simulations is shown in Table VI and shows an excellent accuracy. B. Raised S/D The account of raised S/D can be added to the previous study. Fig. 16(a) shows a schematic view of the studied structure. In Fig. 16(b), a potential map generated with FlexPDE software shows the parasitic capacitance components to be modeled in the following. For the outer-fringe capacitance, (7) can be used directly after replacing tsp with t1 . The component Cgateepiflat is modeled as Cpccaflat in Section III, after replacing Hg with Hepi − tox   W Hepi − tox − t21 εspacer Cgateepiflat = . (41) t1

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Fig. 16. (a) Schematic representation and dimension of structure with raised S/D. (b) Potential map generated with FlexPDE with associated parasitic capacitance components.

Fig. 18. (a) Schematic representation and dimension of structure with raised S/D. (b) Potential map generated with FlexPDE with associated parasitic capacitance components.

Finally, the parallel-plate component of gate-to-contact capacitance model has to be replaced by (43), leading to   min(Hg−Hepi ,t2 ) εspacer W Hg +tmask −Hepi − 2 Cpccaflat = . t1 +t2 (45) C. Faceted Raised S/D Fig. 17. Ctot [sum of the four components described in Fig. 15(a)] analytical model versus numerical simulations for spacer 1 thickness variation for several spacer 2 thicknesses and epitaxy heights.

Cgateepitop is modeled as Cof , after replacing tsp with Hg − tox − Hepi , tox with t1 , and Hg with t2 , leading to Cgateepitop 2 = W εspacer sinh−1 π   min(Hg −Hepi , t2 )2 +2t1 min(Hg −Hepi , t2 )  × t1

W W ln π + 0.35εspacer . (42) π t1 Finally, Cpccaflat is modeled as in Section III   min(Hg−Hepi ,t2 ) W Hg +tox −Hepi εspacer 2 Cpccaflat = . (43) t1 +t2 Fig. 17 shows the good accordance of model with numerical simulations. Note that this model, designed for planar architectures, can be easily ported to 3-D devices. Indeed, for gate-to-epitaxy capacitance, only the component on the top of the fin has to be replaced by (41) and (42), yielding Cgateepi

In scaled CMOS technologies, below the 28-nm node, faceted raised S/D is becoming a standard [21]. To predict its impact on parasitic capacitance, we start from the schematic structure in Fig. 18(a) with the introduction of the facet angle α. We investigate the range of facet angle from 45◦ to 90◦ , typical for Si epitaxies on (100) substrate, in performing 2-D simulations with epitaxy height (Hepi ) variation and facet angle (α) variation by a step of 15◦ . As the facet angle only impacts the parallel-plate component of the gate-to-epitaxy capacitance (Cgepi_flat ), we simulate only the faceted surface and keep the same calculation for Cgepi_top and Cof developed in Section VI-B. The simulation kit and the parasitic capacitances of the structure are shown in Fig. 18(b). To evaluate Cgepi_flat component in the case of faceted S/D epitaxy, we considered that this capacitance is composed of elementary parallel-plate capacitances, equal to (εspacer /t1 + (y/ tan(α))) for a given height y. Then, we obtain an analytical expression by integration of those elementary capacitances from height y = t1 /2 + tox to Hepi . Note that integration does not start from zero in order to account for the fringe correction, similar to the calculation of Cpcca_flat treated in Section III-D1 H epi

Cgateepi

flat

= t1 2

εspacer dy y t1 + tan(α)

(46)

+tox

leading to onfin



= Nfin TSi Hepi −tmask − −1

min(t1 , Hg −tmask ) 2

εspacer t1

+N Si εspacer sinh  fin T min(Hg −Hepi , t2 )2 +2t1 min(Hg −Hepi , t2 )  × t1

TSi Nfin TSi ln π + 0.35εspacer . (44) π t1

 Cgateepi

flat

= W εspacer tan(α) ln 

t1 +

Hepi tan(α)

t1 +

tox + 21 tan(α)

t

 .

(47)

Fig. 19 shows the sum of gate-to-faceted-epitaxy and outerfringe capacitances. A good agreement between analytical model and numerical simulations is obtained, for epitaxy height, facet angle, and spacer thickness variation.

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Fig. 19. Cof + Cgateepiflat ; analytical model versus numerical simulations for facet angle variation for several spacer 1 thicknesses and epitaxy heights.

VII. C ONCLUSION In this paper, we have presented accurate and easily implementable capacitance models for the evaluation of parasitics in advanced CMOS technologies such as scaled bulk, FDSOI, planar DG, FinFET, and trigate, taking into account specific technologies such as the raised S/D and bilayer spacer in gate-first or gate-last scheme. All models have been validated through 2-D or 3-D numerical simulations. This model can be adapted to other structures such as quantum-well devices. ACKNOWLEDGMENT The authors would like to thank D. Hoguet for the help in the 3-D simulations.

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Joris Lacord was born in Saint Etienne, France, in 1986. He received the M.Eng. degree in semiconductor devices and microsystems from the Institut National Polytechnique de Grenoble (INPG), Grenoble, France, and the M.S. degree in microand nanoelectronics from Université Joseph Fourier, Grenoble, in 2009. He is currently working toward the Ph.D. degree at the Universite de Grenoble, Grenoble. He is currently with IMEP-LAHC, Minatec– INPG–CNRS, Grenoble, and also with STMicroelectronics, Crolles, France. His research interests are device analytical modeling and circuit level performance prediction, for advanced CMOS architecture benchmarking.

Gérard Ghibaudo was born in France in 1954. He received the M.S. degree from Grenoble Institute of Technology, Grenoble, France, in 1979 and the Ph.D. degree in electronics and the State Thesis degree in physics from the University of Grenoble, Grenoble, in 1981 and 1984, respectively. In 1981, he became an Associate Researcher at CNRS, Minatec–INPG, Grenoble, where he is currently the Director of Research and the Director of IMEP-LAHC located also at Minatec–INPG. During the academic year 1987–1988, he spent a sabbatical year at the Naval Research Laboratory, Washington, DC, where he worked on the characterization of MOSFETs. He has supervised over 74 Ph.D. students in his career. He was or is involved in several European research projects (a Joint Coordinator of BRA-NOISE and a participant to APBB, ADEQUAT 1-2-+, PROPHECY, ADAMANT, NANOCMOS, PULLNANO, FOREMOST, HONEY, MODERN, SQWIRE, UTTERMOST, etc.) or national programs (a Coordinator of RMNT-Ultimox and a participant to RMNTCMOS-DALI or ANR Multigate projects, etc). He is also a Member of the editorial board of Solid-State Electronics and an Associate Editor of Microelectronics Reliability. During his career, he has been the author or coauthor of over 350 articles in international refereed journals, 545 communications, and 61 invited presentations in international conferences and of 26 book chapters. His main research activities were or are in the fields of electronics transport, oxidation of silicon, MOS device physics, fluctuations and low-frequency noise, and dielectric reliability. Dr. Ghibaudo has been a member of several technical/scientific committees of international conferences [European Solid-State Device Research Conference, Workshop on Low Temperature Electronics (WOLTE), ICMTS 1996–2004, MIEL, ESREF, SISC 1996–2000, MIGAS, ULIS, IEEE/IPFA, ICMTD, FaN 2006, ICNF since 2005, INFOS since 2011, etc.]. He was a Cofounder of the First European WOLTE (1994) and an Organizer of 15 conferences/workshops/summer school during the last 15 years.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012

Frédéric Boeuf (M’08) was born in 1972. He received the M.Eng. and M.Sc. degrees from the Institut National Polytechnique de Grenoble, Grenoble, France, in 1996 and the Ph.D. degree from Université Joseph Fourier, Grenoble, in 2000. In 2000, he joined STMicroelectronics, Crolles, France, where he worked on the predevelopment phase of 65- and 45-nm CMOS technologies. He actively participated to the development of the MASTAR model, used for the definition of the 2005 to 2009 editions of the “International Technology Roadmap for Semiconductors” roadmap to which he collaborated. He is currently managing the Advanced Devices Technology Group working toward the 14-nm CMOS thin-film technology and disruptive technologies. He is an Industrial Advisor of several Ph.D. theses in the field of device integration and modeling. His fields of expertise are semiconductor physics and CMOS device physics. He served several European Commission-funded projects as a Work Package or Subproject Leader. He authored and coauthored over 135 publications, including book chapters, invited talks, and presented papers at several conferences in the field. He submitted several patents and served as a Reviewer for the main journals in the domain of physics, devices, technology, and microelectronics. Dr. Boeuf served as the Chair of the “CMOS Devices” Technical Subcommittee and the European Arrangement Chair of the International Electron Device Meeting Conference in 2007 and 2008–2009, respectively. He has been a member of the “Device Physics” Subcommittee of the “Solid State Devices and Materials” Conference since 2006, and he participated to the Technical Program Committee of the European Solid-State Device Research Conference in 2004–2005.