Available online at www.sciencedirect.com
Procedia Technology 6 (2012) 371 – 378
2nd International Conference on Communication, Computing & Security [ICCCS-2012]
Architecture Design and FPGA Implementation of CORDIC Algorithm for Fingerprint Recognition Applications b
a P.Revathi,M.Tech Student,Dept. of ECE,GMRIT,Rajam-532127,India M V Nageswara Rao, Professor, abG R Locharla , Asst.Prof., Dept. of ECE,GMRIT,Rajam-532127,India*
Abstract Fingerprint recognition is one of the most popular methods used by Biometric identification systems for personnel identification. CORDIC algorithm provides wonderful solution to perform the math intensive operations at the cost of few components like adder, shifter, multiplexer...Etc. Such math intensive operations are required to perform during the image enhancement phase of finger print recognition process. In this paper CORDIC based architecture is proposed to evaluate almost all the trigonometric functions. This is implemented using XILINX ISE 13.2. Performance of the architecture is analyzed in terms of relative error. © 2012 The Authors. Published by Elsevier Ltd.
© 2012 The Authors. Published by Elsevier Ltd. Selection and/or peer-review under responsibility of the Department of Computer Selection and/or peer-review under responsibility of the Department of Computer Science & Engineering, National Institute Science & Engineering, National Institute of Technology Rourkela of Technology Rourkela Keywords: FPGA; XILINX 13.2; CORDIC; LUT; FFT; AFIS;Gabor;VerilogHDL;
1. Introduction Fingerprints are completely formed at about seven months of fetus development and finger ridge pattern do not change throughout the life of an individual except due to accidents. This property makes fingerprints a very attractive biometric identifier.The fingerprint is characterized by minutiae, which are points where a curve track finishes, intersect or branches off. Taking a Fingerprint at first we enhanced the quality of that image to make the image clearer for easy further operations, because the fingerprint images acquired from sensors or other media are not assured with perfect quality. Therefore it is mandate to enhance the raw finger print for increasing the contrast between ridges and furrows and for connecting the false broken points of ridges due to
*
Corresponding author. Tel.: +91-995-995-7720. E-mail address:
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2212-0173 © 2012 The Authors. Published by Elsevier Ltd. Selection and/or peer-review under responsibility of the Department of Computer Science & Engineering, National Institute of Technology Rourkela doi:10.1016/j.protcy.2012.10.044
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insufficient amount of ink, are very useful for keep a higher accuracy to fingerprint recognition. Fast Fourier Transform and Gabor Filter are popular for fingerprint enhancement. FFT and Gabor are involves almost trigonometric evolutions. Proposed architecture in this paper contributes a CORDIC based module to the image enhancement part of AFIS (Automatic Fingerprint Identification System). This module can perform sin, cos, arctan, sinh, cosh, arcsinh, arctanh and ex functions. The CORDIC (Coordinate Rotation In Digital Computer) algorithm provides very smart solution to evolutes almost all the trigonometric functions with optimal usage of the hardware. 2. Review of CORDIC Algorithm CORDIC is a trigonometric algorithm, which computes the trigonometric functions using vector rotations. Transformation of the coordinates after rotation is defined by the CORDIC as follows:
xi 1 yi 1
K i [ xi K i [ yi
i 1
...(1)
d i xi 2 i ]
...( 2)
di
i
Ki
2.1. Circular functions: i 0,1,2,3...etc;
md i yi 2 i ]
... (3)
i
1 / (1 2
2i
) m
Rotation mode: di 1 if i 0; 1otherwise; z 1.7433; Vector mode: di 1 if yi 0; 1 otherwise; tan 1 ( y0 / x0 ) 2.2. Linear functions: i 0,1,2,3...etc; Rotation mode: di
1 if i
1; m 0;
Ki
0; 1otherwise; z
i
1
tanh ( y / x ) 0
0
1 if i 1.1182;
0; 1 ow; z
tan 1 (2 i )
i
1.7433;
2 i
1 Vector mode: di
2.3. Hyperbolic functions: i 0,1,2,3,4,4...12,13,13,14,...etc; Rotation mode: d i
1;
Ki
1 if yi
1 / (1 2
1.1182 Vector mode: d i
2i
1 if yi
) m
0; 1 otherwise; z
1;
i
y 0 / x0
tanh 1(2 i )
0; 1 ow;
3. Implementation of CORDIC Algorithm Proposed Architecture in this paper is hardware efficient, see Fig 1. Iteration controller manages the pseudo rotations and initialization of xi , yi and z i registers. En_clk is used to freeze the registers and counters when en signal is active low. Table 1. Operating modes of the proposed architecture S.No.
as
at
mode
Functions performed
1.
0
0
Rotation
sin and cos when
2.
0
1
Vector
arctan when
3.
1
0
Vector
arcsin when = 0; arcsinh otherwise
4.
1
1
N/A
N/A
= 0; sinh,cosh otherwise
= 0; arctanh otherwise
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Counter generates the iteration sequence according to and Arctan ROM provides either tan 1 (2 i ) or tanh 1 (2 i ) based on . Mux: M1 provides the initial values to be loaded into x 0 according to the mode described in Table.1. Sign controller generates the signal di according to the mode decided by the control inputs as shown in Table.1. Signal di holds logic 1 when d i in equations (1, 2 and 3) has to be -1 and holds logic 0 otherwise.
en
done
Iteration control
En Clk
clk
init
4
at at 1
0.6073
arg
16
0
1.2051
1 y 10 0 16 0 16 0 M3 0
En_Clk
M2
xi
1
M1
1
1
1
16
16
z0
0
20
En_Clk
20 M4
Counter
zi
yi 16
>>2-i
i Arch Tan/Tanh ROM
>>2-i
di
20
di
di
16
20
16 XOR
di
sign control
2 16 16
{at, as} zi[19] yi arg
Fig. 1. Proposed CORDIC architecture
4. Performance Analysis Performance of the architecture is measured in terms of the relative error. We define the error as the distance between the ideal value and the practical value divided by the ideal value:
Re lative error ( FunctionPC
FunctionCORDIC ) ( FunctionPC )
..... (4)
Proposed architecture is implemented in Xilinx ISE 13.2 using Verilog HDL and simulated using ISIM. FPGA Simulation outputs are manually taken into MATLAB to compare with theoretical numeric values and to compute & plot the relative error in each case, see appendix. A.
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0.05
Relative error in sin theta
Relative error in sin theta
0.045 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0
0
10
20
30
40
50
60
70
80
90
theta in degrees, 1 unit = 1 degree
(a) 0.08
Relative error in cos theta
Relative error in cos theta
0.07 0.06 0.05 0.04 0.03 0.02 0.01 0
0
10
20
30
40
50
60
70
80
90
theta(Angle in degrees), 1 unit = 1 degree
(b) 0.14
Relative error in arcsin
Relative error in arcsin
0.12
0.1
0.08
0.06
0.04
0.02
0
0
5
10
15
20
25
30
35
40
45
50
arg values, 1 unit = 0.02
(c) Fig. 2. Relative error in the result of following calculations performed by the CORDIC architecture (a) sin ;
; (c)sin-1 (arg)
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0.012
Relative error in arctan
Relative error in arctan
0.01
0.008
0.006
0.004
0.002
0
0
10
20
30
40
50
60
70
80
90
100
argument value, 1 unit = 0.02
(a) 0.025
Relative error in sinh(theta)
Relative error sinh 0.02
0.015
0.01
0.005
0
0
10
20
30
40
50
60
70
Theta(Angle in degrees), 1unit = 1degree
(b) 0.018
Relative error in coshh
Relative error in cosh(theta)
0.016 0.014 0.012 0.01 0.008 0.006 0.004 0.002 0
0
10
20
30
40
50
60
70
theta(Angle in degrees), 1unit = 1degree
(c) Fig. 3. Relative error in the result of following calculations performed by the CORDIC architecture (a) arctan(arg);
; (c)
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Relative error in arcsinh(argument)
0.018
Relative error in arcsinh
0.016 0.014 0.012 0.01 0.008 0.006 0.004 0.002 0
0
5
10
15
20
25
30
35
40
45
50
argument, 1unit = 0.0279
(a) 0.25
Relative error in arctanh
Relative error in arctanh 0.2
0.15
0.1
0.05
0
0
5
10
15
20
25
30
35
40
45
50
argument, 1 unit = 0.0183
(b) 0.02
Relative error in exp
0.018
Relative error in exp
0.016 0.014 0.012 0.01 0.008 0.006 0.004 0.002 0
0
10
20
30
40
50
60
70
theta(Angle in degrees), 1 unit = 1degree
(c) Fig. 4. Relative error in the result of following calculations performed by the CORDIC architecture (a) arcsinh; (b) arctanh; (c) ex
P.Revathi et al. / Procedia Technology 6 (2012) 371 – 378
5. Device Utilization Summery Architecture is implemented using Verilog HDL with XILINX ISE 13.2 software. XC3s500e-4fg320 device XST. For RTL schematic of the implementation, see Fig.5.
Fig. 5. RTL Schematic of the proposed architecture
Estimated device utilization summery generated by the XST tool is given in Table 2. Table 2. Resource utilization (estimated values for xc3s500e-4fg320 device) summery of the proposed architecture Resource Type
Used
Utilization
Number of slices
207
4%
Number of slice flip-flops
123
1%
Number of LUTs
386
4%
Number of bonded IOBs
94
40%
As seen in section.4, performance of the architecture can be appreciated throughout the range specified by the algorithm. Proposed architecture can adopt the improved CORDIC techniques without major hardware modifications. In addition, latency can also be minimized by applying the pipelined technique to the proposed one. Therefore it can be concluded that, proposed CORDIC architecture based IPs can be adopted by the image enhancement module of the Automatic Finger print Identification System. References Ray Andraka. A Survey of CORDIC Algorithms for FPGA based Computers. Kingstown, RI02852.
Andraka Consulting Group, Inc, North
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Appendix A. A.1. Sample of MATLAB code to generate relative error in sin and cos calculation by the proposed architecture
A.2. Sample window of ISIM simulation showing the sin and cos calculation by the proposed implementation
