FPGA Design and Implementation of MIMO-OFDM ...

FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Communications Networks Nguyen Trung Hieu1, Nguyen Thanh Tu2, Au Ngoc Duc1, Bui Huu Phu1 1 DCSELAB, University of Technology, Vietnam National University in Hochiminh City, Vietnam Email: {nguyentrunghieu, ngocduc, bhphu}@dcselab.edu.vn 2 University of Science, Vietnam National University in Hochiminh City, Vietnam Email: [email protected]

ABSTRACT A combination of Multiple-Input Multiple-Output Spatial Division Multiplexing technology and Orthogonal Frequency Division Multiplexing technique, namely MIMO-OFDM SDM systems, has been well-known as a potential technology to provide high speed data transmission and spectrum efficiency for modern wireless communications networks. Many technical papers have been evaluated the systems based on theory analyses and/or computer simulation, but just few ones have investigated the systems based on FPGA design, which is an important step before going to manufacture the integrated circuits. In the paper, we present our own design and implementation of three different MIMO-OFDM SDM systems on FPGA-based DSP Development Kit. Based on the design, we evaluate the bit-error rate performance of the systems and also consider the consumption of the FPGA elements in our design. The results have shown our successful design and implementation of the systems on FPGA hardware.

CONCLUSIONS MIMO-OFDM SDM technology has been considered a candidate for high speed wireless data transmission networks because of its significant increase of channel capacity and use of spectrum efficiently. In the paper, we have investigated the systems based on hardware design and implementation. We have shown our detailed design of three different systems on the FPGA-based DSP Development Kit. Based on the design, we have measured and evaluated BER performance of the systems. The results have shown that our design and implementation are successful. Here, we also considered the consumption of FPGA elements. It has shown the efficiency of our design.

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Access this article online Website: www.ijrws.org ISSN Citation Nguyen Trung Hieu, Nguyen Thanh Tu, Au Ngoc Duc, and Bui Huu Phu, “FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Communications Networks,” International Journal of Research in Wireless Systems (IJRWS), Vol. 2, Issue No. 2, pp. 26 – 33, June 2013 ISSN: 2320 - 3617

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue No 2, pp. 26 – 33, June 2013

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FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Network

I. INTRODUCTION A combination of Multiple-Input Multiple-Output Spatial Division Multiplexing technology (MIMO SDM) and Orthogonal Frequency Division Multiplexing (OFDM) technique has been considered as a potential technology for high speed data wireless transmission networks, such as IEEE 802.11, 3GPP Long Term Evolution, and WiMAX [1-5]. The MIMO SDM technology can significantly increase channel capacity by simultaneously transmitting multiple independent substreams with the same data rate and power level. Meanwhile, the OFDM technology can eliminate the effect of multipath fading and use given spectrum efficiently. There have been a lot of technical papers considered about the MIMO-OFDM SDM systems. They have been studied and evaluated the systems based on theory analyses and/or computer-based simulation [5-8]. However, there have just been few papers that investigated the systems based on their design and implementation on FPGA hardware, which is a very important step to evaluate the systems before going to design and manufacture integrated circuits of the systems [911]. In [9], authors presented the design and implementation results of a digital 120 Mb/s MIMO orthogonal frequencydivision multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. In [10], a prototype field programmable gate array (FPGA) implementation of an OFDM physical layer is shown using the Xilinx System Generator. In [11], authors presented an experimental broadband wireless 4x4 MIMO-OFDM system operating at two well-known WLAN frequency bands: 2.4GHz and 5.2GHz. The demonstrator is described placing special emphasis, both at the RF and DSP levels, on the design of reconfigurable hardware architecture. In the papers, authors have not considered the consumption of FPGA elements in their system design, which evaluate the efficiency of system design. In addition, a detailed design and implementation of the MIMO-OFDM systems have not fully described. The main contribution of the paper is to present our own design and implementation of the systems on the FPGA-based DSP Development Kit. A detailed design of full systems included transmit side, MIMO channel, and receive side is shown. The system performance is evaluated based on biterror rate (BER) criteria, and the efficiency of our design is shown through the calculation of the FPGA element consumption. This paper is divided into five parts as follows. After a brief introduction, an overview of MIMO-OFDM SDM systems is described in section II. In section III, we present the design and hardware implementation of the MIMO-OFDM SDM systems. The results and discussion of our implementations are shown in section IV. Conclusions are presented in final part.

II. MIMO-OFDM SDM SYSTEMS A. MIMO SDM Figure 1 shows the basic MIMO SDM NR x NT system. Let H denote as a channel matrix. The transmitted spatiallymultiplexed data and the corresponding received signal are T T presented by x = [x1, x2,…,xNT] and y = [y1, y2,…, yNR] , respectively. The received signal can be written by

,

(1)

T

where z = [z1, z2,…, zNR] is the white Gaussian noise, in which each zi is an independent Gaussian process with zero mean 2

and variance σ , H is MIMO channel matrix described as below:

h12 ⋅⋅⋅ h1NTX  h11  h22 ⋅⋅⋅ h2 NTX  h21 H = ⋮ ⋮ hij ⋮   hN 1 hN 2 ⋅⋅⋅ hN N RX RX TX  RX

   ,   

(2)

th

where hij is the channel response from the j transmit antenna th to the i receive antenna. Fig. 1. Block diagram of MIMO SDM system

To detect received signals, a receive weight matrix is used to detect the received signals as follows: , ,…, (3) There are some other kinds of receive weight matrix. In the paper we consider a linear detection method, zeros forcing (ZF) algorithm. Its weight matrix is given by

(4) B. MIMO-OFDM SDM System Fig. 2 shows a block diagram of MIMO-OFDM SDM systems. On each transmit antenna, the complex data stream is done by IFFT process, and then adds cyclic prefix signals to mitigate multipath effects. At the receive side, received signals are first removed cyclic prefix signals, and then converted to frequency domain by FFT process. Signals on each subcarrier are then detected by a receive weight matrix to obtain transmitted data.

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue No 2, pp. 26 – 33, June 2013

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FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Network

Fig. 2. Block diagram of MIMO-OFDM SDM systems

demodulation, add training symbol, FFT/IFFT, channels, Estimation and SDM decoder. Parameters of the simulation system we have designed are described in Table I. Fig. 4. Matlab Simulink simulation system

III. HARDWARE DESIGN OF MIMO-OFDM SDM SYSTEM In the section, we will present our own hardware design of 2x2, 2x3 and 3x3 MIMO-OFDM SDM systems using 4-QAM on Simulink platform, Altera DSP builder library and Altera Quartus II software for Verilog coding. The process of our design consist of three main steps: Matlab Simulation, Verilog HDL Design and Synthesis as shown in Fig.3. Fig. 3. Process of designing

TABLE I. SIMULATION SYSTEM PARAMETERS The number of transmit antennas The number of receive antennas Modulation FFT/TFFT Estimation Multipath Channel Feedback Channel model Data rate

2, 3 2, 3 QBSK, 16QAM 64 points Preamable 8x8 Hardamard Exponential channel Ideal 2, 3

B. Verilog HDL Design

A. Matlab Simulation The design of a simulation system on Matlab Simulink is absolutely necessary before we start to design system with Verilog HDL. It not only provides the results we use to compare, but also is the foundation on which we can set the required parameters as well as easily debug errors for hardware model. Figure 4 shows us a design of 2x2 MIMO-OFDM SDM system on Matlab Simulink. It includes blocks: modulation,

The system design with Verilog HDL has disadvantages such as long design time, difficult simulation and debugging error. It also requires the designer to master the theory and have good experience in their subject. To overcome this, we can design system by switching from C to HDL language or the use of IP core already completed. However, both methods have two common drawbacks. First one, it's taking a very high cost to purchase licensed programs or get the ownership of the IP core. Second, it's not high academic. Therefore, considering the advantages of the design in Verilog, reducing costs to a minimum while being highly academic, we have decided to use this method for your system. The objective of this paper is to design the MIMO-OFDM SDM systems on hardware. After reviewing the results of from Simulink Matlab simulation system, we decided to use fixedpoint 10.22 to reduce the consumption of resources comparing to the floating point. The system is divided into three main parts: transmitter, channel and receiver. 1) Transmitter

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue No 2, pp. 26 – 33, June 2013

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FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Network

At the transmitter, two serial bit streams are modulated by using 4-QAM. The symbols after that are grouped into a pair of 64 symbols. They are converted to the time domain by IFFT algorithm, and, finally, they are sent on two different antennas at the same time slot. Each of the signals includes two parts: in-phase (I) and Quadrature (Q) components, as shown in Fig. 5.

Fig. 7. Constellations of 4QAM.

Fig. 5. Transmitter

c) OFDM modulation block The main point of OFDM technique is to employ FFT/IFFT algorithm for creating orthogonal sub-carriers. On each antenna, a group of 64 complex symbols is transformed to time domain by taking IFFT algorithm. The output of the IFFT algorithm is:

The transmitter consists of three main parts: Data generation, digital modulation, and OFDM modulation. a) Data generating module At first, two bits data are created prior to entering 4QAM modulation module. The counter values are saved into Look up Table (LUT). LUT carries out a random database based on the input data, as shown in Fig. 6.

j 2π nk 1 N −1 x(n) = ∑ X ( k )e N N k =0

(5)

After that, a cyclic-prefix data (CP) is inserted at the beginning of OFDM symbol. The block diagram of IFFT algorithm and add CP (or GI) module are shown in Fig. 8. Fig. 8. IFFT and add CP modules

Fig. 6. Data generating module

b) Modulation module The modulation module uses 4QAM modulation and applies LUT method. The content in the LUT at the address includes values of -1 or 1. The constellation of 4QAM is shown in Fig. 7. The preamble training data sequences are added into the original data for channel estimation after modulating. Here we use 8 bits orthogonal Hadamard matrix for channel estimation.

2) Multipath fading channel In this experience, the channel is modeled as a selected frequency fading channel. The number of channel paths we used is 16, and their power delay profile (PDP) follows the exponential function, with 1 dB degradation between two adjacent paths. Fig. 9 shows the PDP of multipath fading channels. Each of the impulse responses hi,j of the channel th th corresponding to j transmitter to i receiver antenna. It is considered as Rayleigh channel. The real and imaginary parts of hi,j obey Gaussian distribution, which have mean of 0 and variance of ½.

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue No 2, pp. 26 – 33, June 2013

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FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Network

Fig. 9. Power delay profile

a) OFDM demodulation The received signal on each antenna is firstly removed CP, and then converted to frequency domain by FFT algorithm as shown in Fig. 12. The output of FFT module: N −1

X ( k ) = ∑x ( n) e

− j 2π nk N

(6)

n=0

Fig. 12. Remove cyclic prefix and FFT hardware modeling

The received signals are also affected by AWGN noise. Thus, each of them is passed through two modules: multipath Rayleigh and AWGN noise. The hardware description is showed in Fig. 10. Fig. 10. Multipath Rayleigh and AWGN channel modeling

b) Channel estimation module At the receiver, the channel coefficients hi,j are estimated by using preamble training sequences which were created at the transmitter as shown in Fig. 13. The channel coefficients after that are used for extracting data. Fig. 13. Channel estimation module

3) Receiver Site The hardware receiver description is shown in Fig. 11. It mainly includes 4 processing block: OFDM demodulation, channel estimation, ZF decoder, and digital demodulation. Fig. 11. Receiver

c) SDM ZF/MMSE decoder Detector modules of MIMO-SDM systems are placed after estimation module. By performing ZF algorithm detection which was described in section II above, we can take the complex data streams back. d) 4QAM demodulation module At the receiver, the complex data streams are demodulated by “4QAM demodulation module”. After that, we compare the received bit stream to the transmitted bit stream to calculate BER performance of the systems.

IV. EXPERIMENTAL RESULTS In this section, we present the results of the MIMO-OFDM SDM systems using QPSK and 16QAM modulation.

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue No 2, pp. 26 – 33, June 2013

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FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Network

A. BER performance of designed hardware-systems First, Figure 14 shows a comparison between the BER (bit error rate) for hardware designs. Here, we implement hardware models in various cases such as changing the numbers of transmit antennas, changing the number of receive antennas or modulation. Fig. 14. MIMO-OFDM SDM Zero Forcing

than the other systems. BER performance of 3x3 system is worse than that of 2x2 system. This is because the ZF algorithm could not eliminate noise components, thus noise power increase proportionally to the number of antennas. Figure 15 is the result of SDM MIMO-OFDM systems on hardware using different detection algorithms, namely the Zero Forcing (ZF) and MMSE. From this result we can see, the quality of the systems using ZF detection algorithms are always worse than the MMSE systems. From the results in Figure 8 and Figure 9, it is easily seen that the OFDM technique has well resistant to multipath interference; quality of system is ensured because of inserting the guard interval. This is one of the main advantages when of OFDM technique. Fig. 16. BER of coded systems

Fig. 15. BER of systems using ZF and MMSE

Figure 16 is the BER of the MIMO-OFDM SDM systems using Zero Forcing algorithm with channel coding. We can see, at the high SNR, quality of coded systems is better than noncoded ones. However, at low SNR, the quality is not good due to noise is too high. That makes the channel decoder using the Viterbi algorithm be not correct. B. FPGA Synthesis Results

BER performance of our own designed 2x2, 2x3 and 3x3 MIMO-OFDM SDM systems on FPGA hardware is shown in Fig. 14. Here, we can see the BER performance of 2x3 system obtains the best result due to getting higher diversity order

After designing and simulating the system, the Verilog code is synthesized on the FPGA using Quartus 9.1 software. Hardware system is compiled on FPGA Stratix III 3SL150F1152C2. Table I shows the hardware cost for MIMO-OFDM SDM 2x2 system. From this table, we can easily see that the sum of all the registers, logic gates is used only about 45% of the total resources. This is the reason that we decided to select 32 bits to represent the parameters of the system and all the

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue No 2, pp. 26 – 33, June 2013

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FPGA Design and Implementation of MIMO-OFDM SDM Systems for High Speed Wireless Network

calculations are done on 32-bit fixed-point number to increase the accuracy of the process. TABLE II. HARDWARE COST OF MIMO-OFDM SDM 2X2 Consumption Dedicated Logic Registers

The number in Model

Max Speed

Combinational ALUTs

(MHz)

Max: 113,600

Modulation

2

420

0 (0%)

20 (