Architecture selection for a Multi-Standard DECT/Bluetooth Front-End in 0.18 µ m CMOS Vojkan Vidojkovic, Johan van der Tang, Arjan Leeuwenburgh ∗ , and Arthur van Roermund Eindhoven University of Technology (TU/e), Mixed-signal Microelectronics (MsM) Group, EH 5.28 P.O. Box 513, 5600 MB Eindhoven, The Netherlands phone: +31 40 247 3393, fax: +31 40 245 5674 email:
[email protected] ∗ National Semiconductor, ’s-Hertogenbosch, The Netherlands Abstract— Architecture selection is one of the key steps in a multi-standard front-end design flow. By choosing a suitable front-end architecture, problems in the building block design (DC-offsets, flicker noise, high power consumption) can be avoided. In this paper the selection of the most suitable architecture for a multi-standard front-end for DECT and Bluetooth is presented. An important selection criterion is the flexibility of an architecture for different wireless standards, but some other selection criteria are also used: robustness of an architecture to the technology scaling, level of integration, image rejection, power consumption and chip area. Taking into account the fact that modern CMOS technologies migrate fast towards deep submicron processes and in order to alleviate a front-end redesign in new CMOS technologies, special attention is paid to develop a realistic scaling scenario end to evaluate their consequences on the architecture selection. Starting from a generic front-end architecture, six architectures are evaluated. According to a qualitative analysis, a quadrature low-IF architecture with adaptive image rejection shows the best performance considering the selection criteria. Keywords— Multi-standard front-end, scaling, front-end architecture selection, low-IF architecture
I. INTRODUCTION
gies migrate fast towards deep submicron processes and a facilitated front-end redesign in new CMOS technologies is important in order to reduce time to market. Nowadays receivers operate in congestive radio environment and the ability to provide high image rejection is crucial for high reception quality. A front-end solution that satisfies the specifications under the worst conditions is very expensive. It is important to take into account the fact that radio environment is not constant and the power consumption can be reduced by applying solutions for adaptive image rejection. The minimization of the power consumption reduces the battery size and provides a longer talk time. Considering that the IC package represents a significant part of a chip price, it is important to reduce the die size and pin count. Starting from a generic receiver architecture (see Fig.1), six front-end architectures are discussed. Applying the selection criteria the most suitable architecture for a DECT/Bluetooth multi-standard front-end will be selected.
complex filtering
The wireless market is changing very rapidly. Pushed by customer requirements new standards for wireless commutations are emerging fast creating a congestive radio environment with a lot of interference. So far, most of the research in the area of wireless communications is directed to obtain cost-effective front-ends dedicated to one standard, but now in order to reduce costs by hardware reuse and to increase functionality and flexibility of a front-end, designers try to develop solutions for multistandard front-ends. The first step towards an implementation is to find a front-end architecture that has enough flexibility to accommodate the requirements of selected standards. An architecture must show a high robustness to technology scaling because modern CMOS technolo-
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complex mixing
complex filtering
complex mixing
...
complex filtering
ADC
DSP
Fig. 1. Generic receiver architecture
The most simple architecture is RF-sampling (see Fig.2). Due to its almost full digital nature, the RF sampling architecture is very flexible and it can be scaled very easily, but unfortunately the requirements for analog to digital converter (ADC) are the bottleneck. The ADC RFF LNA
ADC
DSP
Fig. 2. RF-sampling architecture
must have very high sampling frequency (few GHz) and a high number of bits (more than 10) [1]. With current technology, the power consumption and occupied chip area are too high and this architecture is not feasible and architectures that employ more analog signal processing are normally used. The paper is organized as follows. Few different scaling scenarios are discussed in section 2. A superheterodyne architecture is investigated in section 3. The main properties of a zero-IF architecture are given in section 4. A low-IF architecture with its derivatives is presented in section 5. II. SCALING SCENARIOS Varying the design parameters of a simple analog circuit (a common source amplifier can be taken as an example) and monitoring the analog circuit performance (signal to noise ratio, power consumption, bandwidth) it is possible to investigate the influence of technology scaling to analog circuits and to define appropriate scaling scenarios. In this case the design parameters are: aspect ratio (W /L) of MOST, overdrive voltage of MOST (Vgs − Vt , where Vgs is the gate-source voltage and Vt is the threshold voltage) and supply voltage (Vdd ). The mentioned analog circuit performance (in the case of common source amplifier) can be described by the following equations: • the bias current of a MOST in the saturation (Ib ) is given by: Ib = 12 µnCox WL (Vgs −Vt )2 where µn is the electron mobility, Cox is the gate oxide capacitance per unit area, W is the channel width and L is the channel length. • the power consumption of the circuit can be calculated as: P = Vdd Ib • the transconductance (gm ) of MOST can be expressed by: gm = µnCox WL (VGS −Vt ) • in the saturation, neglecting the overlap capacitance, the gate-source capacitance can be approximated as: Cgs = ε0 εox 2 3 W LCox , Cox is defined as: Cox = tox where tox is the oxide thickness and can be approximated as t ox = L/50 [2]. • the total channel capacitance can be calculated as: C ch = W LCox . • the dynamic range is equal to signal to noise ratio when the thermal noise is taken as a bottom limit and given by: 2 s gm DR = V4kT γ , where Vs is the signal level. • the bandwidth (BW ) of the common source amplifier that is loaded with another common source amplifier can be approximated by: BW = gCm where C is the gate-source capacitance of MOS transistor in the second common source amplifier. • the mismatch of two identical and closely spaced MOS transistors can be characterized by the variance of the rel-
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ative current difference ( ∆II ) when the transistors are biased with the same Vgs voltage and by the variance of their gate-source voltage difference when they are biased 4AV2 th with identical bias current (Ib ) [3]: σ 2 ( ∆II ) = W1L (V −V , )2 GS
th
AV2 th WL ,
σ 2 (∆VGS )
= where AVth is the matching parameter. It is very important to emphasize that AVth scales down linearly with the technology [4]. The improvement of the performance of digital circuits by scaling can be achieved by scaling down the MOST dimensions (W and L) and voltage supply (Vdd ) with factor s (s > 1) [2]. The most important consequence of digital scaling is a big deterioration of the dynamic range. This is the main reason why such a scaling scenario can not be applied on analog circuits. In order to keep dynamic range constant it is necessary to scale MOST width with factor 1/s. Such scaling scenario is suggested in [2] as an analog scaling and represented in Table I. The other TABLE I A NALOG SCALING
L s B 1/s
W 1/s Cch 1/s
Vdd s Cgs 1/s
Vs s P 1
Ib 1/s DR 1
gm 1/s2 AVth s
tox s 2 σ (∆VGS ) s2
Cox 1/s 2 σ ( ∆II ) 1
consequences of the analog scaling scenario are: power consumption stays the same, bandwidth is increased, capacitances are increased and matching gets better. They will be taken into account in the front-end architecture selection. III. SUPERHETERODYNE ARCHITECTURE A double-conversion superheterodyne architecture is presented in Fig.3. The major problem in the superheteroHigh Frequency Image Reject Filter (HFIRF) RFF
IFF LNA
IFIRF ADC
VGA
LO1
DSP
LO2
Fig. 3. Double-conversion superheterodyne receiver architecture
dyne architecture is the integration of the high frequency image reject filter (HFIRF). The requirements for such filter are very high and they will be calculated for DECT and Bluetooth. The quality factor (Q) of such a filter can be expressed as Q = f c /B where f c is the filter center frequency (for DECT f c = 1.9 GHz) and B is the filter bandwidth. For 50 MHz < B < 200 MHz, Q is between 38 and 9.5. For Bluetooth Q will be higher because f c = 2.4 GHz.
The filter order is determined by the required image rejection ration (IRR). The image signal is situated at the frequency: fi = fw − 2 fIF where fw is the center frequency of the wanted signal. Concerning the interference performance and radio receiver blocking requirements [5], it follows that the level of the image signal will depend on f IF . So, the required image rejection and filter order will be function of f IF . The filter order estimation will be done for DECT. It will be required that the image signal must be 20 dB below the wanted signal in order to avoid corruption of the wanted signal. For this amount of image suppression, the required filter order (n) as a function of the fIF is depicted in the Fig.4(a) and Fig.4(b). It was assumed that the filter bandwidth is B = 100 MHz. As it can 170.0
Filter order (n)
105.6
73.4
41.2
I Q
40
50
IF [MHz] (a)
60
I/Q
LO
generator
Fig. 5. Zero-IF architecture
capacitance and the junction capacitance at the source. The substrate resistance (Rs ) together with the gate-source and the source junction capacitance forms a low-pass filter. The source junction capacitance can be approximated gate Cgs
+
n
drain
NF [dB] 30
+
n
25
channel 9.6
15
Cs
8.4
p
Rs 6.0
20
depletion region
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10 5
substrate 9.0
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VGA
RFF
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137.8
Filter order (n)
LPF
60
70
80
90
(a)
100
IF [MHz] (b)
Fig. 4. The HFIR filter order as a function of intermediate frequency
be seen the requirements for the HFIRF are very high and such filter can not be integrated while discrete solutions are very expensive [6]. Such discrete filters will cause a higher power consumption because the low noise amplifier (LNA) will be loaded with 50 Ω input impedance of the HFIR filter and LNA needs a lot of power to achieve a reasonable gain of 10 to 15 dB. The main disadvantages of the superheterodyne architecture are: low flexibility for different standards, no possibility to implement adaptivity and to make trade-off between IRR and power consumption and high cost because of external components. These are the reasons why this architecture is not selected. IV. ZERO-IF ARCHITECTURE A zero-IF architecture is represented in Fig.5. DCoffsets are the major problem in the zero-IF architecture. They overlap with the down-converted wanted signal and corrupt it reducing the receiver sensitivity. DC-offsets are result of self-mixing, which depends on capacitive and substrate coupling. It is important to see the influence of analog scaling on capacitive and substrate coupling. Fig.6(a) shows the mechanism how the signal from the gate can leak into the substrate through the gate-source
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0 0.5 1
2
3
4 f if [MHz]
(b)
Fig. 6. (a)Signal leakage through capacitive coupling (b)NF of Gilbert cell mixer as function of intermediate frequency
by [2]: Cs = W E Wεsid where W is the MOST width, E is the length of the source region, εsi is the dielectric constant of the silicon and Wd is the width of the depletion region. Since, by applying the analog scaling scenario, W will be scaled with 1/s and E with s, the source junction capacitance will be inversely proportional to Wd . Wd can q 2εsi 1 1 be approximated with [2]: Wd = q ( NA + ND )(φB +VR ) where NA and ND denote the doping levels, φB is the junction built-in voltage and VR is the reverse-bias voltage that is equal to zero in the case of the common source amplifier. It can be shown that in the case of the analog scaling when NA and ND scale with s, the width of depletion region reduces. This means that the source junction capacitance will increase and together with the increasing of Cgs (see Table I) move the pole of the mentioned low-pass filter towards higher frequencies, which makes the coupling stronger and thus to the DC-offsets problem greater. It is very difficult to predict, model and characterize DC-offsets because it is not possible to take into account and to determine the level of all capacitive and substrate couplings, that are present on an integrated circuit. The method for the DC offsets cancellation depends, very much, on the standard for which a front-end is applied. AC coupling can not be applied in the systems with the modulation schemes having the highest energy at the cen-
tral frequency in their spectrum and this is the case with DECT and Bluetooth. Even if it is applied the capacitors must be very big in order to filter out as less as possible signal energy. Such big capacitors will occupy too much chip area. DC-offsets cancellation in the digital domain can be applied in the systems with Time Division Multiple Access (TDMA) technique where the blind slots are implemented. With a tendency to increase the system capacity, the number of blind slots will be reduced making troubles for these DC-offsets cancellation techniques. The flicker noise severely deteriorates the noise figure of zero-IF front-end, which reduces the front-end sensitivity. In order to see the effect of flicker noise on a mixer noise figure (NF), the simulations are done with a standard mixer topology (Gilbert cell). The Gilbert cell mixer is designed in 0.18 µ m CMOS technology. At very low frequencies the flicker noise is dominant and NF increases very fast (see Fig.6(b)). At higher frequencies the flicker noise decreases and the thermal noise starts to dominate. At the frequencies higher then the corner frequency, NF decreases very slowly. So, there is no reason to go with f IF higher than few MHz, but certainly it is necessary to avoid zero fIF and an unacceptable corruption of sensitivity. The 2 flicker noise can be expressed as: V n = K/(CoxW L f ), where K is technology dependent constant. It is difficult to predict the behavior of K with scaling and in new CMOS technologies. This fact makes the flicker noise estimation very difficult. The main advantages of zero-IF architecture are the following: first, low requirements for low-pass filters and ADC and second, it is not necessary to provide high IRR because the image signal is basically the wanted signal but located at the negative frequency in the spectrum. Typically IRR of 20 to 25 dB is enough and this can be easily achieved with an I/Q generator implemented as a RC polyphase filter [7]. Although the zero-IF architecture has clear advantages, it can be selected as the most promising one only in the case of smart solutions for DC-offsets and future technologies that will provide low level of the flicker noise. At the moment DC-offsets and the flicker noise are big drawbacks and this architecture is not selected. V. LOW-IF ARCHITECTURES The quadrature low-IF architecture is represented in Fig.7 In this architecture the RF signal is down-converted to a low IF,that is typically few MHz. In that way problems like a high level of the flicker noise and DC-offsets are avoided. This represents the main advantage of the low-IF architecture. Since the IF is a few MHz, the ADC requirements are not high. Another advantage of the low-IF archi-
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I path VGA
RFF
IF polyphase filter (IFPF)
LNA
DSP Q path VGA
I Q
I/Q generator
ADC
ADC
LO
Fig. 7. Quadrature low-IF architecture
tecture is that the image rejection is done after the downconversion, by the IF polyphase filter. So any changes in the system operating frequency can be solved by using another local oscillator (LO) frequency, down-converting the RF signal to the same IF. This makes quadrature low-IF architecture very flexible in terms of different standards. The maximal achievable IRR depends on the matching in the I and Q branches in the LO path. If the I/Q generator in the LO path is implemented as RC polyphase filter, which is the most frequent and most straightforward implementation, then achievable IRR will be limited by the spread in the absolute value and mismatches between resistors and capacitors in the RC polyphase filter. In [7] it was shown that with the two stage RC polyphase filter assuming the spread in the absolute value of 20% for resistors and 16% for capacitors and a mismatch of 1%, IRR of about 28 dB can be obtained in the frequency range 1.8 − 2.5 GHz. This is enough for DECT, but may not be high enough for Bluetooth because Bluetooth is located in ISM band (free band) where the interference is high. It is also interesting to provide a solution for an adaptive image rejection and to make trade-off between IRR and power consumption. There are two reasons for that: first, for DECT a high IRR is not necessary because the interference is not so high and even for Bluetooth the radio environment is not always constant and it is beneficial to monitor the level of interferers and when they are high to provide a high IRR or when they are low to reduce IRR and save power. This can be done in three ways: • First one is to increase IRR in the digital domain. In this case the flexibility is very high and it is easy to implement an adaptivity but it is necessary to pay attention on a complexity of algorithms and computational power in terms of number of transistors that is necessary to handle such algorithms. • The second possibility is to apply I and Q correction in the analog domain after the down-conversion. In this case the bottleneck is the accuracy of an analog system that has to do the correction. • The third and most straightforward way is to implement a RF polyphase filter (that can be a RC polyphase fil-
ter) before the down-conversion [6]. In that way doublequadrature low-IF architecture is obtained. A full analysis of this architecture is given in [7]. A modified doublequadrature low-IF architecture that allows adaptive image rejection is represented in Fig.8. RF buffers 1,2 and 3 repMX1
+
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MX2
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polyphase filter
buf1
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+ buf3
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I
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+ I
IF polyphase filter Q path (IFPF)
+
RF
E2
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I/Q
generator
generator
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LO2
−
RF
RF
ADC
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I path
RF
buf2
I path +
I/Q generator
DSP
Fig. 9. Wide-band IF double-conversion architecture
ADC
LO
I
−f w
−f i
X rf
0
X lo 1
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−f lo1
A i p1
A w+
fi
fw
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A lo 1
A lop1
resent an identical circuit. RF buffer 1 and 2 help to obtain higher gain and better sensitivity. They can be considered as a second stage of the LNA. RF buffer 3 is a dummy circuit and its purpose is to provide symmetrical load for RF polyphase filter. Otherwise, the mismatch between I and Q paths will to high and IRR will be significantly corrupted. The image level estimator has the task to estimate the level of an image signal and to generate the control signals E1, E2 and E3. If the image signal is strong then signal E2, E3 and E1 will enable operation of RF buffer1, MX3 and MX4 and disable the operation of RF buffer 2. In that way RF polyphase filter will be in the signal path and it increases IRR. The analysis and estimation of achievable image rejection is presented in [7]. It was shown that it is possible to achieve a maximum IRR of 63 dB. If the image signal is weak then signals E2, E3 and E1 must disable operation of RF buffer1, MX3, MX4 and enable operation of RF buffer2. In that way lower IRR is obtained but the power consumption is reduced and better sensitivity can be achieved because RFPF is bypassed. Signal E1, E2 and E3 can be also generated externally avoiding the need for the image level estimator. In that way static adaptivity will be obtained and can be used to achieve high IRR for Bluetooth and low IRR for DECT but to increase the sensitivity and reduce the power consumption. A wide-band IF double-conversion architecture [8] is another type of low-IF architecture. It is represented in Fig.9. The main idea was to try to avoid the passive RC polyphase filter in the RF path. It looks that a high IRR can be obtained with this architecture, but a careful analysis of the down-conversion process gives a negative answer. The first step in the down-conversion process is depicted in Fig.10. In this down-conversion step, the RF signal is down-converted to the first intermediate frequency (IF1 ). Aw is the amplitude spectrum of the wanted signal, A i is
A i+ ~ ~
Ai − ~ ~
Fig. 8. Double quadrature - low IF architecture with adaptive image rejection
Aw−
A i d1
IF1
f
A wp1
f
Fig. 10. The first step in the down-conversion process
the amplitude spectrum of the image signal, A lo1 is the amplitude spectrum of the I and Q signals in the LO path of the first down-converter, Alop1 is the amplitude spectrum of the signal component caused by the mismatches in the LO path of the first down-converter. The signal A ip1 is the result of the convolution between the signals A i+ and Alop1 . It falls in the band of the down-converted wanted signal Awd1 and it corrupts it. Aid1 is the down-converted image signal and the signal Awp1 is the result of the convolution between the signals Aw+ and Alop1 . In the second downconversion step, the signal from the first intermediate frequency (IF1 ) is down-converter to the second intermediate frequency (IF2 ) and it is identical to the first downconversion step. As it can be seen from Fig.10, the first down-conversion step will put a limit on the image suppression and the final effect will be the same as in the case of the quadrature low-IF architecture. So, with the wideband IF double-conversion architecture it is not possible to achieve a high IRR as in the case of double-quadrature low-IF architecture while six mixers and two local oscillators are used and they increase significantly the power consumption. This is a big drawback and this architecture is not selected. The double-quadrature low-IF architecture shows good flexibility for different standards, high level of integration and possibility to implement adaptive image rejection. This architecture is most suitable for a multi-standard
DECT/Bluetooth receiver. An achievable image rejection depends on matching, which becomes better with scaling (see Table I). So in new CMOS technologies even higher IRR can be expected. In the circuit level design the attention must be paid to reduce power consumption and chip area. VI. CONCLUSIONS A qualitative analysis of six different front-end architectures is presented. The selection criteria for a DECT/Bluetooth receiver are clearly defined and include robustness of an architecture to the technology scaling, level of integration, image rejection, power consumption and chip area. In order to allow an easy redesign in new CMOS technologies, special attention is paid on the consequences of the technology scaling. According to the presented qualitative analysis, the double-quadrature lowIF architecture shows the best performance. The concept of an adaptive image rejection is introduced. It makes a trade-off between image rejection ratio, sensitivity and power consumption. ACKNOWLEDGMENTS The authors would like to thank the Technology Foundation STW for the financial support.
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R EFERENCES [1] B. Razavi, CMOS RF Receiver Design for Wireless LAN Applications, Radio and Wireless Conference (RAWCON), 1999, pp. 275 - 280, 1999. [2] B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 2001. [3] J. Kinget, et al., Impact of transistor mismatches on the speedaccuracy-power trade-off of analog cmos circuit, Custom Integrated Circuit Conference, 1996, pp. 333-336. [4] K. Bult, Scalability of wire-line analog front-ends, Advances in Analog Circuit Design, 2001. [5] ETSI DECT Standard, TBR6-Technical Basis for Regulation, 1999. [6] J. Crols, et al., Low-IF Topologies for High performance Analog Front Ends of Fully Integrated Receivers, IEEE Transactions on circuit and systems-II: analog and digital signal processing, vol. 45, no. 3, pp. 269-282, 1998. [7] V. Vidojkovic, et al., Analysis of an 1.8 - 2.5 GHz Multi-Standard High Image-Reject Front-End, International Conference on Electronics Circuits and Systems, 2002. [8] J. Rudell, et al., 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications, IEEE Journal of Solid State Circuits, vol.32, no. 12, pp. 2071–2087, 1997.
