Abstract. In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation.
At-Speed Testing with Timing Exceptions and Constraints -Case Studies Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato*, Toshiharu Asaka*, Takashi Aikyo* Mentor Graphics Corporation 8005 SW Boeckman Rd. Wilsonville, OR 97070
Abstract In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during atspeed ATPG has been presented in [1][2]. The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism. Keywords: At-speed test, static timing analysis (STA), Synopsys Design Constraints (SDC), timing exceptions, timing constraints, false paths, multicycle paths.
1.
Introduction
Scan-based stuck-at test pattern generation methodology has matured, and it has been widely applied in high volume manufacturing (HVM). However stuck-at test patterns are no longer sufficient to achieve high product quality in nanometer technologies. Resistive bridges and vias, power droops, cross-talk noise effect, etc. may manifest in subtle timing changes that require atspeed tests to detect [3][4]. At-speed testing has become necessary to guarantee high product quality and low defective parts per million (DPM) [4][5]. At-speed scan patterns typically consist of a relatively slow scan operation followed by two or more fast clock pulses applied at or near functional frequency [6][7][8][9]. One of the challenges in generating at-speed scan tests is to avoid false failures on the tester due to exercising paths that are not designed to propagate logic values within a single clock cycle [1][2][5][10]. These paths are known as timing exception paths, and they include false paths, multicycle paths, and conditional false paths. False paths are not exercisable in the functional mode of operation, but may be exercisable during scan testing. Multicycle paths are designed such that expected values are only available at the destination after some specified number of clock cycles. Conditional false paths are false paths along
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Semiconductor Technology Academic Research Center* Yokohama, Japan with boolean conditions. If the associated condition is violated, the effect of the false path needs to be considered. The timing exception paths can be derived from timing exceptions and constraints provided by designers to Static Timing Analysis (STA), synthesis, and layout tools. They allow the tools to better optimize a design by relaxing timing constraints and overriding the default single-cycle clock constraint. This data is usually provided in the Synopsys Design Constraints (SDC) format. Considering timing exceptions and constraints is essential to generating correct-by-construction at-speed test patterns that achieve high quality and avoid yield loss. The traditional method [10] to generate at-speed test patterns involves extracting cell constraints and generating patterns under these cell constraints. These cell constraints mask the state elements that are either the source or the destination points of the timing exception paths. The cell constraints-based method suffers from several limitations. First, generating a complete set of cell constraints is error prone, and can be a tedious process. Second, while generating cell constraints the path information is lost, and it can mask out valid transitions. The inherent pessimism in this approach results in increasing the number of unknowns in the test response. Hence the test coverage drops, and the test quality suffers. This also lowers the efficiency of on-chip scan compression schemes [11][12][13][14]. A new path-oriented approach to handle timing exception paths during at-speed scan pattern generation has been proposed in [1][2]. This method can be applied to any fault models. This new method directly reads in the timing exceptions and constraints provided in the standard SDC format, and uses this information to generate correct-by-construction at-speed test patterns. This method minimizes the number of unknowns by accurately analyzing the sensitization of timing exception paths in each test pattern during its creation. The at-speed test patterns generated by the proposed method significantly cut down the pattern debugging time on the automatic test equipment (ATE) by eliminating mismatches caused by timing exceptions. Reducing unknowns in the test responses results in improving both test coverage and test compression. This method is far superior to the traditional cell constraint-based static masking methodology in terms of 1) ease of use, 2) test coverage and 3) test compression.
If at-speed patterns are generated without SDC information and then simulated with the extracted timing information to compute the final test responses, the resulting patterns can still produce mismatches on the ATE. The extracted timing information from circuit layout may not be accurate, and it is impossible to simulate the design with timing at all possible process corners. Hence this is not a robust method. The paper is organized as follows. The next section describes the at-speed test pattern generation flow using conventional ATPG or Embedded Deterministic Test (EDT) [11] in the presence of timing exceptions and constraints. The algorithmic details are reviewed in section 3. Section 4 presents the test cases created by STARC, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without any pessimism. Results on large industrial circuits are presented in section 5, and conclusions are drawn in the last section.
2.
Consider the circuit shown in Figure 1. The timing exception “set_false_path –from [get_pins {U2/CK}] – through [get_cells {G1}] –to [get_pins {U3/D}]” defines a false path starting from flip-flop U2 through gates G1 and G2 to flip-flop U3. Example 2.2: Consider Figure 2. The SDC command “set_case_analysis 1 [get_pins {G3/select}]” is used to assign logic value 1 at the select line of the multiplexer G3. STA considers only the G3/data1 to G3/out path for timing analysis. Paths G3/data0 to G3/out and G3/select to G3/out are treated as false paths, and they are ignored for timing analysis. set_case_analysis 1 [get_pins {G3/select}] G1
G2 data1
At-speed Scan Pattern Generation Flow
The timing exceptions are used to override the default single-cycle clock timing and constraints. Since the designers know the functional design, they specify these timing exceptions for the appropriate timing paths. The timing exceptions and constraints are specified in SDC files. The following SDC commands can be used to specify timing exceptions and constraints. set_false_path, set_multicycle_path, set_disable_timing, set_case_analysis, create_clock, create_generated_clock and set_hierarchy_separator. The SDC command set_false_path specifies a false path, and the SDC command set_multicycle_path specifies a multicycle path. set_disable_timing command is used to disable the analysis of timing arcs in STA. set_case_analysis command is used to specify a boolean state, and STA tools use these states while performing timing analysis. The SDC commands create_clock and create_generated_clock can be used to define clocks in a design. The command set_hierarchy_separator defines the instance hierarchy boundary in a pin path name or a net name or an instance path name. The following examples show the usage of two SDC commands.
data0
G3
0
out
G4
1
select
Figure 2: Case Analysis The new flow is shown in Figure 3. The designers provide one or more SDC files to the static timing analyzer. STA tool reads in user defined SDC file(s), and performs timing analysis. STA tool then generates one or more SDC file(s) as shown in Figure 3. These are the same SDC files that are used for the final place and route. The transform_exceptions command within PrimeTime, a commercially available STA tool is used before saving the SDC file(s) to clean up the content of these constraint file(s). This command removes any redundant, invalid and overridden path exceptions. This command in PrimeTime also removes any timing exceptions within atspeed clock networks in a design.
Static Timing Analysis
User SDC file
transform_exceptions
Example 2.1: set_false_path –from [get_pins {U2/CK}] -through [get_cells{G1}] –to [get_pins {U3/D}] U1 Clk1
D
G1
G2
Q
U3 D
write_sdc
SDC file Q
Physical Design tools
CK CK Clk1
U2 D
ATPG/EDT Tool
Q
CK
Figure 3: At-speed Test Generation Flow Figure 1: False Path
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Then the write_sdc command in PrimeTime is used to save the updated information. For at-speed test pattern generation, this clean and updated SDC file is used. The test generation tool directly reads in the SDC file(s) before generating test patterns. During at-speed test pattern generation, the effects of the timing exceptions and constraints are considered. The advantage of using this flow is that the path information of the timing exception paths is preserved, and no cell constraints are to be generated. By directly reading in SDC the problem of over-masking is avoided during test pattern generation. ATPG/EDT tool uses patent-pending [1] dynamic masking capability. The dynamic masking per pattern based on path sensitization not only increases test coverage, but also reduces the number of unknowns in the test responses. Reducing unknowns greatly improves the ability to achieve superior test compression results. In this flow ATPG/EDT tool does not use any circuit timing information specified in SDF (standard delay format) file(s). The timing information is generated from parasitic (RLC) values of a circuit, and there are inherent inaccuracies in parasitic extraction. Hence SDF data may not be reliable. During at-speed pattern generation, analysis is done in a timing-independent way. Any unreliability in SDF data is completely avoided. The process is robust, and generated at-speed patterns are correct-by-construction. SDC file(s) can be generated at the module level. In this flow, the ATPG/EDT tool can read in module level SDC file(s) at full-chip with the correct context. This capability is very useful in SoC design flows.
3. Path-oriented Method This section describes algorithmic details about how timing exceptions and constraints are handled during generation of traditional scan or EDT [11] at-speed test patterns. The methods presented here can be applied to any fault model for generating at-speed test patterns. The core algorithm consists of two main procedures. The first one is a static analysis that is executed only once prior to at-speed pattern generation. The second one is a dynamic analysis that gets executed for each generated pattern or a set of patterns.
3.1
Static Analysis
The timing exceptions and constraints are read into the ATPG tool from one or more SDC files, and the timing exception paths are derived. The timing exception paths include false paths, multicycle paths and conditional false paths. The false paths and multicycle paths are identified from the SDC commands set_disable_timing, set_false_path, set_multicycle_path, create_clock and create_generated_clock. In the case of SDC command set_case_analysis, Procedure I is applied to derive the relevant false paths and conditional false paths.
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Step 1.
Assign logic states defined by set_case_analysis and propagate the assigned logic values by implication.
Step 2.
Check if a circuit element with conflicting logic values exists.
Step 3.
If there are conflicts, report them and stop.
Step 4.
Add false paths through the circuit locations at which the original Boolean constraints were specified.
Step 5.
Find the combinational gates with 1) output logic state yet to be specified and 2) at least one input with a specified logic state of either 0 or 1.
Step 6.
For each combinational gate found in step 5, add a conditional false path through the gate along with the Boolean condition defined by its specified fanin logic values.
Step 7.
Find the sequential gates with at least one input with a specified logic state of either 0 or 1.
Step 8.
For each sequential gate found in step 7, add a conditional false path through each data input along with the Boolean condition defined by its specified fanin logic values.
Procedure I: Deriving Conditional False Paths A driver cell of a timing exception path is a sequential element that drives the start points either through a simple net or through a set of combinational gates. When a start point of a timing exception path is a sequential element, then the driver cell of the timing exception path is the start point itself. Otherwise, the combinational input cone of logic from the start points is traced backward to find out all of the driver cells. The driver cells of all the timing exception paths are determined. This step is needed in order to check path sensitization due to glitches. The timing exception paths are then statically analyzed to identify the interacting timing exception paths. The partitions are formed based on this static analysis. This step is necessary in order to reduce the pessimism in simulation of timing exception paths. During per pattern analysis, paths in a given partition are analyzed together to determine their impact on the test responses. The final test responses are computed by accumulating the effects from each partition. The timing paths are then annotated into the netlist which involves identifying the circuit elements associated with the timing exception paths for each partition. This is
referred to as the Timing Exception Path Cone, and this information will be used during at-speed pattern generation. This is implemented by static forward and backward traversal of the netlist. The following Procedure II summarizes the steps involved in static analysis. Step 1.
Read SDC file(s).
Step 2.
Extract timing exception paths: false paths, multicycle paths, and conditional false paths.
Step 3.
Determine the driver cell(s) of the timing exception paths.
Step 4. Step 5.
X are recorded, and the original state of the circuit is restored. Once sensitization checks are performed for all the partitions, Xs are injected at the affected end points that were recorded during sensitization checks. The effects of these Xs are then propagated forward, and the correct atspeed test responses are computed. At-speed test patterns are sequential in nature and they have multiple time frames. The above procedure is applied to each time frame in a given test pattern. The following Procedure III summarizes the steps involved in dynamic per pattern analysis. Step 1.
Perform static partitioning of timing exception paths for accurate simulation. For each partition identify exception path cones.
the
For each partition perform steps from 1.1 to 1.5. step 1.1. For each timing exception path in the current partition, check if X needs to be injected at a driver cell.
timing
step 1.2. If needed inject X at the driver cell. Procedure II: Static Analysis
3.2
step 1.3. Propagate the effects of injected Xs through the timing exception path cones.
Dynamic per Pattern Analysis
Once the static analysis is completed, at-speed pattern generation starts. The dynamic analysis is done for each generated pattern. During the at-speed pattern generation, the sensitizations of timing exception paths are checked. The path sensitization can be due to a transition (rise or fall) or a glitch, or both. The following procedure is used for checking the sensitization of timing exception paths for a given partition. If a timing exception path is a conditional false path, the associated boolean condition is examined. Only if the associated boolean condition is violated, the conditional false path is considered for path sensitization check. For other timing exception paths, path sensitization check is always carried out. The logic values at the driver cells of a timing exception path are examined. If an at-speed transition is found at a driver cell, the original logic value is stored and the logic value X (representing unknown logic value) is injected. Since the delay along a timing exception path may not be known, the logic value X is also injected at a driver cell if there was a past at-speed transition at that point in the given pattern. A slow operation like scan load/unload resets this accumulation of at-speed transitions at the driver cells. If a timing exception path has a hold time violation problem, X is injected at a driver cell if the new captured state creates a transition. The effects of the injected Xs are then propagated forward through the gates defining a complete timing exception path. If logic value X is found at a subset of the end points, the timing exception path is sensitized. If none of the end points have logic value X, the timing exception path is not sensitized. For the sensitized paths, the affected end points with logic value
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step 1.4. Record the affected end points where Xs have been propagated. step 1.5. Restore the original circuit state. Step 2.
Inject Xs at the affected end points recorded in step 1.4, and simulate the resulting Xs forward.
Procedure III: Dynamic per Pattern Analysis
4. STARC Example Circuits At STARC, 22 test cases were created. The pathoriented method as described in section 3 is used to generate at-speed scan patterns in the presence of timing exceptions and constraints on these circuits. These experiments are performed to verify the correctness and efficiency of the method presented in section 3. In this section, 5 example circuits are presented to illustrate how the proposed method generates correct-by-construction atspeed patterns on these circuits without pessimism. Example 4.1: Consider the circuit shown in Figure 4. The SDC command “set_false_path –from [get_clocks {Clk1}] –to [get_pins {U3/D}]” defines false paths starting from flipflops U1 and U2 through gates G1 and G2 to flip-flop U3. Suppose there is a rising (0−>1) transition at U2, and there is a falling (1−>0) transition at U1. The path from U2 through G2 to U3 is sensitized due to pure transition. The paths from U1 and U2 first through G1 and then through
G2 to U3 are sensitized due to glitches. The method presented in section 3, is applied. Flip-flop U3 is masked out, and flip-flip U4 correctly sees a falling (1−>0) transition. set_false_path –from [get_clocks {Clk1}] –to [get_pins {U3/D}] U1 Clk1
D
1−>0
G1
G2
sensitized and U3/D will remain at logic state 0. If the false paths were simulated together, both flip-flops U3 and U4 would have been masked. P1: set_false_path –from U1/Q -to U4/D P2: set_false_path –from U2/Q -to U3/D U1
1−>X U3
Q
D
Clk1 Q
D
G1
1−>0
D
CK
CK
Clk1
D
G3
0−>1
D
Q
D
Q
G3 0−>X U4
0−>1
Q
D
Q
CK
Clk1
CK
CK
Clk1
CK
U2
1−>0 U4
Q
CK
Clk1
CK U2
0−>0 U3
G2
Q
Figure 6: Example 4.3 Figure 4: Example 4.1 Example 4.2: Consider the circuit shown in Figure 5. There is a false path “set_false_path –from [get_pins {U1/CK}] –to [get_pins {U3/D}]”. The false path starts from flip-flop U1, then goes through gates G1 and G2, and ends at flipflop U3. Flip-flop U1 has falling (1−>0) transition, and flip-flop U2 has a rising (0−>1) transition. In this case the false path is sensitized due to glitches produced at gate G1. The method described in section 3 can analyze glitches in a timing-independent way. It finds the false path to be sensitized. Flip-flop U3 is correctly masked out, and flip-flip U4 sees a falling (1−>0) transition.
Example 4.4: Consider a false path from flip-flop U1 to flip-flop U3 as shown in Figure 7A. Flip-flop U1 has falling (1−>0) transition, and flip-flop U2 has a rising (0−>1) transition. Clearly this timing exception path from flip-flop U1 through gate G1 to flip-flop U3 is sensitized. X is injected at the D pin of flip-flop U3. As a result only flip-flop U3 is masked out. Flip-flop U4 captures logic value 0. set_false_path –from [get_pins {U1/Q}] –to [get pins {U3/D}] U1 D
Clk1
Clk1
D
1−>0
G1
D
CK
Clk1
U2 D
0−>1
D Clk1
U4 Q
D
Q
CK
Clk1
Figure 7A: Example 4.4 Q
CK
Figure 5: Example 4.2 Example 4.3: Consider the circuit shown in Figure 6. There are two false paths: 1) P1 from flip-flop U1 to U4 and 2) P2 from U2 to U3. From U1 to U3 there is a true functional path and from U2 to U4 there is a true functional path. Clearly P1 and P2 have distinct end points and they are not driving any common end points through any combinational paths. Hence they are simulated separately. The generated atspeed test pattern has a falling (1−>0) transition at U1/Q and a rising (0−>1) transition at U2/Q. Clearly the false path P1 is sensitized due to the transition at U1/Q and a potential glitch through gate G1. Hence at U4/D there will be a transition (0−>X) and the flip-flop U4 will be masked for this pattern. However the false path P2 is not
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Q
CK
0−>0
0−>1
CK
CK
G3 1−>0 U4
Q
CK
D
D
Clk1
U2
Q
U3
0−>X
Q
G2 1−>X U3
Q
G1
CK
set_false_path –from [get_clocks {U1/CK}] –to [get_pins {U3/D}] U1
1−>0
In Figure 7B, flip-flop U1 has rising (0−>1) transition, and flip-flop U2 has a falling (1−>0) transition. Clearly this timing exception path from flip-flop U1 through gate G1 to flip-flop U3 is not sensitized as flip-flop U2 is controlling gate G1. Hence flip-flop U3 and flip-flop U4 capture logic value 0. set_false_path –from [get_pins {U1/Q}] –to [get pins {U3/D}] U1 Clk1
D
0−>1
Q
CK
U3
0−>0
1−>0
Q
U4
0−>0 D
Q
CK
D
CK
Clk1
U2 D
G1
Clk1
Figure 7B: Example 4.4
CK
Q
0−>1 1−>0
G1
data0
G2 data1
0
out
U1
G4 1−>X
D Q
1
CK
1−>0 select
Figure 8: Example 4.5
5. Results In this section, results on five industrial designs are presented. All five designs have AC scan mode support for transition delay scan patterns. They all have phase lock loop (PLL) based internally generated AC scan clocks and the clock waveforms are configurable through a JTAG interface. Table 1 shows the detailed characteristics of these designs.
MAXIMUM CLOCK SPEED
GATES
SCAN CHAINS
SCAN CELLS
C1
7
162MHz
3.7M
512
160K
C2
7
108MHz
3.5M
1004
128K
C3
96
96MHz
3.8M
128
160K
C4
52
528MHz
2.8M
95
162K
C5
15
372MHz
1.5M
128
120K
TESTCASES
CLOCK DOMAINS
Table 1 : Testcase Characteristics
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FALSE PATHS
MULTICYCLE PATHS
CASE ANALYSIS
G3
Table 2 : SDC Characteristics
SDC FILES
set_case_analysis 1 [get_pins {G3/select}]
For each of these five designs we used the SDC files generated for the place and route tool by the static timing analyzer. Table 2 shows the details of the SDC files generated for the five testcases. From these SDC files the cell constraints are also generated for the timing exception paths. It was a tedious time consuming process involving manual steps and scripting.
C1
1
1210
29
6
C2
1
1795
0
9
C3
2
1254
76
0
C4
1
78
0
0
C5
1
353
0
0
TESTCASES
Example 4.5: Consider the circuit shown in Figure 8. The timing constraint for this circuit consists of the SDC command “set_case_analysis 1 [get_pins {G3/select}]”. Here STA will use the logic state 1 of G3/select line for computing delay. If for some reason this condition is violated in an at-speed scan pattern, it can potentially lead to incorrect test responses. In order to handle this situation effectively, a conditional false path through multiplexer G3 along with logic condition 1 at G3/select is added. If G3/select is not at logic state 1 the effect of false path through multiplexer G3 will be considered. In addition to the conditional false path, a false path through the G3/select pin is also needed, as an at-speed transition through this pin cannot be propagated reliably. Suppose G1 has a rising (0−>1) transition, G2 has a falling (1−>0) transition, and pin G3/select has a falling (1−>0) transition. In this case the conditional false path through G3 along with logic condition 1 is sensitized. The false path through the G3/select pin is also sensitized. Flip-flop U1 is masked out.
The at-speed test patterns are generated in three distinct ways. In the first flow called baseline flow, test patterns are generated without reading in SDC information and cell constraints information. Clearly if these patterns are used on ATE as generated for at-speed testing there will be a lot of mismatches. Hence these patterns are unusable for screening any real small delay defects in absence of any instrumentation. In the second flow called static masking flow, the cell constraints are read in, and at-speed test patterns are generated using this information. These patterns can be used on ATE as generated to screen small delay defects. In the third flow called SDC flow, the tool directly reads in one or multiple SDC files and creates at-speed test patterns using timing exceptions and constraints specified in the SDC files. In this flow, the tool uses the method described in this paper to create patterns. An ATE can use these patterns to screen small delay defects. Table 3 shows the at-speed test generation statistics using the three flows described in the above paragraph. Clearly the SDC flow using the new proposed method produces at-speed test patterns with test coverage 1.06% to 16.59% better than the static masking flow using the old cell constraints method. The average number of unknowns per pattern in the SDC flow is 3 to 50 times lower than that in the static masking flow. The proposed method of generating at-speed patterns in the presence of timing exceptions and constraints by directly reading in SDC files improves the quality of test. On average the proposed method takes about 20% more run-time compared to the baseline run. The direct SDC handling capability in the proposed method makes it very easy to use at-speed test generation flow.
[2]
V. Vorisek, B. Swanson, K.-H. Tsai, D. Goswami, “Improved Handling of False and Multicycle Paths in ATPG”, Proc. IEEE VLSI Test Symposium, 2006, pp. 160-165.
[3]
B. R. Benware, R. Madge, C. Lu, and R. Daasch, “Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs”, Proc. IEEE VLSI Test Symposium, 2003, pp. 39-46.
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W. Needham, C. Prunty, E. H. Yeoh, “High Volume Microprocessor Test Escapes, an Analysis of Defects our Tests are Missing”, Proc. International Test Conference, 1998, pp. 25-34.
[5]
K. S. Kim, S. Mitra, P. G. Ryan “Delay Defect Characteristics and Testing Strategies”, IEEE Design & Test of Computers, Sept.-Oct. 2003, pp. 8-16.
[6]
X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, N. Tamarapalli, “High-frequency, At-speed Scan Testing”, IEEE Design & Test of Computers, Sept.Oct. 2003, pp. 17-25.
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M. Beck, O. Barondeau, F. Poehl, X. Lin, R. Press, “Measures to Improve Delay Fault Testing on Low-Cost Testers – A Case Study”, Proc. IEEE VLSI Test Symposium, 2005, pp. 223-228.
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N. Tendolkar, R. Raina, R. Woltenberg, X. Lin, B. Swanson, G. Aldrich, “Novel techniques for achieving high at-speed transition fault test coverage for Motorola’s microprocessors based on PowerPC instruction set architecture”, Proc. IEEE VLSI Test Symposium, 2002, pp. 3-8.
[9]
B. Cory, R. Kapur, B. Underwood, “Speed Binning with Path Delay Test in 150-nm Technology”, IEEE Design & Test of Computers, Sept.-Oct. 2003, pp. 41-45.
[10]
J. Saxena, K. Butler, J. Gatt, R. Raghuraman, S. Kumar, S. Basu, D. Campbell, J. Berech, “Scan-Based Transition Fault Testing – Implementation and Low Cost Test Challenges”, Proc. International Test Conference, 2002, pp. 1120-1129.
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J. Rajski, J, Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.-H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, and J. Qian, “Embedded Deterministic Test for Low-Cost Manufacturing Test,” Proc. International Test Conference, 2002, pp. 301-310.
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The authors would like to thank Atsuo Takatori of STARC, and Xijiang Lin of Mentor Graphics Corporation DFT for their contributions to this work.
[13]
V. Chickermane, B. Foutz, and B. Keller, “Channel Masking Synthesis for Efficient On-Chip Test Compression”, Proc. International Test Conference, 2004, pp. 452-461.
References:
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N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, and T. W. Williams, “Changing the Scan Enable During Shift,” Proc. IEEE VLSI Test Symposium, 2004, pp.73-78.
Table 3 : Test Generation Statistics
STATIC MASKING
SDC
BASELINE
STATIC MASKING
SDC
BASELINE
STATIC MASKING
SDC
UNKNOWNS/PATTERN
BASELINE
#PATTERN (K)
TESTCASES
TEST COVERAGE (%)
C1
82.28
77.40
78.46
16.0
20.5
20.4
100
26531
5848
C2
97.56
92.89
95.83
8.4
13.5
12.3
118
1602
367
C3
79.21
61.38
77.97
15.7
17.1
16.9
205
51302
929
C4
81.03
73.33
78.46
30.0
30.0
30.0
800
4900
1500
C5
84.05
76.26
80.28
13.9
12.3
12.4
29
405
94
6. Conclusions In order to meet high product quality goals, scanbased at-speed testing has become necessary for nanometer designs. Scan-based at-speed testing can only be successful if reliable (no false failures) test patterns are generated. Today’s designs have many timing exceptions and constraints, and it is extremely important to generate at-speed scan pattern in the presence of timing exceptions and constraints. Considering timing exceptions and constraints significantly cuts down the pattern debugging time on the ATE by eliminating mismatches covered by timing exceptions. It also eradicates any concern for yield loss. A path-oriented method for generating reliable atspeed test patterns in the presence of timing exceptions and constraints was presented in [1][2]. This method has been applied to many industrial circuits. Results show that the path-oriented approach is far superior to the traditional cell constraint-based static masking methodology in terms of 1) ease of use, 2) test coverage and 3) test compression. This method has been extensively studied at STARC. Several test circuits were created. Experiments were performed on these circuits to verify the correctness and efficiency of this method. The extensive verification process concludes that this path-oriented method generates correct-by-construction at-speed patterns without any pessimism
Acknowledgements:
[1]
D. Goswami, K.-H. Tsai, M. Kassab, J. Rajski, “Generating Responses to Patterns Stimulating an Electronic Circuit with Timing Exception Paths”, US Patent Application.
15th Asian Test Symposium (ATS'06) 0-7695-2628-4/06 $20.00 © 2006
