JOURNAL OF APPLIED PHYSICS 114, 234503 (2013)
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory Y. Li,1,2 Y. P. Zhong,1,2 Y. F. Deng,1,2 Y. X. Zhou,1,2 L. Xu,1,2 and X. S. Miao1,2,a) 1
Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074, China 2 School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China
(Received 22 November 2013; accepted 6 December 2013; published online 19 December 2013) Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel C 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4852995] memory devices. V I. INTRODUCTION
Electronic devices or circuits that can store and process data information are considered as building blocks for new computing architectures to break the Von Neumann bottleneck.1,2 Phase-change memory (PCM), a promising candidate for the next-generation nonvolatile memory to replace Flash or be used as storage class memory,3–5 recently has shown its surprising capability of information processing through neuromorphic and logic approaches.6–11 In the neuromorphic paradigm of computing, the PCM is used as electronic synapses. The analog properties of device resistance tuning due to partial crystallization6,7 or charge-trapping8 controlled memristance are utilized to emulate the plastic modification of synaptic efficacy. This paradigm may aim at developing brain-inspired chips in a long term scope. In the case of logic paradigm, Ovshinsky et al. proposed12–14 and Wright et al. exploited9,10 the energy accumulation effects of amorphous phase-change materials and built phase-change accumulators on which arithmetic computations such as addition, subtraction, and factoring are performed. Cassinerio et al. demonstrated Boolean logic computation in a single PCM device by manipulating the threshold and memory switching behaviors.11 However, the above mentioned logic implementations still have some shortcomings that need to be addressed. First, the operation reliability or repeatability is still far from application, because the energy accumulation and threshold switching behavior is vulnerable to disturbance of device variation and random nucleation and growth process during crystallization. Second, they are all sequential operation because of the simple two-terminal feature of PCM. Compared to parallel computing, multiple steps with longer operation time are needed to complete a logic function although occupied device area is significant reduced,10,11 limiting the application in some ultrafast computing occasions. a)
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Here, we present novel nonvolatile AND, OR, and NOT logic circuits consisting of PCM devices, resistors, and switches. The logic operation utilized the reversible binary switching between amorphous and crystalline states of PCM, and the simple control of the phase transition enables reliable logic operations. These three simple circuits allows AND, OR, and NOT three basic logic functions implemented in one step. Moreover, the logic computing results can be directly stored in the nonvolatile states of the circuits. Validity of the circuit setups and operation principles are verified by SPICE simulation and experimental results. II. EXPERIMENT
T-shaped PCM devices (TiW 100 nm/Ge2Sb2Te5 150 nm/TiW 100 nm) were fabricated on SiO2/Si substrates. The 1 1 lm2 contact area was patterned using ultra-violet lithography and the films were deposited by DC sputtering. More details of the PCM fabrication process can be found in our earlier work.8,15 The PCM devices were wire-bonded to a ceramic package and connected on a self-designed PCB testing board to ensure good contact for electrical measurements. The current-voltage (I-V) characteristics, pulsed switching behaviors, and logic operations were measured with a semiconductor characterization system (Keithley 4200-SCS). The waveforms were obtained with an oscilloscope (Agilent DSO5012A). All measurements were carried out at room temperature in air. A compact SPICE model for PCM of Ref. 16 was adopted in our simulations with characteristic low-resistance of 10 kX and high-resistance of 200 kX. III. RESULTS AND DISCUSSION
In our experiment, the switch of PCM acts as the basis of implementing the three basic Boolean logic functions. Figure 1(a) shows measured I-V characteristics of a PCM. The pristine high-resistive device switched to a lowresistance state at a threshold of 1.26 V, where Ge2Sb2Te5 material went through a phase transition from amorphous to
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crystalline state. Figure 1(b) shows the repeated switching property of a PCM device by alternating voltage pulses. The device was set to low-resistance (ON, RON ¼ 8.47 kX) state by using a 200 ns-0.8 V SET pulse, and reset to highresistance (OFF, ROFF ¼ 224 kX) state by using a 30 ns-2 V RESET pulse. The device shows a dynamic switching resistance ratio over 25, which is enough to distinguish logic 1 and logic 0 during the logic operations. The energy inputs for set and reset operations are 0.57 pJ and 14.17 pJ, respectively. In our operation approach, an input of RESET pulse is assigned a logic value of 0, and an input of SET pulse is assigned a logic value of 1. The AND gate circuit is shown in Fig. 2(a). Two PCM devices, M1 and M2, and a load resistor, R, are connected in series to the ground. The node between M1 and M2 is connected to the ground through a switch S. For input terminal A and B, RESET pulse and SET pulse are assigned logical
input 0 and 1, respectively. To perform an AND operation, close the switch S and input the pulses at terminals A and B. The states of M1 and M2 are determined by input A and B, respectively, regardless of their initial states. M1 will be OFF state when applying RESET pulse at terminal A and be ON state when applying SET pulse at terminal A, and so does M2. The AND logic operation is implemented simultaneously as the inputs are applied to terminals A and B. To read the result of the operation, open the switch so the M1, M2, and R are connected in series, and apply a small reading voltage pulse (0.2 V with 10 ms pulse width) at terminal A and readout at terminal OUTPUT. The selection of R is important to the outcome of the operation. The resistance is chosen such that R approximately equals RON, where RON and ROFF are the resistance of ON state and OFF state of PCM. Here, R is 10 kX. If either M1 or M2 is OFF state, VA drops mainly across PCMs because R < ROFF, so Voutput is low and represents logical output 0. However, when both M1 and M2 are ON states, Voutput is relatively high since R ¼ RON and represents logical output 1. Figure 2(c) shows an experiment demonstration of the complete AND operations. Only two SET pulses representing logic input 1 lead to high voltage output representing logic output 1. The simulative Voutput for logic output 0 and logic output 1 are approximately 3 mV and 66 mV, respectively, whereas small variations exist in experimental realization. By comparing the conditional operation results of Fig. 2(c) to the truth table of Fig. 2(b), we see that we successfully executed AND logic function. OR logic gate could be realized based on two parallel connected PCM devices in series with a 10-kX load resistor R and a switch S, as shown in Fig. 3(a). To perform an OR operation, close the switch S and program M1 and M2 in the same way of AND gate. To read the result of the operation, open the switch so the M1 and M2 are connected in parallel, and apply a reading voltage pulse at both terminals A and B and readout at terminal OUTPUT. If both M1 and M2 are OFF state, VA drops mainly across PCMs because R < ROFF, so Voutput is low and represents logical output 0. Obviously,
FIG. 2. Illustration of the AND operation based on PCM. (a) The AND gate circuit setup includes two PCM devices, a switch and a load resistor. (b) The truth table for the AND operation. (c) Experimental realization and SPICE simulation of the AND gate.
FIG. 3. Illustration of the OR operation based on PCM. (a) The OR gate circuit setup includes two PCM devices, a switch and a load resistor. (b) The truth table for the OR operation. (c) Experimental realization and SPICE simulation of the OR gate.
FIG. 1. Electrical switching characteristics of PCM device. (a) I-V characteristics of PCM device with a phase transition threshold voltage of 1.26 V. (b) Reversible switching between ON and OFF states by applying SET and RESET pulses.
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when either M1 or M2 is ON state, Voutput is relatively high since R ¼ RON and represents logical output 1. Figure 3(c) shows the simulated and measured voltage waves that prove the OR operation. The NOT gate design is shown in Fig. 4(a), in which a PCM device M is utilized in cooperation with a load resistor R. Note that here the resistance of the load resistor is 140 kX, comparable to the high resistance state of PCM. The logic operation is performed only in one step: input SET or RESET pulse at terminal A. Then the operation result can be readout by a read voltage pulse applied at terminal INPUT. Specifically, when logic input 1 (SET pulse) is inputted, the PCM is operated to RON, and the voltage drops mainly across the load resistor when the read pulse is applied, thus output a low voltage (13.3 mV in simulation and 36.5 mV in experiment). On the contrary, the PCM is operated to ROFF due to logic input 0 (RESET pulse), so we can obtain a relative high voltage (156 mV in simulation and 133 mV in experiment) at the OUTPUT which represent the logic output 1. Figures 4(b) and 4(c) show the logic function table and operations for the NOT gate. In our above approaches, each PCM device first acts as a switch. The switch can easily represent two states: on and off, which are also the physical basis in transistor-based logic gate designs. Second, the PCM devices serve as memories to store the logic output in the gate circuit, enabling “stateful” logic operations with a nonvolatile nature.17 Moreover, by combining the AND, OR, and NOT logic gates together we can construct more complex logic functions, such as NAND, NOR, and XOR. In other words, a functional logic completeness of any possible truth tables can be reproduced in networks of PCM based logic gates. Although the PCM based logic gates cannot outperform the CMOS logic gates at this stage, there are ways to improve PCM device performance, bringing the logic gates closer to real applications. The PCM devices consume zero
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standby power and low dynamic power with high computing speed. Switching time and power consumption could be further reduced by means of material modification, device structure and programming schemes optimization. Recent advances make it possible to achieve ultrafast and stable switching with 500-ps pulses for both set and reset processes by applying an incubation electrical field.18 And ultralow switching power was obtained in a Sn10Te90/Sb2Te3 diluted superlattice device. The power is approximately 1/2550 that of a GST device.19 Note that additional power consumption should take into account due to the introduction of switches in the logic gates. The switches could be transistors, diodes, PCMs, or other latches. Comparing to sequential computing in a single PCM device,11 more devices are needed to build up the logic gates in this work. However, only one programming step is needed to implement the three basic logic functions and two stable resistive states are utilized, leading to faster and more reliable logic operations in our gates. We believe that a complementation of these two different approaches of PCM based logic gate construction is necessary to reach an optimum trade-off between speed and chip area in future PCM based logic chip designs. IV. CONCLUSIONS
In summary, we proposed PCM-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations. The logic functions are demonstrated in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. The realization of nonvolatile logic gate may promote future nonvolatile central processing unit (CPU) design with fast computing speed and ultralow power consumption. ACKNOWLEDGMENTS
The work was financially supported by the National Natural Science Foundation of China (61376130), the International Science & Technology Cooperation Program of China (2010DFA11050), the National High-tech R&D Program (863 Program) of China (2011AA010404), and the Fundamental Research Funds for the Central Universities (HUST: 0118182046). 1
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FIG. 4. Illustration of the NOT operation based on PCM. (a) The NOT gate circuit setup includes one PCM device and a load resistor. (b) The truth table for the NOT operation. (c) Experimental realization and SPICE simulation of the NOT gate.
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