Boolean Logic Operations and Computing Circuits Based on Memristors

This article has been accepted for publication in IEEE Trans. Circuits Syst. II, Expr. Briefs journal, but has not been fully edited. Content may change prior to final publication. DOI: 10.1109/TCSII.2014.2357351

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Boolean Logic Operations and Computing Circuits Based on Memristors Georgios Papandroulidakis, Ioannis Vourkas, Student Member, IEEE, Nikolaos Vasileiadis, and Georgios Ch. Sirakoulis, Member, IEEE

Abstract—This brief contributes to the design of computational and reconfigurable structures which exploit the unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation based validation of the proposed circuits and systems is provided. Index Terms— memristor, memristive systems, programmable analog circuits, Boolean logic, memristive computing

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I. INTRODUCTION

t was not until 2008 when Chua’s theory of the fourth fundamental circuit component, which he called memristor (concatenation of “memory resistor”), was successfully linked to its first modern practical implementation by HP Laboratories [1]. Memristor (here used to describe both an ideal memristor as well as a generalized memristive system [2]) is a two-terminal passive nonvolatile resistance switching device, quite promising to advance the electronic circuits and systems state-of-the art thanks to its many favorable properties [3]. Most experimentally realizable memristors demonstrate threshold-type response; they comply with a set of usually asymmetric voltage thresholds for SET and RESET operations meaning that there is negligible change induced to their memory resistance (memristance) if the magnitude of the applied voltage remains below these thresholds [4]. Memristor opens new pathways for the exploration of advanced circuit architectures where computing and storing is performed on the same devices [5]. Related work on logic circuit design with memristors has so far focused on stateful logic [6-7]. However, its major disadvantage is the necessity to perform lengthy sequences of imply/false operations in order to synthesize a given Boolean function. Moreover, programmable resistors are nowadays required for various circuit applications in order to facilitate adaptation to Manuscript received April 30, 2014. This work was supported in part by a scholarship from the BODOSSAKI Foundation in Greece. G. Papandroulidakis, I. Vourkas, N. Vasileiadis, and G. Ch. Sirakoulis are with the Department of Electrical & Computer Engineering, Democritus University of Thrace (DUTh), Xanthi, Greece (Tel: +30-25410-79916; Fax: +30-25410-79540; e-mails: [email protected], [email protected], [email protected], [email protected]).

particular conditions. Memristors could be arbitrarily programmed to theoretically all intermediate conducting states. However, a given memristance precision requires biasing with very precise amplitude and duration, thus is strongly dependent on device variations [8]. This brief addresses novel computational methods and structures which exploit the threshold-dependent resistance switching behavior of memristors and their compositions. The presented applications include Boolean logic operations and programmable memristive switches. The fundamental dynamics of all primitive memristive structures are described. Then a novel memristive logic family which uses the total conductance of memristive ensembles for several Boolean operations is proposed. Moreover, a methodology for the construction of robust fine-resolution programmable memristive switches is presented. This new methodology makes unnecessary the need for high precision tuning of single devices. Finally, the proposed memristive switches are used in a memristive closed loop analog computing circuit able to generate scalable output voltage levels in a step-wise manner. II. SWITCHING DYNAMICS OF MEMRISTORS AND MEMRISTIVE CIRCUIT COMPOSITIONS Fig. 1 presents the qualitative current-voltage (I-V) characteristics of memristors with opposite polarities and their serial/parallel combination under AC applied voltage. We consider a memristor to be forward/reversely polarized (FPM/RPM) when the voltage is applied to the top/bottom terminal with the bottom/top terminal being grounded; bottom terminal is denoted by the black thick line. For the employed devices we assume asymmetric thresholds and the following initial states: {RPM, FPM} = {ON, OFF}. Memristors with opposite polarities generally demonstrate reversed behavior to the applied signals. According to Fig. 1a, when a positive voltage applied to a FPM reaches its “set threshold” (VS,1), the device switches to its low resistive state (ON state). Then, an ohmic behavior is observed until a “reset threshold” (VR,1) is reached and the device returns to the high resistive state (OFF state). The I-V graph of a RPM shown in Fig. 1b is symmetric to that of a FPM and has the opposite voltage thresholds. Fig. 1c illustrates the composite I-V response of two reciprocal memristors connected in parallel. When a positive applied voltage reaches the “reset threshold” of the RPM (VR,2) its state is changed and the total current drops. Next, when the voltage exceeds the “set threshold” (VS,1) of the FPM

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Fig. 1 Qualitative current-voltage (I-V) characteristics of individual memristors with opposite polarities and their serial/parallel combination.

it switches to the ON state and total current rises again. Afterwards the composite device exhibits an ohmic behavior unless a negative voltage is applied. This behavior is opposite to that of the anti-serially connected memristors presented in Fig. 1d. However, here the voltage thresholds (denoted as Vth,1 - Vth,4) cannot be formerly known exactly because the connected devices here form a voltage divider; the voltage drop over each element depends on the total applied voltage, on the internal states of the devices, and on their particular switching characteristics. In both connection types, a negative applied voltage will in turn reset the memristors to the given initial states. An outstanding feature that appears for both the series and the parallel connection of reciprocal memristors is the perfectly symmetric I-V curve which resembles a truncated Ohm’s law; current is piece-wise linear with the voltage. However, if the devices are all placed with the same polarity, their overall behavior resembles that of a memristor of the same polarity but with complex switching properties [9]. III. THRESHOLD-BASED SWITCHING BEHAVIOR ENABLES BOOLEAN LOGIC OPERATIONS In this section we present a memristive logic family which uses the total memory conductance (memductance) of the employed devices for the computation of Boolean AND, OR, NAND, NOR, XOR, and XNOR operations. Fig. 2 summarizes the general concept for the construction of twoinput memristive logic gates. According to Fig. 2d the aggregate input voltage is applied to a memristive ensemble which can be any of the six provided options, each implementing a particular logic operation. All necessary input combinations of the aggregated input signals could be generated by either using appropriate switches or via a summing amplifier. The qualitative I-V graphs of Fig. 2a-c show why memductance is inherently suitable to be the state variable for Boolean logic operations. In all cases the input voltages consist in 0V for logic ‘0’, whereas logic ‘1’ corresponds to a voltage value which must lie between the first (lower) and the second (higher) of the defined thresholds.

Fig. 2 General concept for the construction of 2-input memristive logic gates. (a-c) Qualitative I-V characteristics corresponding to FPMs or RPMs and their series/parallel combination. (d) Circuit implementing any of the six provided logic operations with two variables.

As shown in Fig. 2a, a FPM will switch from a low conductance (L) to a high conductance (H) if any of the applied inputs is logic ‘1’ (or both), i.e. it exceeds VS,1. Likewise, when employing two FPMs in series, the composite memductance will rise from a low value (L’) to a high value (H’) only when both inputs are logic ‘1’ so that the aggregate input voltage exceeds the cumulative threshold 2×VS,1. Therefore, memductance in these two cases is defined by the following equations which describe OR and AND logic operations as functions of the aggregate applied voltage:  H , VIN ,SUM > VS ,1 OR : G (VIN ,SUM = VIN ,1 + VIN , 2 ) =   L , otherwise

(1)

 H ' , VIN ,SUM > 2 × VS ,1 (2) AND : G (VIN ,SUM = VIN ,1 + VIN , 2 ) =  otherwise  L' ,

When employing a RPM or two RPMs in series, as shown in Fig. 2b, under similar working principles the circuit implements a NOR and a NAND logic gate, respectively. Unlike in Fig. 2a, it is threshold VR,1 and 2×VR,1 which now define memristance switching. OR and NOR gates with more inputs can be implemented by adding more than two signals in the applied sum; this number is practically limited by the maximum voltage a device can tolerate without being damaged. For AND and NAND operations an additional memristor has to be included for each additional input signal so as to accordingly increase the cumulative threshold. As shown in Fig. 2c, when using two reciprocal devices in series or in parallel, the circuit implements XOR and XNOR logic operations, respectively. In the series connection the composite memductance rises from a low level (L’) to a high

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level (H’) if any of the applied inputs is logic ‘1’, i.e. exceeds Vth,1. However, if both inputs are logic ‘1’ then together they exceed Vth,2 and the composite memductance collapses to level L’. In the same fashion, the equivalent memductance of the parallel configuration collapses from level H” to L” if only one input is logic ‘1’, i.e. > VR,2, but rises again to H” if both inputs are logic ‘1’, thus together exceed VS,1. The memductance in these two cases is defined by the equations:  H ' , Vth ,1 < VIN ,SUM < Vth , 2 (3) XOR : G (VIN ,SUM = VIN ,1 + VIN , 2 ) =  otherwise  L' ,  H " , VR , 2 < VIN ,SUM < VS ,1 (4) XNOR : G (VIN ,SUM = VIN ,1 + VIN , 2 ) =  otherwise  L" ,

Regarding the composite conductance levels of the memristive ensembles, assuming {L, H} = {GON, GOFF}, then for the parallel/serial compositions it is {L’, H’} = {½×GON, ½×GOFF} and {L”, H”} = {2×GON, 2×GOFF}. Overall, the more expanded the thresholds for each configuration are, the easier it becomes to avoid potential overlap due to variation. Having |VRESET|>|VSET| (|VRESET|