Modulator (DSM) and monitoring the RMS output in the digital domain. A closed loop least mean squares (LMS) algorithm adjusts the sampling frequency of the ...
Calibration of Delta-Sigma Data Converters in Synchronous Demodulation Sensing Applications Ashwin Duggal and Sameer Sonkusale
John Lachappelle
Department of Electrical Engineering Tufts University Medford, MA 02144
The Charles Stark Draper Laboratory Cambridge, MA 02139-3563
Abstract— Delta-Sigma converters used in synchronous demodulation sensing applications for analog to digital conversion contain zeroes in the NTF (NTF) for aggressive noise shaping; however, analog component errors typically result in misplacement of the notch frequency resulting in lower SNDR and reduced sensor sensitivity. In this paper we propose a digital error detection technique by injecting a single tone directly at the input of the quantizer inside the loop of the Delta Sigma Modulator (DSM) and monitoring the RMS output in the digital domain. A closed loop least mean squares (LMS) algorithm adjusts the sampling frequency of the modulator until the tone strength is reduced to a minimum, which corresponds to the accurate placement of the notch. Simulation results have demonstrated an improvement of 20 dB for a Single-Loop, Third-Order CIFB (Cascade of Integrators, Feedback Form), single-bit quantizer, delta sigma modulator with an oversampling ratio (OSR) of 128 and a notch filter coefficient error of 50%. The technique is highly suitable for applications where high-Q resonators are employed, such as in tuning fork gyroscopes.
I.
INTRODUCTION
Delta sigma modulators (DSM) have been popular in synchronous demodulation sensing applications such as accelerometers [1]-[4], tuning fork gyroscopes [5] and other lock-in detection techniques due to higher signal to noise ratio and low power implementation. DSMs sample the input at a frequency much greater than Nyquist sampling rate, and utilize a loop filter that assists in the shaping of quantization noise introduced at the coarse quantizer, out of the band of interest, providing high in-band signal to noise ratio. DSMs are attractive from a cost standpoint as majority of the design complexity is placed in the digital domain. A common technique to enhance the resolution in DSM data converters is to place a zero in the Noise Transfer Function (NTF) of the DSM, creating a notch that produces aggressive noise shaping around the notch frequency. In many narrowband communication applications, where higher OSR is not feasible, zero placement is utilized for increased signal to noise ratio [6]. However, accurate placement of zeroes in NTF is not possible because of component errors induced due to process variations. This result in reduced SNR and could affect the sensitivity of the sensor or the bit-error-rate of the communication system. Calibration techniques are therefore
U.S. Government work not protected by U.S. copyright
sought to correct for these errors to adjust the poles and zeroes of the loop filter to desired values. A commonly used technique directly tunes the component values (e.g. capacitor array) of the filter [7]. This technique is simple and can provide coarse tuning of the filter coefficients and of the notch in the NTF. Unfortunately, major limitations of directly tuning the feedback coefficient via capacitive array tuning include difficulty in realizing the small-sized unit capacitors that dictates the feedback coefficient, resulting in the approach being only effective to applications that require coarse tuning. From a circuit area perspective, the layout complexity of capacitors and its digital controller results in significant area overhead. In this paper we propose, a unique approach of adjusting the sampling frequency of the modulator to correct the errors in the NTF. This is feasible and a more attractive solution since in most system-on-chip solutions for synchronous demodulation, such as for TFG, the system clock is derived directly from the high-Q resonator structure and is synthesized using built-in frequency synthesizer. One could thus change the parameters of the frequency synthesizer to adjust the sampling frequency of the modulator, and consequently correct for the notch misplacement in NTF. The basic premise of the calibration technique is to inject a single tone (generated from the built-in resonator) into the loop of the DSM, and based on the DSM loop response to this tone; to adaptively tune the loop parameters utilizing a LMS approach. There has been related work on background calibration using tone injection for MASH DSMs [8] and pipelined ADCs [9] and for bandpass DSMs [7]. Some key differences in the proposed approach is that tone injection for calibration is performed directly at the input of the quantizer, and secondly the tuning parameter is the sampling frequency of the DSM. This implementation is minimally invasive, does not require any additional high-precision analog circuitry, and it utilizes components already present on-chip. If one were to use the wideband topology for the DSM [10], then due to the presence of direct feed-forward path, the injection of the tone at the input of the quantizer is already provided for. More so, the calibration tone is readily available in applications such as
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IEEE SENSORS 2009 Conference
Fig. 1: LEFT: shows a typical TFG system-on-a-chip. It consists of a resonator structure driven into oscillation that serves as the calibration tone as well as the signal tone, RIGHT: Figures show the output FFT response of the tone injected inside the loop of the DSM for three cases; for the left two cases A and B, the notch frequency is not aligned with tone frequency resulting in low SNDR.
Fig. 2: LEFT: depicts the error estimation technique where strength of the tone is measured using bandpass filtering whereas the Fc is the carrier tone frequency. RIGHT: presents a conceptual block diagram of the bandpass filtration error detection scheme utilized during calibration mode.
TFG where the resonator structure is driven into oscillation and system clock is derived thereof. II.
DELTA SIGMA MODULATOR FRONT END FOR SYNCHRONOUS DEMODULATION SENSING
Fig. 1 depicts a block diagram of the TFG front-end sensor system as a representative example of a synchronous demodulation sensing system. It can be segmented into three major sections, the front-end signal conversion and amplification, DSM Analog to Digital converter and the digital filter, post processing circuitry. The architecture of the TFG consists of two proof masses, suspended by flexible beams that allow for the proof masses to move in the x and yaxis. These beams are connected to an anchor that connects to the substrate. Above the proof masses is a sense plate which forms a capacitor with the proof mass. To the both sides of the proof masses is a comb-like structure that causes the proof masses to oscillate in the sense axis. At start-up, the mechanical movement of the proof masses is detected by the outer series combs. The signal is subsequently amplified by the drive oscillator and fed to the inner sense combs, which drives the circuit. Additionally, this oscillatory signal is fed to a Phased Locked Loop (PLL) and up-converted to provide the clock for the rest of the system. When the system experiences rotation around the z-axis, the proof masses are displaced along the y-axis, resulting in a change in capacitance, as the distance between the sense plate and the proof masses changes. The difference signal, modulated upon the oscillation tone of the TFG, is then amplified by charge amplifier/variable gain amplifier, and is passed through an anti-aliasing filter and converted to the
digital domain by the DSM. The sampling clock for the DSM is generated by an on-chip frequency synthesizer, which is driven by the same tone signal supplied by the TFG. Upon digital conversion, the digital bit-stream is downsampled and decimated to produce the digital output, which is sent to the DSP processing unit. The DSP processing unit extracts the in-phase and out-of-phase sensor information. This approach for sensing, similar to lock-in measurement, has been shown to be highly sensitive as the signal information is contained in a single sinusoid tone (or a narrowband signal) reducing the effect of 1/f noise and offset errors. In such applications, the choice of the architecture for DSM is typically a single loop, higher order structure for low power and high-resolution requirements. Due to the narrow bandwidth of the input signal in synchronous demodulation sensing application, placement of the resonance notch (zeros) of the NTF at the location of the input frequency results in significant SNR improvement (see Fig. 1, right). Placement of the zero in the NTF requires a localized feedback loop within the DSM filter. Circuit optimization may result in a coefficient value too small to be effectively realizable. Parasitics as well as component variation severely effect the coefficient value changes the location of the notch frequencies away from desired value. This filter coefficient error must be corrected for accurate placement of the notch. Therefore, calibration is necessary to correct for these errors, which is the focus of this paper. III.
BASIC PRINCIPLE OF THE PROPOSED CALIBRATION
During calibration operation, the input signal, which is assumed to be a single tone, generated using the built-in resonator structure is added directly to the input of the quantizer. Since the input signal is introduced into the loop
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after the integrator, it is well known that it will be attenuated and shaped along with the quantization noise out of band of interest. Since the applied tone is at the same frequency as the notch in the NTF, the digital output will show aggressive attenuation of the tone. However due to the misplacement of the notch, the strength of the injected tone measured at the output will be detectable and will be low as the frequency of the notch gets closer to that of injected tone. At the output of the DSM, the strength of the tone is quantified via an RMS detector using a 10th order, standard digital band-pass, Butterworth filter and digital power measurement block. This is compared to a desired value. Based upon this difference, the least mean square adaptation is utilized to iteratively tune the NTF using sampling clock adjustment. This is achieved by adjusting the parameters of the Fractional-PLL based synthesizer that controls the sampling clock of the modulator. A LMS approach is utilized to adjust the parameters of the frequency synthesizer until the error is reduced. This corresponds to the event that notch in the NTF completely aligns with the input signal tone frequency. This approach is depicted in Fig. 2. The LMS update equation for sampling frequency update can be written as follows: .
injected at the input of the delta sigma modulator and the RMS power was detected at the output. The output was recovered after A/D conversion, filtered and measured by the RMS detector. Depending on the RMS value detected at the output and the error correction technique implemented, the sampling frequency of the PLL was adjusted accordingly, using equations 2 or 3, or the capacitance was directly tuned. This process was repeated until the RMS performance was determined to be acceptable. The input signal has been removed from the plots in order to illustrate the performance gain of the calibration method. A 50% mismatch in the resonator coefficient to the error corrected performance. To test performance, a 217-point FFT was taken. The noise floor was integrated across a 200 Hz bandwidth, around the 20 kHz signal. Sampling clock based tuning with bandpass error estimation and sampling clock based tuning with low-pass filter based error estimation both had the resolution of the frequency synthesizer set to 160 kHz. The performance of the calibration system produced results, of which can be found depicted in Fig. 4. The calibration scheme recovered 20 dB of SNR performance from the mismatch error in the coefficient.
1 .
.3
The major advantage of the sampling clock based tuning is that the architecture and circuit elements of the main modulator are untouched. Moreover since the approach relies on utilizing an already existing frequency synthesizer, available in most synchronous demodulation based sensing applications, very little additional hardware is required to realize calibration. Moreover majority of the circuit complexity is placed in the digital domain, introducing very little power consumption to the circuit. Another major advantage of sampling clock based tuning is that the tuning resolution is not limited by fabrication; rather the performance of the calibration is based upon the resolution of the Frequency Synthesizer, which gets better with technology scaling. Precise tuning is possible given that the frequency synthesizer is able to resolve a decent frequency range. The disadvantage of the approach however is that the technique is not portable to many other applications where frequency synthesizers are not used or it is not feasible to alter its parameters. IV.
1 1 − z −1
Fig. 3: Third-Order Delta Sigma Modulator, Cascade of Integrators, Feedback form structure. Table I DSM Coefficient Values Utilized During Simulation
SIMULATION RESULTS
For evaluation we used a 3rd order, low-pass, single-loop ΣΔ modulator with an OSR of 128. The filter coefficients can be found in Table 1. NTF for the DSM is a third-order, inverse Chebyshev high-pass function with an optimized zero located at the input signal frequency. The OSR and filter coefficients were chosen accordingly to optimize SNR performance as well as maintain system stability. The system architecture can be found in Fig. 3. Utilizing Simulink, the system was simulated and the calibration performance was measured. The sampling clock frequency was 5.12 MHz. A 20 kHz sinusoidal tone was
1 1 − z −1
a1
1 1 − z −1
V.
Coefficient
Value
a0
108/256
a1
156/256
a2
80/256
b1
58/256
b2
48/256
k1
0.08/256
CONCLUSION
In this paper, we have presented digital calibration of delta sigma converters used in synchronous demodulation sensing applications such as Tuning Fork Gyroscopes. The approach relied on injection of a tone inside the loop at the input of the quantizer, with its frequency set at the desired notch frequency and measuring the response of the modulator. Based on the response, a LMS algorithm was used to correct for the misplacement of the notch frequency. The approach
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taken to calibrate for the mismatch error adjusted the sampling frequency of the modulator itself. Coefficient errors of 50%, or greater, was shown to have been corrected using Simulink environment. Although the results presented here were targeted for correction of notch frequency in sensing applications, it can also be utilized for communication applications where the OSR is limited. Techniques can also be extended to correct for more than just the location of the notch frequency, and will be the focus of future investigation.
Band of Interest
[3]
Yufeng Dong; Kraft, M.; Redman-White, W., "Higher Order NoiseShaping Filters for High-Performance Micromachined Accelerometers," Instrumentation and Measurement, IEEE Transactions on , vol.56, no.5, pp.1666-1674, Oct. 2007. [4] J. Wu, G.K. Fedder, and R. Carley, “A low-noise low-offset chopper stabilized capacitive-readout amplifier for CMOS MEMS accelerometers,” in IEEE Int. Solid State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb.2002, pp. 428–429. [5] Sharma, A.; Zaman, M.F.; Ayazi, F., "A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork Microgyroscopes," Solid-State Circuits, IEEE Journal of , vol.42, no.8, pp.1790-1802, Aug. 2007. [6] Raghavan, G.; Jensen, J.F.; Walden, R.H.; Posey, W.P., "A bandpass ΣΔ modulator with 92 dB SNR and center frequency continuously programmable from 0 to 70 MHz," Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International , vol., no., pp.214-215, 459, 1997. [7] Yun-Shiang Shu; Bang-Sup Song; Bacrania, K., "A 65nm CMOS CT ΣΔ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection," Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International , vol., no., pp.500-631, Feb. 2008. [8] Kiss, Peter, José Silva, et. al, “Adaptive Digital Correction of Analog Errors in MASH ADC’s – Part II: Correction using Test-Signal Injection,” IEEE Transactions on Circuits and Systems–II: Analog and Digital Signal Processing, 2000. [9] Bjornsen, J.; Moldsvor, O.; Saether, T.; Ytterdal, T., "A 220mW 14b 40MSPS gain calibrated pipelined ADC," Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European , vol., no., pp. 165-168, Sept. 2005 [10] J. Silva, U. Moon, J. Steensgaard, and G.C. Temes, "Wide-band lowdistortion delta-sigma ADC topology." Electron. Lett., vol. 37, no. 12, pp. 737-738, 2001.
Band of Interest
Fig. 4: Output FFT for pre and post calibrated DSM circuits. Simulation results show a 20 dB improvement in SNR performance when the frequency is adjusted.
VI.
ACKNOWLEDGEMENTS
The authors of this paper would like to acknowledge the partial support of Draper Laboratories. The authors would also like to thank Rob Bousquet for his help in laying the groundwork understanding of DSM operation. VII. [1]
[2]
REFERENCES
M. Lemkin, B. Boser, “A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics”, IEEE Journal of Solid State Circuits, vol. 34, pp. 456468, 1999. M. Kraft, “Closed loop digital accelerometer employing oversampling conversion,” Ph. D. Thesis, University of Coventry, U.K., 1997.
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