Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-
2010, John Wiley. 15-1. Chapter 15: Design Examples. Department of Electronic
...
Chapter 15: Design Examples
Chapter 15: Design Examples Prof. Ming-Bo Lin
Department of Electronic Engineering National Taiwan University of Science and Technology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-1
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-2
Chapter 15: Design Examples
Objectives After completing this chapter, you will be able to: Describe basic structures of µP systems Understand the basic operations of bus structures Understand the essential operations of data transfer Understand the design principles of GPIOs Understand the design principles of timers Understand the design principles of UARTs Describe the design principles of CPUs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-3
Chapter 15: Design Examples
Syllabus Objectives Bus A µp system architecture Bus structures Bus arbitration
Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-4
Chapter 15: Design Examples
A Basic µP System
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-5
Chapter 15: Design Examples
Syllabus Objectives Bus A µp system architecture Bus structures Bus arbitration
Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-6
Chapter 15: Design Examples
Bus Structures Tristate bus using tristate buffers often called bus for short
Multiplexer-based bus using multiplexers
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-7
Chapter 15: Design Examples
A Tristate Bus
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-8
Chapter 15: Design Examples
A Tristate Bus Example // a tristate bus example module tristate_bus (data, enable, qout); parameter N = 2; // define bus width input enable; input [N-1:0] data; output [N-1:0] qout; wire [N-1:0] qout; // the body of tristate bus assign qout = enable ? data : {N{1'bz}}; endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-9
Chapter 15: Design Examples
A Bidirectional Bus Example
// a bidirectional bus example module bidirectional_bus (data_to_bus, send, receive, data_from_bus, qout); parameter N = 2; // define bus width input send, receive; input [N-1:0] data_to_bus; output [N-1:0] data_from_bus; inout [N-1:0] qout; // bidirectional bus wire [N-1:0] qout, data_from_bus; // the body of tristate bus assign data_from_bus = receive ? qout : {N{1'bz}}; assign qout = send ? data_to_bus : {N{1'bz}}; endmodule Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-10
Chapter 15: Design Examples
A Multiplexer-Based Bus
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-11
Chapter 15: Design Examples
Syllabus Objectives Bus A µp system architecture Bus structures Bus arbitration
Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-12
Chapter 15: Design Examples
Daisy-Chain Arbitration Types of bus arbitration schemes daisy-chain arbitration radial arbitration
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-13
Chapter 15: Design Examples
Syllabus Objectives Bus Data transfer Synchronous transfer mode Asynchronous transfer mode
General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-14
Chapter 15: Design Examples
Data Transfer Modes Data transfer modes synchronous mode asynchronous mode
The actual data can be transferred in parallel: a bundle of signals in parallel serial: a stream of bits
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-15
Chapter 15: Design Examples
Synchronously Parallel Data Transfers Each data transfer is synchronous with clock signal Bus master Bus slave
Two types Single-clock bus cycle Multiple-clock bus cycle
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-16
Chapter 15: Design Examples
Synchronously Parallel Data Transfers
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-17
Chapter 15: Design Examples
Synchronously Serial Data Transfers Explicitly clocking scheme Implicitly clocking scheme
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-18
Chapter 15: Design Examples
Synchronously Serial Data Transfers Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-19
Chapter 15: Design Examples
Syllabus Objectives Bus Data transfer Synchronous transfer mode Asynchronous transfer mode
General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-20
Chapter 15: Design Examples
Asynchronous Data Transfers Each data transfer occurs at random Control approaches strobe scheme handshaking scheme
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-21
Chapter 15: Design Examples
Strobe
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-22
Chapter 15: Design Examples
Handshaking Four events are proceeded in a cycle order
ready (request) data valid data acceptance acknowledge
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-23
Chapter 15: Design Examples
Handshaking Two types source-initiated transfer destination-initiated transfer
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-24
Chapter 15: Design Examples
Asynchronously Serial Data Transfers Transmitter Receiver
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-25
Chapter 15: Design Examples
Asynchronously Serial Data Transfers
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-26
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-27
Chapter 15: Design Examples
General-Purpose Input and Output Devices The general-purpose input and output (GPIO) input output bidirectional
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-28
Chapter 15: Design Examples
General-Purpose Input and Output Devices An example of 8-bit GPIO
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-29
Chapter 15: Design Examples
Design Issues of GPIO Devices
Readback capability of PORT register Group or individual bit control Selection the value of DDR Handshaking control Readback capability of DDR Input latch Input/Output pull-up Drive capability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-30
Chapter 15: Design Examples
General-Purpose Input and Output Devices The ith-bit of two GPIO examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-31
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Interface Basic operation modes Advanced operation modes
Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-32
Chapter 15: Design Examples
Timers Important applications
time-delay creation event counting time measurement period measurement pulse-width measurement time-of-day tracking waveform generation periodic interrupt generation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-33
Chapter 15: Design Examples
Timers
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-34
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Interface Basic operation modes
Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-35
Chapter 15: Design Examples
Basic Timer Operations Timers
What is a timer? What is a counter? What is a programmable counter? What is a programmable timer?
Basic operation modes
terminal count (binary/BCD event counter) rate generation (digital) monostable (or called one-shot) square-wave generation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-36
Chapter 15: Design Examples
Terminal Count
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-37
Chapter 15: Design Examples
Rate Generation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-38
Chapter 15: Design Examples
Retriggerable Monostable (One-Shot) Operation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-39
Chapter 15: Design Examples
Square-Wave Generation clk 4 out
3
2
1
0(4)
3
2
1
0(4)
Latch register = 4 (a) A waveform example of square-wave mode Data bus wr latch_load Latch
timer_load timer_load generator clk gate
rd
Shift plus LSB
D Q CK
out
timer timer is 1
out logic
timer_enable (b) Block diagram of square-wave mode
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-40
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators
A simple CPU design Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-41
Chapter 15: Design Examples
UARTs Hardware model the CPU interface the I/O interface
Software model
receiver data register (RDR) transmitter data register (TDR) status register (SR) control register (CR)
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-42
Chapter 15: Design Examples
UARTs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-43
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators
A simple CPU design Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-44
Chapter 15: Design Examples
Design Issues of UARTs
Baud rate Sampling clock frequency Stop bits Parity check
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-45
Chapter 15: Design Examples
A Transmitter of UARTs The transmitter
a transmitter shift data register (TSDR) a TDR empty flag (TE) a transmitter control circuit a TDR parity generator
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-46
Chapter 15: Design Examples
A Transmitter of UARTs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-47
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators
A simple CPU design Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-48
Chapter 15: Design Examples
A Receiver of UARTs The receiver
a RDR a receiver shift data register (RSDR) a status register a receiver control circuit
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-49
Chapter 15: Design Examples
A Receiver of UARTs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-50
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators
A simple CPU design Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-51
Chapter 15: Design Examples
Baud-Rate Generators The baud-rate generator provides TxC and RxC
Design approaches Multiplexer-based approach Timer-based approach Others
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-52
Chapter 15: Design Examples
Baud-Rate Generators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-53
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Programming model Datapath design Control unit design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-54
Chapter 15: Design Examples
CPU Basic Operations
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-55
Chapter 15: Design Examples
The Software Model of CPU
The programming model Instruction formats Addressing modes Instruction set
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-56
Chapter 15: Design Examples
The Programming Mode
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-57
Chapter 15: Design Examples
Instruction Formats Two major parts Opcode Operand
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-58
Chapter 15: Design Examples
Addressing Modes The ways that operands are fetched
register indexed register indirect immediate
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-59
Chapter 15: Design Examples
The Instruction Set Double-operand instruction set
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-60
Chapter 15: Design Examples
The Instruction Set Single-operand instruction set
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-61
Chapter 15: Design Examples
The Instruction Set Jump instruction set
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-62
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Programming model Datapath design Control unit design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-63
Chapter 15: Design Examples
A Datapath Design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-64
Chapter 15: Design Examples
ALU Functions
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-65
Chapter 15: Design Examples
Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Programming model Datapath design Control unit design
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-66
Chapter 15: Design Examples
A Control Unit The decoder-based approach
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-67
Chapter 15: Design Examples
A Control Unit A better approach
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-68
Chapter 15: Design Examples
A Control Unit The operations of T3 and T4 are determined separately by each instruction
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
15-69
