Characterizing the Effects of Clock Jitter Due to Substrate Noise in ...

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Characterizing the Effects of Clock Jitter Due to Substrate Noise in Discrete-Time ∆/Σ Modulators Payam Heydari Department of Electrical Engineering and Computer Science University of California Irvine, CA 92697-2625 E-mail: [email protected] ria and applications [3], only a few papers study the effect of substrate noise in the performance of oversampling data converters. Blalack et al. in [14] presented an experimental study of the effects of switching noise in a high resolution oversampling data converter. With the design of an experimental test circuit, the authors were able to make interesting observations about the temporal spacing of the noise clock transitions with respect to the sampling clock transitions and its impact on the signal-to-noise+distortion (SNDR) ratio of the converter. The authors, however, did not quantify their observations and experiments. Therefore, some of their experimental results are valid only for a particular ∆Σ architecture that was used in their experiments. [13] studies the performance degradation in CT ∆Σ modulator due to the clock jitter. The noise model used by [13] is inaccurate and this model is not properly incorporated in the behavioral model of the CT ∆Σ modulator. Demir et al. in [15] proposed a generalized methodology for the evaluation of the interference noise caused by the digital switching activity. The authors used Markov chains to model the digital switching activities. The propagation media (e.g., substrate, the power-grid network) is modeled by a linear time-invariant (LTI) system. The methodology is very general and as a result, cannot address specific problems in conjunction with the ∆Σ modulators. The goal of this paper is to consider the effects of substrate noise on the performance of the DT oversampling ∆Σ modulators. The main contributions of this paper are as follows: 1. an efficient stochastic model for substrate noise coupling in heavily doped substrates, 2. a new study on the effects of clock jitter induced by substrate noise in the performance of the DT ∆Σ modulators. Section 2 presents a general overview of ∆Σ modulators. Section 3 explains a new mathematical model for substrate noise. Section 3 illustrates substrate noise effect on the ∆Σ modulator. Next, a detailed analytical model for the PLL clock jitter induced by substrate noise is proposed in Section 4. The impact of the clock jitter on the ∆Σ modulator is presented in Section 5. Section 6 summarizes the experimental results. Finally, Section 7 presents the conclusions of our paper. All the details regarding calculations are omitted due to the space limitations.

Abstract - This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling ∆Σ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the ∆Σ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the ∆Σ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order ∆Σ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1pF capacitors is designed in a 0.25µm standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.

Categories and Subject Descriptors: B.7.2 [Design Aids]: Types and Design Styles -Mixed-signal simulation

General Terms: Algorithms, Design, Theory. Keywords: Mixed-signal Integrated Circuits, ∆Σ modulators, Substrate Noise, Phase-Locked Loop, Phase Noise, Jitter.

1. INTRODUCTION One of the greatest challenges in the design of a system-on-a-chip (SOC) is the need to place sensitive analog circuits and large complex digital signal processing components on the same die. Due to the highlevel of interactions between the noisy digital blocks with the noisesensitive analog portion of the system through various propagation mechanisms it is highly possible that the large-signal switching transients of the digital circuits corrupt the performance of the analog subblocks. Coupling from digital circuits into analog components mostly propagates through the common substrate, thereby being named as substrate noise. Substrate coupling degrades analog signal integrity in mixed-signal integrated circuits where thousands of digital gates may inject noise into the substrate, especially during clock transitions, introducing hundreds of millivolts of disturbance in the substrate potential [1],[2]. ∆Σ modulation is a ubiquitous technique widely used in mixed-signal integrated circuits to achieve high resolution systems including oversampling data converters [3]-[6], and frequency synthesizers [7][12]. Depending on the implementation there are two types of ∆Σ modulators: discrete-time (DT) [3], and continuous-time (CT) [13]. The more popular DT ∆Σ modulators, which are the focus of this paper, are less susceptible to noise than the CT counterparts and are easily implemented using switched capacitor circuits. Although numerous papers use the oversampling technique to design high-resolution systems that target various types of design crite-

2. AN OVERVIEW OF ∆/Σ MODULATORS The concept of the ∆Σ modulation technique is well understood in the context of oversampling data converters (figures 1 (a) and (b)). Anti-aliasing filter

S/H

∆Σ modulator

Digital

low-pass filter

OSR

(a)

OSR

Interpolation low-pass filter

∆Σ modulator

m-bit D/A

Analog low-pass filter

(b)

Fig. 1. (a) Block Diagram of an oversampling A/D converter. (b) block diagram of an oversampling D/A converter.

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As its name suggests the basic idea behind an oversampling data converter is to sample (re-sample in the case of a D/A converter) the input signal at a rate significantly faster than the Nyquist rate so as to spread the quantization noise power spectral density over a bandwidth, fs, which is much greater than the Nyquist frequency, 2fB (fB is the signal bandwidth). The signal-to-noise ratio (SNR) is enhanced by as much as fs ⁄ 2f B , which is called oversampling ratio (OSR). 532

The circuit is comprised of forty 1pF capacitors each driven by 6stage CMOS tapered buffers. To reduce the simultaneous switching noise, every ten tapered buffers are connected to a single ground and supply pin. In Fig. 3 (a), ZVDD,k , ZGND,k (k = 1, ... , 4) are power/ground impedances modeling the chip-package interface parasitics including the chip bondwires and package traces. These impedances are highly inductive. ZSUB,i ( i ∈ [ 1, n ] ) represents the equivalent substrate impedance consisting of the substrate bias resistance and inductance, respectively. ZN,i is the equivalent impedance from the chip ground to the heavily doped substrate including the wiring capacitance and junction capacitance of NMOS device. ZP,i is the equivalent impedance from the chip power supply to the heavily doped substrate including the nwell junction capacitance and the nwell physical resistance. ZL,i is the equivalent load impedance including the gate capacitance of the following fan-out stages. CD is the on-chip decoupling capacitor used to reduce the power/ground bounce. Since the substrate is tightly coupled to the return path by distributed surface substrate contacts, the voltage bounce arising from logic switching, especially on the ground path, appears as substrate noise. Fig. 3 (b) shows the substrate noise for a complete one-cycle simultaneous switching of the buffers. Our goal is to provide a simple closed-form expression for substrate noise that will be utilized later to investigate the impact of clock jitter induced by substrate noise on ∆Σ modulators. In practice, substrate noise is caused by random switching pattern of digital switching circuits in a chip. The switching activity of a large digital block is a function of the nature and the statistics of the input signals. Subsequently, substrate noise, vsub(t), is a stochastic process. In order to characterize the statistics of substrate coupling due to the circuit switching, an observation based on actual experimental test circuits is made [21]. In a lightly doped epitaxial layer grown on a heavily doped substrate, if the analog and digital circuits are separated by at least four times the thickness of the epitaxial layer, the resistance between the substrate contacts will be independent of their separations [21]. Therefore, the spacing between the switching blocks causes solely a random phase shift on the noise fluctuations. The peak amplitudes of damped oscillations for each noise waveform vsub,N(t) and vsub,P(t), (cf. Fig. 3 (b)) are a function of switching activities of digital circuits and are thus represented by discrete-time random processes. The above observations helps us derive a mathematically robust and efficient stochastic model for substrate noise, as follows:

Higher resolutions and wider dynamic ranges are attained through the use of the ∆Σ modulator, which effectively reshapes the quantization noise over the frequency band of interest, and enhance the signal-to-noise ratio (SNR). Due to their better performance in the presence of clock jitter and noise, the DT ∆Σ modulators are used in mixed-signal integrated circuits compared to their continuous-time counterparts [16] [17]. Therefore we focus our analysis on the discrete-time ∆Σ modulators, although a similar study can also be done for the continuous-time ∆Σ modulators. There are many architectures proposed for the DT ∆Σ modulators [5], [16], [18]. All topologies may be characterized by two transfer functions: the noise transfer function (NTF) and the signal transfer function (STF). The NTF determines to what extent the quantization noise is reduced in a given bandwidth and hence determines the overall SNR of the converter. From a system viewpoint all single-quantizer loops are indicated by the universal architecture shown in Fig. 2:

e[n]

y[n]

H∆Σ(z)

u[n] v[n]

noise-shaped low resolution digital signal

m-bit D/A

Fig. 2. The system block diagram of a discrete-time ∆Σ modulator Depending on the specific application and the frequency band of the input signals H∆Σ (z) can be either a low-pass filter (in the base-band processing) or a bandpass filter (in RF and wireless applications). ∆Σ modulators are more noise sensitive than other blocks in figures 1(a) and (b). Like any feedback system, they can potentially be driven to unstability, if the closed-loop poles are close to the unit-circle in the zplane. They are also susceptible to clock jitter due to substrate noise. To understand this effect, substrate noise must first be characterized.

3. SUBSTRATE NOISE CHARACTERIZATION In this section, an efficient model for substrate coupling in mixed-signal integrated circuits is developed. The analytical model contains the statistical nature of the switching activity of digital circuits. The model is germane to epi-type heavily doped substrate used in mixed-signal circuits. Note that this model is less accurate compared to 3D models proposed in [19] and [20]. However, the advantage of the proposed model is that it can appropriately be incorporated in the PLL as well as ∆Σ modulator circuit models discussed later. In a CMOS mixed-signal integrated circuit the substrate is normally composed of a lightly doped epitaxial layer grown on a heavily doped substrate in order to minimize the transistor latch-up [21]. In an epitype substrate technology the injected lateral current from the source of a digital circuit (e.g., a CMOS inverter) flows through the heavily doped substrate material because of its low resistivity compared to the inter-layer silicon or epitaxial layer [21]. The bulk can thus be modeled as a single electrical node for any given technology (see [21]). Fig. 3 (a) demonstrates the circuit schematic being utilized to demonstrate the substrate noise injection in an epitaxial technology.

[t ⁄ T]

vsub( t ) =

n = –∞

...... CD Vin

ZP2

ZP1 ZL1

ZN1 Z SUB1

ZPn

...... ZLn

ZL2

...... ZN2

ZSUB2

ZGND,k

vsub(t)

ZN,n

......

ZSUB,n

vsub,P

0.3

(a)

(b)

Voltages (lin)

200m

0

0

-0.3 -200m

vsub,N t(ns) 14 16 18 20 14n

18n 16n Time (lin) (TIME)

sub , N [n ]vsub, N ( t – nT –λn )

+

∑A

n = –∞

T   sub, P [n ]vsub, Pt – nT– --- – γn 2

(1) Substrate noise is comprised of two additive terms, one is due to the low-to-high signal transition, and the second one is due to the high-tolow signal transition. Asub,N(P) is a discrete-time random process that accounts for the number of adjacent switching circuits switching simultaneously. λ n and γ n are a set of uniformly distributed independent random variables in the interval [0, T] (T is the clock cycle-time). Their presence in the noise expression is because the digital circuits switch randomly across the chip. The random switchings of the digital circuits located at different locations across the chip are directly translated to random signal propagation delays at the sensitive analog terminals. The analysis can easily be extended to a more general scenario in which there are multiple clock frequencies across the digital circuit (such a discussion is out of the scope of this paper). The dominant source of substrate noise in large-scale mixed-signal integrated circuits is the leakage of the voltage bounce on the highly inductive supply/ return rails into the substrate. The ringing duration of substrate noise is small compared to the duty-cycle of the clock signals currently being used in the switched capacitor circuits of a ∆Σ modulator. Therefore, for the particular application discussed in this paper, the substrate noise is accurately modeled as impulse train with normally distributed random area and a uniformly distributed random time-shift to account for the switching activity and random signal propagation delay, respectively. Consequently, the noise expression in Eq. (1) is simplified to a stochastic impulse train.

VDD

ZVDD,k

∑A

[ t ⁄ T]

20n

Fig. 3. (a) The circuit consisting of multistage tapered buffers for substrate noise injection. (b) Substrate noise waveform

533

Theorem 1 proves useful in determining the spectral contents of vsub(t).

Shown in Fig. 5 is the circuit topology of a differential delay stage. Each MOS transistor of the differential source-coupled pair experiences a large-signal gate voltage and therefore, it experiences multiple transitions in its region of operation. Moreover, the ID-VGS relationship of a MOS transistor is nonlinear for both triode and saturation regions. All these phenomena cause the VCO frequency to be a nonlinear function of the supply and input control voltages. This nonlinear relationship is also dependent on the circuit topology being adopted for a delay stage, however, as will be seen later in this section, the general relationship between the excess VCO frequency and substrate noise remains approximately the same. In most of today’s differential ring oscillator architectures the VCO gain is controlled by the tail current which makes it possible to have a wider tuning range and a pseudo-linear frequency-voltage relationship.

Theorem 1. Consider the following wide-sense cyclo-stationary stochastic process:

∑ A[n ]v (t – nT ) ∞

x (t) =

n = –∞

where A[n] is a discrete-time random-process. The shifted process z(t), given below: z( t ) =

∑ A[n ]v (t – nT – λ ) ∞

n

n = –∞

is a wide-sense stationary process, whose power spectral density is: jω 2 (2) S z ( ω ) = --1- SA( e ) V (ω ) T Proof: This theorem is an extension of Theorem 2 in pp. 374 of the reference [22].

VDD




Using Theorem 1 and Eq. (2) the power spectral density (PSD) of substrate noise vsub(t) is obtained as follows: 1 jω 2 jω 2 S sub ( ω ) = --- [ SA ( e ) Vsub, N (ω ) + SA ( e ) Vsub, P (ω ) ] (3) sub, N su b , P T The above analytical model is used in Section 4 to derive the timing jitter and the phase-noise of a PLL clock generator.

CL

The operation of a discrete-time ∆Σ modulator implemented using the switched-capacitor circuits depends on the complete charging or discharging during each phase of the clock. Therefore, the effects of clock jitter induced by substrate noise on a switched capacitor circuit can be analyzed by examining its effect on the sampling of the input signal and the reconstruction of the output signal. This also implies an important observation, that is, the effects of the clock jitter on a switched-capacitor ∆Σ modulator is independent of the structure or order of the modulator. Discrete-time ∆Σ modulators are clocked with a monolithic phaselocked loop (PLL). To analyze the effects of clock jitter induced by substrate noise, it is needed to study the noise impact on the PLL timing jitter. In this section we briefly study the timing jitter induced by substrate noise in closed-loop phase-locked loops. [23]-[25] discuss the PLL timing jitter in more depth and detail. The jitter and phase noise in a free-running oscillator are not discussed (see [25] and [26]). The main focus is on charge-pump PLLs, although the analysis is easily extended to any type of phase-locked loop (e.g., the gm -based PLL). Fig. 4 shows a simplified system block diagram of a chargepump PLL circuit employed as a clock generator.

Phase/Frequency Detector

Lowpass Filter

Frequency Divider

÷M

(6)

ISS

Using the BSIM3v3 MOS model, the tail current ISS is: ISS = Wυsat Co x (Vcont + vcont, sub – vtr, sub – VTH – VDS, sat ) (7) According to Eq. (7), substrate noise affects ISS through both the control path and the direct coupling to the tail current’s transistor. The former component is attenuated by using a differential control input while the latter being almost intact. Since the velocity-saturated drainsource voltage, VDS,sat , is also a nonlinear function of the gate-source voltage, the tail current becomes a nonlinear function of substrate noise which introduces harmonic distortion at the PLL output. To quantify the VCO phase noise and subsequently, the PLL jitter induced by substrate noise, we first obtain the VCO phase noise in response to substrate noise variations. For the ultimate design criteria of having a small coupling from the substrate and supply rail to the PLL circuit we can simplify Eq. (7) and derive the autocorrelation function of excess frequency variation in terms of the autocorrelation of substrate noise. Starting with Eq. (7), the current variations due to substrate noise is equal to: (8) ∆ISS , noise = Wυsat Co x κ ∆ vsub LE sat 2 if vsub < 0.5 (Vcont – VTH ) κ ∆ ≈ ---------------------------------κ ( Vcont – VTH ) where vsub accounts for the total contributions of coupled noise on the control input line and coupled noise through the substrate bulk. The above inequality is satisfied by placing on-chip decoupling capacitors across the large current drivers. Differential operation reduces the noise to a great extent. Nonetheless, the large-signal operation of a ring VCO influences the overall VCO sensitivity to substrate noise. The output current of the differential delay stage in Fig. 5 is a function of the instantaneous differential input voltage V id = Vi1 – Vi2 to the delay stage and the current at the output of the tail current ∆I SS, noise+ ISS , with ISS being the noise-free current: (9) I o = I D1 – I D2 = F ( V id, I SS + ∆ISS , noise ) Assuming ∆I SS, noise