Charge-Controlled GaN FET Modeling by

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786

1

Charge-Controlled GaN FET Modeling by Displacement Current Integration from Frequency-Domain NVNA Measurements Daniel Niessen, Member, IEEE, Gian Piero Gibiino, Student Member, IEEE, Rafael Cignani, Member, IEEE, Alberto Santarelli, Member, IEEE, Dominique M. M.-P. Schreurs, Fellow, IEEE, and Fabio Filicori  Abstract—We propose an efficient procedure for the extraction of a charge-controlled nonlinear model of a 1-mm Gallium Nitride on Silicon Carbide (GaN-on-SiC) Field-Effect Transistor (FET) (L = 0.25 m) from Nonlinear Vector Network Analyzer (NVNA) acquisitions. A fast, single-shot measurement technique is described, in which the two Device-Under-Test (DUT) ports are excited by single-tone sources at carefully selected tone frequencies, acquiring calibrated waveforms at the on-wafer DUT ports with an almost complete coverage of the voltages domain. The gate and drain charge functions identification is executed by integration of the displacement currents in the frequency domain. A suitable approach for separating the conductive and displacement drain current components is provided. The presence of thermal self-heating and charge trapping phenomena is empirically evaluated, and accounted through an equivalent voltage approach. Experimental validation is provided at 2.5 and 5 GHz for a Continuous-Wave (CW) excitation, and at 2.5 GHz for a two-tone excitation. Index Terms— Large-signal measurements, Nonlinear Vector Network Analyzer (NVNA), Field-effect transistors (FETs), Gallium nitride (GaN), Semiconductor device modeling.

I. INTRODUCTION

G

AN

FET technology is fundamental to meet the high power, high efficiency, and wideband specifications of radio-frequency (RF) power amplifiers (PAs) in next generation wireless transmitters. In order to allow a full exploitation of GaN FETs electrical performances in PA design, much research has been invested during the last decade for providing precise, reliable, easy-to-extract, and numerically-efficient GaN FET nonlinear models [1]–[7]. However, this goal has revealed to be not a trivial one, due to the specific behavior shown by GaN devices. In particular, the presence of charge trapping phenomena, their nonlinear dynamic dependency with respect to the voltages applied to This paper is an expanded version from the IEEE MTT-S International Microwave Symposium, San Francisco, CA, USA, May 22-27 2016. D. Niessen, G. P. Gibiino, R. Cignani, A. Santarelli and F. Filicori are with the Department of Electrical, Electronic, and Information Engineering (DEI) “Guglielmo Marconi,” University of Bologna, 40136 Bologna, Italy (e-mail: [email protected]). D. M. M.-P. Schreurs is with ESAT-TELEMIC, KU Leuven, B-3001 Leuven, Belgium (e-mail: [email protected]).

the transistor’s terminals, and the high thermal dissipation involved, cause non-negligible dispersive effects measurable under large-signal operation [8], [9]. As GaN technology is under continuous performance improvements, beside physicsbased models (e.g., [10], [11]), developed through numerical or analytical approaches, measurement-based compact models, such as equivalent circuit models (e.g. [7]), look-up-tablebased (e.g., [12],[13]) and artificial-neural-networks-based models (e.g., [14]) have gained interest for their qualities of acceptable accuracy, relatively low complexity, and high portability among the various process evolutions. Among compact models, those based on charge-controlled approaches (e.g., [15]) implicitly satisfy terminal charge-conservation conditions, and allow more accurate predictions of critical figures of merit, such as efficiency and distortion. However, if aiming to include complex dispersive effects in order to achieve higher prediction accuracy, the number of measurements needed to identify compact models can become very large (e.g., [1]), involving consistent extraction time and potentially stressful transistor operation throughout the extraction process. The actual availability of advanced instrumentation capable of nonlinear vector network analysis such as NVNAs or largesignal network analyzers (LSNAs) [1], [16] provides the means for developing efficient identification techniques for model extraction (e.g., [16]-[20]). The idea consists in reducing the measurement time involved in the extraction of empirical transistor models, while measuring the DUT under realistic large-signal excitations. In other words, the aim is to provide a simple identification method for both the conduction current function as well as for the intrinsic terminal charge functions (or, alternatively, the nonlinear capacitances) from the minimum set of measured data. For instance, in [17], a procedure based on harmonic balance (HB) simulations shows the necessity to acquire at least three independent measurements for each point on the 𝑣𝐺 , 𝑣𝐷 plane in order to identify the nonlinear capacitances of the transistor. The work in [13] follows a similar approach for the time-domain extraction of a Gallium Arsenide (GaAs) High Electron Mobility Transistor (HEMT) model from large-signal measurements at a specific RF load, while sweeping the dc bias to cover the 𝑣𝐺 , 𝑣𝐷 plane. In [14], the authors exploit the

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786

(a)

(b) Fig. 1. Charge-Controlled GaN FET model schematic. (a) Extrinsic network. (b) Intrinsic network. Extrinsic parasitic values: 𝑅𝐺 = 1.7 Ω, 𝑅𝐷 =1.3 Ω, 𝑅𝑆 =0.1 Ω, 𝐿𝐺 =102 pH, 𝐿𝐷 = 88 pH, 𝐿𝑆 = 12 pH, 𝐶𝐺𝑆,𝑝 = 30 pF, 𝐶𝐷𝑆,𝑝 = 40 pF, 𝐶𝐺𝐷,𝑝 = 0 pF.

Fig. 2. Large-signal NVNA-based characterization setup (phase reference channel for calibrated measurement not shown).

2

artificial neural network (ANN) and to obtain the model of both the conduction and displacement drain current components of an SOS-MOSFET. The presence of thermal and charge trapping related effects in GaN FETs actually makes the problem of separation of the two drain current components particularly difficult. In [19], by means of a measurement approach somehow similar to [20], although tailored for GaN FETs, we have shown how to select the proper excitation frequencies for an iso-thermal and isodynamic extraction of the charge function at the gate terminal from a direct integration of the measured displacement current. In this work, we extend the approach in [19] to identify the conduction current as well as the displacement current (thus, the drain charge function) at the drain terminal from a single-shot NVNA acquisition. Moreover, we make use of the extracted charges to propose a new compact chargecontrolled nonlinear model for GaN FETs, which takes into account both thermal and charge trapping effects. The identification experiments rely on NVNA instrumentation (in this case, a Keysight PNA-X with 67 GHz measurable bandwidth) capable of accurate, low-noise, and high dynamic range (e.g., > 100 dB) acquisitions to measure frequency components of periodic, yet wideband excitations applied at both the gate and drain terminals of the transistor. The paper is organized as follows. In Sec. II we describe the NVNA-based setup (II.A), the criteria used for the selection of the excitation frequencies (II.B), the GaN FET characterization (II.C) and, finally, the separation procedure between conductive and displacement drain current components (II.D). The Charge-Controlled GaN FET modeling is addressed in Sec. III, in terms of gate (III.A) and drain (III.B) charge extraction as well as conductive drain current generator modeling (III.C). Finally, experimental validation is provided in Sec. IV, while Conclusions are drawn in Sec. V. II. NVNA-BASED TWO-TONE IDENTIFICATION

Fig. 3. NVNA-based measurement setup and on-wafer DUT.

real-time active load pull (RTALP) measurement technique [20] obtained by means of an LSNA. Such a method is very efficient to densely cover the 𝑣𝐺 , 𝑣𝐷 plane in a one single measurement. They use the acquired dataset to train an

The GaN-FET will be modeled throughout this work according to the schematic shown in Fig. 1Errore. L'origine riferimento non è stata trovata.. Although the main focus will be laying on the extraction of the gate and drain charge functions, a simplified yet complete GaN FET model will be provided and used for the experimental validation presented in Sec. IV. Apart from the purely-algebraic gate-source and gatedrain diodes shown in Errore. L'origine riferimento non è stata trovata., which are taken into account through canonical exponential analytical functions [4], the charge-controlled instantaneous intrinsic device currents can be described by adopting a charge-controlled formulation: 𝑑 𝑄𝐺 [𝑣𝐺 , 𝑣𝐷 , 𝜗, 𝑥] 𝑖𝐺 = 𝑑𝑡 (1) 𝑑 𝑄𝐷 [𝑣𝐺 , 𝑣𝐷 , 𝜗, 𝑥] 𝑖𝐷 = 𝐹𝐷 [𝑣𝐺 , 𝑣𝐷 , 𝜗, 𝑥] + 𝑑𝑡

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 where 𝜗 is the channel temperature and 𝑥 a variable accounting for the charge trapping state. As will be discussed in the following, the charge functions 𝑄𝐺 and 𝑄𝐷 can be retrieved by integration of the gate and drain displacement currents over the 𝑣𝐺 , 𝑣𝐷 plane. An efficient experiment to achieve a dense coverage of such a plane consists of exciting the DUT with two large-signal single-tone power waves at two different frequencies 𝑓𝐴 and 𝑓𝐵 in a single wideband measurement [14], [20]. The tone at frequency 𝑓𝐴 is applied at the gate terminal, while the tone at frequency 𝑓𝐵 is applied at the drain terminal. Because of the nonlinear response of the DUT, the voltages and currents at both ports will have, in general, frequency components at: 𝑛𝑓𝐴 + 𝑚𝑓𝐵 , with 𝑛, 𝑚 being harmonic indexes. The complex spectral components at each mixing frequency can be directly measured by NVNA instrumentation (see Fig. 2) at the extrinsic plane. Parasitic de-embedding allows then to obtain these quantities (namely, 𝑉̅𝐺𝑛,𝑚 , 𝑉̅𝐷𝑛,𝑚 , 𝐼𝐺̅ 𝑛,𝑚 , and 𝐼𝐷̅ 𝑛,𝑚 ) at the intrinsic plane. According to the Fourier series analysis, the intrinsic voltages and currents can be expressed as:

3

Fig. 4. Evaluation of 𝑓𝐾,𝑚𝑖𝑛 and ∆𝑓𝐾,𝑚𝑖𝑛 for the optimal search of tone frequency 𝑓𝐵 (with (M,N,R) = (10,10,20) and 𝑓𝐴 = 2 GHz). Selected 𝑓𝐵 = 2.740 GHz highlighted. Figure from Ref. [19].

𝑣𝐺 (𝑡) = ∑ 𝑉̅𝐺𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴+𝑚𝑓𝐵 )𝑡 𝑛,𝑚

𝑣𝐷 (𝑡) = ∑ 𝑉̅𝐷𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴+𝑚𝑓𝐵)𝑡 𝑛,𝑚

𝑖𝐺 (𝑡) = ∑ 𝐼𝐺̅ 𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴+𝑚𝑓𝐵)𝑡

(2)

𝑛,𝑚

𝑖𝐷 (𝑡) = ∑ 𝐼𝐷̅ 𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 +𝑚𝑓𝐵)𝑡 . 𝑛,𝑚

Considering that such an acquisition involves the excitation of a wideband spectrum and low-order intermodulation products, maximum care should be undertaken in the choice of the frequencies. Moreover, considering the dispersive effects of GaN, additional constraints on the excitations should be applied to obtain iso-thermal and iso-dynamic acquisitions. A. NVNA Setup The core of the deployed on-wafer measurement set-up is a Keysight PNA-X N5247A with the Nonlinear Vector Network Analyzer option Fig. 2 and Fig. 3). Such an instrument is capable of measuring incident and scattered power waves at the two ports of the DUT from 10 MHz up to 67 GHz on a discrete frequency grid set by the reference comb generator. Absolute amplitude and phase calibration has been performed at the probe tips plane. Since the incident gate and drain RF powers requested to sweep the full device characteristic (for instance, for the voltages values: −10 𝑉 < 𝑣𝐺 < 1 𝑉; 0 𝑉 < 𝑣𝐷 < 80 𝑉) are far higher than the PNA-X test port, wideband external couplers, together with external bias-tees, were used. The dc quantities are applied and measured by means of an Agilent Precision IV Analyzer (E5270B), while the baseplate temperature is controlled by a thermal chuck. Two additional bench RF power amplifiers (Mini-Circuits ZHL-5W-2G-S and Agilent 83020A) fed by the internal

Fig. 5. Mixing products frequency grid and corresponding order due to the two-tone excitation (𝑓𝐴 = 2 𝐺𝐻𝑧 (blue), 𝑓𝐵 = 2.740 𝐺𝐻𝑧 (red), M =10, N = 10). R limited to 10 in the plot for readability. Figure from Ref. [19].

PNA-X CW sources, are deployed to generate the necessary input power at both ports. All measurements have been acquired by setting an Intermediate Frequency (IF) filter bandwidth (BW) of 1 KHz. With this setting, a full spectrum acquisition of 220 frequency harmonics (as will be described in Sec. II.B) took approximately 3 seconds. If using a 1 Hz of IF-BW, the spectrum acquisition sweep takes, instead, around 3 minutes. B. Two-Tones Frequency Selection The excitations must be designed suitably in order to perform an iso-thermal (i.e., 𝜗 ≅ 𝜗0 ) and iso-dynamic (i.e., at constant charge trapping state: 𝑥 ≅ 𝑋0 ) acquisition of the GaN FET characteristics, still without exciting non-quasi-static effects. In order to select the best frequencies 𝑓𝐴 , 𝑓𝐵 of the two excitation tones, a preliminary search has been carried out. Let us indicate as 𝑁 and 𝑀 the maximum orders of the tones at 𝑓𝐴 and 𝑓𝐵 , respectively (i.e., |𝑛| ≤ 𝑁, and |𝑚| ≤ 𝑀), as 𝑅 the maximum mixing order (i.e., 𝑟 =̇ |𝑛| + |𝑚| ≤ 𝑅) and let 𝑓𝐾 (of the kind 𝑛𝑓𝐴 + 𝑚𝑓𝐵 ) be the k-th generated mixing frequency. These quantities should satisfy the following constraints [19], clearly differentiating this procedure from [20]:

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 a) all 𝑓𝐾 components should be measurable. Those that are not, they must involve a negligible contribution (i.e. they must correspond to high mixing orders); b) in order to obtain an iso-thermal and iso-dynamic characteristic, 𝑓𝐾,𝑚𝑖𝑛 = 𝑚𝑖𝑛(𝑓𝐾 ) must be higher than the upper cut-off frequency of dispersive effects for GaN (i.e., a few MHz [8]); c) the multiplying integration factor 1/𝑓𝐾 grows as 𝑓𝐾 →0,

Fig. 6. Characterization locus over the intrinsic gate and drain voltage domain. 𝑉𝐺𝑄 = −3.4 𝑉, 𝑉𝐷𝑄 = 30 𝑉, 𝐼𝐷 ≈ 80 mA. Figure from Ref. [19].

4

highly weighting low frequency current components. Thus, integration errors tend also to increase at low frequencies. For this reason, 𝑓𝐾,𝑚𝑖𝑛 should be maximized; d) in order to maximize the charge characterization accuracy, two mixing components should never fall too close in frequency. The minimum distance between two components ∆𝑓𝐾,𝑚𝑖𝑛 , should be maximized or at least higher than a threshold; e) frequencies where the GaN FET behaves non-quasi-static should correspond to very high mixing order, so to consider non-quasi-static effects negligible. The frequencies 𝑓𝐴 , 𝑓𝐵 of the two excitation tones and the maximum orders 𝑁, 𝑀, 𝑅 have been selected with the intent to satisfy the above criteria. The frequency of the first tone 𝑓𝐴 has been chosen equal to 2 GHz, this being a frequency high enough to well characterize gate and drain charge functions without involving non-quasi-quasi static effects. The three numbers 𝑁 = 10, 𝑀 = 10, 𝑅 = 20 have been chosen for a good compromise between spectrum extension and computational cost of the offline data elaboration for model extraction. Finally, the optimal frequency of the second tone 𝑓𝐵 has been selected by taking into account the resulting 𝑓𝐾,𝑚𝑖𝑛 and ∆𝑓𝐾,𝑚𝑖𝑛 . In particular, the optimal value for 𝑓𝐵 has been searched over the discrete subset: 𝑓𝐴 + ∆𝑓𝑠 , …, 𝑓𝐴 + 𝐾 ∙ ∆𝑓𝑠 ,…,𝑓𝐴 + 𝑓𝑠 with ∆𝑓𝑠 = 10 𝑀𝐻𝑧 and 𝑓𝑠 = 1 𝐺𝐻𝑧. This choice corresponds to the spacing of tones of the comb generator used as phase reference during the NVNA calibration. Values of 𝑓𝐾,𝑚𝑖𝑛 and ∆𝑓𝐾,𝑚𝑖𝑛 corresponding to each possible choice of 𝑓𝐵 within the subset are plotted in Fig. 4. By taking into account the explained criteria, the final choice 𝑓𝐵 = 2.740 𝐺𝐻𝑧 corresponds to 𝑓𝐾,𝑚𝑖𝑛 = 220 MHz and ∆𝑓𝐾,𝑚𝑖𝑛 = 80 MHz. The obtained mixing frequency grid is reported in Fig. 5 along with the order of each spectrum component. C. GaN FET Characterization

Fig. 7. Measured GaN FET intrinsic gate current 𝑖𝐺 (𝑡) corresponding to the locus of voltages shown in Fig. 6. Figure from Ref. [19].

The chosen DUT is a 8x125 m (1-mm) GaN-on-SiC FET by United Monolithic Semiconductor (UMS) with gate length L = 0.25 m. All measurements are acquired by setting a baseplate temperature 𝜗𝐵 (40°𝐶) and biasing the device for operation in AB-class with bias: 𝑉𝐺𝑄 = −3.4 𝑉, 𝑉𝐷𝑄 = 30 𝑉, (𝐼𝐷 ≈ 80 mA). In order to guarantee a steady state condition of thermal and trapping effects, the device is held biased and with RF applied for some minutes before the actual waveform acquisition, which only takes a few seconds. The locus 𝑣𝐺 (𝑡), 𝑣𝐷 (𝑡) covered in a single measurement with 17.8 dBm and 35.1 dBm of available source power at the gate and drain ports, respectively, is shown in Fig. 6, while the corresponding gate and drain currents are plotted in Fig. 7 and Fig. 8. D. Separation of Conductive and Displacement Current

Fig. 8. Measured GaN FET intrinsic drain current 𝑖𝐷 (𝑡) corresponding to the locus of voltages shown in Fig. 6.

Contrarily to the gate charge extraction [19], the extraction of the drain charge function 𝑄𝐷 first involves additional elaboration to isolate the displacement current. Having measured the 𝐼𝐷̅ 𝑛,𝑚 harmonic components at the mixing frequencies 𝑛𝑓𝐴 + 𝑚𝑓𝐵 , one could rely on the inverse Fourier transformation (2) for obtaining the drain current on gate and drain voltage loci, like the one shown in Fig. 6. However, in

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 order to achieve the knowledge of the drain current over the whole gate and drain voltage domain, one can preferably rely on the inverse Fourier transformation over an auxiliary twodimensional time domain (e.g., [21]). To this aim, let us consider the following two-dimensional inverse Fourier transform: 𝑁

𝑀

𝑖𝐷 (𝜏𝐴, 𝜏𝐵 ) = 𝑅𝑒 {∑ ∑ 𝐼𝐷̅ 𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴𝜏𝐴, +𝑚𝑓𝐵𝜏𝐵 ) } . (3) 𝑛=1 𝑚=1

Clearly, (3) coincides with the canonical inverse Fourier transform (2), when 𝜏𝐴 = 𝜏𝐵 = 𝑡. In addition, since (3) is periodic both with respect to 𝜏𝐴 (with period 𝑇𝐴 = 1⁄𝑓𝐴 ) and 𝜏𝐵 (with period 𝑇𝐵 = 1⁄𝑓𝐵 ), an arbitrarily dense discretization can be executed over the two time axes 𝜏𝐴 , 𝜏𝐵 , i.e.: 0, … , 𝜏𝐴,𝑘 , … , (𝐾 − 1) ∙ ∆𝜏𝐴 and: 0, … , 𝜏𝐵,𝑙 , … , (𝐿 − 1) ∙ ∆𝜏𝐵 , respectively, with: 𝜏𝐴,𝑘 = 𝑘 ∙ ∆𝜏𝐴 ; 𝑇𝐴 = 𝐾 ∙ ∆𝜏𝐴 and 𝜏𝐵,𝑙 = 𝑙 ∙ ∆𝜏𝐵 ; 𝑇𝐵 = 𝐿 ∙ ∆𝜏𝐵 . Thus, the discretized two-dimensional inverse Fourier transform becomes: 𝑁

𝑀

𝑖𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝑅𝑒 {∑ ∑ 𝐼𝐷̅ 𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴 +𝑚𝑓𝐵𝑙∆𝜏𝐵 ) }. (4) 𝑛=1 𝑚=1

5

𝑖𝐷 (𝑣𝐺 , 𝑣𝐷 ) = 𝐹𝐷 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] + +𝑔21 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙ (𝑣𝐺 − 𝑣𝐺,𝑖 ) + 𝑔22 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙ (𝑣𝐷 − 𝑣𝐷,𝑗 ) (6) 𝑑𝑣𝐺 𝑑𝑣𝐷 +𝐶21 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] + 𝐶22 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙ 𝑑𝑡 𝑑𝑡 where: 𝑔21 = 𝜕𝐹𝐷 ⁄𝜕𝑣𝐺 , 𝑔22 = 𝜕𝐹𝐷 ⁄𝜕𝑣𝐷 , 𝐶21 = 𝜕𝑄𝐷 ⁄𝜕𝑣𝐺 , 𝐶22 = 𝜕𝑄𝐷 ⁄𝜕𝑣𝐷 . The dependency on the channel temperature 𝜗 and on the trapping state variable x have been omitted in (6) for the sake of simplicity. It is worth noting that the gate and drain voltage derivatives in (6) can be easily obtained by direct derivation in the frequency domain: 𝑉̅ ′𝐺𝑛,𝑚 = 𝑗2𝜋(𝑛𝑓𝐴 + 𝑚𝑓𝐵 )𝑉̅𝐺𝑛,𝑚 𝑉̅ ′𝐷𝑛,𝑚 = 𝑗2𝜋(𝑛𝑓𝐴 + 𝑚𝑓𝐵 )𝑉̅𝐷𝑛,𝑚 ,

so that:

𝑁

(7)

𝑀

𝑑𝑣𝐺 (𝜏 , 𝜏 ) = ∑ ∑ 𝑉̅ ′𝐺𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴+𝑚𝑓𝐵 𝑙∆𝜏𝐵 ) 𝑑𝑡 𝐴,𝑘 𝐵,𝑙 𝑛=1 𝑚=1 𝑁 𝑀

𝑑𝑣𝐷 (𝜏 , 𝜏 ) = ∑ ∑ 𝑉̅ ′𝐷𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴 +𝑚𝑓𝐵𝑙∆𝜏𝐵 ) . 𝑑𝑡 𝐴,𝑘 𝐵,𝑙

(8)

𝑛=1 𝑚=1

Equivalently, the measured intrinsic gate and drain voltage spectra 𝑉̅𝐺𝑛,𝑚 , 𝑉̅𝐷𝑛,𝑚 , can also be used for mapping the instantaneous gate and drain voltages 𝑣𝐺 , 𝑣𝐷 over the auxiliary two-dimensional time domain 𝜏𝐴 , 𝜏𝐵 : 𝑁

𝑀

𝑣𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝑅𝑒 {∑ ∑ 𝑉̅𝐺𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴 +𝑚𝑓𝐵 𝑙∆𝜏𝐵 ) } 𝑛=1 𝑚=1 𝑁

𝑀

The linearized drain current relationship (6) presents five unknowns (𝐹𝐷 , 𝑔21 , 𝑔22 , 𝐶21 , 𝐶22 ) for each of the small areas (i, j). By indicating with 𝑃𝑖𝑗 the number of drain current points 𝑖𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) falling within the generic area (i, j), the five unknowns can be obtained by solving the following overdetermined linear system of equations:

(5)

𝑣𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝑅𝑒 {∑ ∑ 𝑉̅𝐷𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴 +𝑚𝑓𝐵𝑙∆𝜏𝐵 ) }. 𝑛=1 𝑚=1

Clearly, these are the gate and drain voltage samples corresponding to the drain current samples in (4). A sufficiently-large number of time intervals within each time period (K and L) along the axes 𝜏𝐴 , 𝜏𝐵 allows to sample the gate and drain voltage plane densely enough to obtain the drain current on any chosen voltage couple 𝑣𝐺 , 𝑣𝐷 ., Equivalently, this corresponds to obtain an arbitrarily high number of drain current samples in any given little area across the 𝑣𝐺 , 𝑣𝐷 plane, provided that this is covered by the characterization locus at given amplitudes of the gate and drain signal sources. In order to obtain the separation of the conductive and displacement drain current components, let us partition the 𝑣𝐺 , 𝑣𝐷 plane in small areas with dimensions ∆𝑣𝐺 , ∆𝑣𝐷 and let us indicate with 𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 the central point of the generic area identified by indexes (i, j). Provided that ∆𝑣𝐺 , ∆𝑣𝐷 are chosen small enough with respect to the GaN FET nonlinear characteristics, the drain current (1) can be linearized within this area around the central point 𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 as

(1)

(1)

1 𝑣𝐺 − 𝑣𝐺,𝑖

𝑖𝐷

⋮ (𝑃𝑖𝑗 ) [𝑖𝐷 ]

= ⋮ [

1

(1)

𝑣𝐷 − 𝑣𝐷,𝑖

⋮ (𝑃 ) 𝑣𝐺 𝑖𝑗

− 𝑣𝐺,𝑖

⋮ (𝑃 ) 𝑣𝐷 𝑖𝑗

− 𝑣𝐷,𝑖

(1) 𝐹𝐷 (1) 𝑑𝑣𝐺 𝑑𝑣𝐷 𝑔21 𝑑𝑡 𝑑𝑡 𝑔22 . (9) ⋮ ⋮ (𝑃𝑖𝑗 ) (𝑃𝑖𝑗 ) 𝐶21 𝑑𝑣𝐺 𝑑𝑣𝐷 𝑑𝑡 𝑑𝑡 ] [𝐶22 ]

Clearly, the number of discretized points K, L over each time period along the auxiliary time axes 𝜏𝐴 , 𝜏𝐵 must be adopted high enough in order to satisfy the condition 𝑃𝑖𝑗 > 5 in each area (i, j). It is worth noting that the smaller the dimensions ∆𝑣𝐺 , ∆𝑣𝐷 of each area are chosen, the higher will be the resolution of the displacement current over the 𝑣𝐺 , 𝑣𝐷 , plane at the cost of some extra computation effort. In any case, once the system (9) is solved, the separated conductive (𝑖𝐷,𝑐 ) and displacement (𝑖𝐷,𝑑 ) drain current components within the area can be written for each corresponding 𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 point of the auxiliary two-dimensional time domain, as:

𝑖𝐷,𝑐 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝐹𝐷[𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] + +𝑔21 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙ (𝑣𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) − 𝑣𝐺,𝑖 ) +𝑔22 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙ (𝑣𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) − 𝑣𝐷,𝑗 )

(10)

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786

6

TABLE I FOUR DIFFERENT MEASUREMENT DATASETS

Excitations

PAVS gate (dBm)

PAVS drain (dBm)

A B C D

8 13 17 18

17 27 34 36

𝑣̂𝐺 (negative) peak (V) -4.4 -5.6 -7.4 -8.0

𝑣̂𝐷 (positive) peak (V) 39.3 50.7 70.4 77.0

𝐾−1 𝐿−1

̅ 𝐼𝐷,𝑑 = 𝑛,𝑚 Fig. 9. Thin-plate spline approximation of the gate terminal charge (𝑄𝐺 ) identified on the basis of the four excitation powers A, B, C, and D (see Tab. 1).

2 ∑ ∑ 𝑖𝐷,𝑑 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 )𝑒 −𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴 +𝑚𝑓𝐵 𝑙∆𝜏𝐵 ) 𝐾𝐿

(12)

𝑘=0 𝑙=0

The drain charge function 𝑄𝐷 will be obtained by means of frequency domain integration of (12), as will be described in Section III.B. III. CHARGE-CONTROLLED GAN FET MODELING A. Gate Charge Function Extraction

Fig. 10. Number 𝑃𝑖𝑗 of drain current samples 𝑖𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) within each area (i, j) of the the 𝑣𝐺 , 𝑣𝐷 plane (Δ𝑣𝐺 = 0.1 V, Δ𝑣𝐷 = 1 V). Drain samples obtained by means of (4) on the basis of measured dataset D (described in Tab. 1) and by adopting K = L = 512.

Fig. 11. Conductive and displacement GaN FET intrinsic drain current components plotted over the gate and drain voltage locus 𝑣𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ), 𝑣𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) with K = L = 512. Identification from measured dataset D.

𝑖𝐷,𝑑 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝐶21 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙ +𝐶22 [𝑣𝐺,𝑖 , 𝑣𝐷,𝑗 ] ∙

𝑑𝑣𝐺 (𝜏 , 𝜏 ) + 𝑑𝑡 𝐴,𝑘 𝐵,𝑙 (11)

𝑑𝑣𝐷 (𝜏 , 𝜏 ) 𝑑𝑡 𝐴,𝑘 𝐵,𝑙

Finally, the displacement drain current (11) can be Fouriertransformed in frequency domain, by applying the direct twodimensional discrete Fourier transform:

Extraction of the gate charge is addressed first. In line of principle, the gate and drain charges can be considered as functions of the temperature 𝜗 and the charge trapping state 𝑥, as indicated in (1). Thus, different extractions have been carried out by repeating the integration of the displacement gate current by using four single-shot two-tone measurements (as described in Sec. II-C) at four different amplitudes of the gate and drain signals. These are indicated as A, B, C, D in Tab. I, where the available input power at the gate and drain sides are reported, along with the corresponding negative (gate) and positive (drain) voltage peaks. Although carried out by maintaining the baseplate temperature at the constant value 𝜗𝐵 = 40°𝐶, each measurement corresponds to different channel temperatures due to self-heating. In addition, charge trapping conditions change between one set and the others due to different gate and drain peak values reached during the dynamic operation [4]. What should be kept in mind, however, is that each singleshot acquisition corresponds to iso-dynamic and iso-thermal conditions. The gate charge function 𝑄𝐺 for each one of the four measurements can be directly obtained by means of a direct integration in the frequency domain of the measured spectra of the displacement current 𝑖𝐺 [19]. In fact, no forward or breakdown current was observed neither in the gate-source or in the gate-drain diodes in all the four excitation cases. By taking into account the 𝐼𝐺̅ 𝑛,𝑚 spectral components at each mixing product measured at the frequency 𝑛𝑓𝐴 + 𝑚𝑓𝐵 , we have: 𝑄̅𝐺𝑛,𝑚 =

𝐼𝐺̅ 𝑛,𝑚 𝑗2𝜋(𝑛𝑓𝐴 + 𝑚𝑓𝐵 )

,

(13)

which can be converted into the auxiliary two-dimensional time domain as:

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 𝑁

7

𝑀

𝑄𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝑅𝑒 {∑ ∑ 𝑄̅𝐺𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴+𝑚𝑓𝐵 𝑙∆𝜏𝐵 ) }.

(14)

𝑛=1 𝑚=1

and associated with the corresponding gate and drain voltages (5) for an appropriate identification of the 𝑄𝐺 (𝑣𝐺 , 𝑣𝐷 ) function. It is interesting to observe that: the charge samples (14) (and, equivalently, the charge samples in the onedimensional time domain) obtained from a coherent measurement dataset are found to lay over an almost twodimensional surface defined on the gate and drain voltage plane 𝑣𝐺 , 𝑣𝐷 [19]. Thus, the 𝑄𝐺 (𝑣𝐺 , 𝑣𝐷 ) function can be easily evaluated on a rectangular grid with, for instance, a thin-plate spline approximation, without introducing critical residual errors. Moreover, the four gate charge functions 𝑄𝐺 (𝑣𝐺 , 𝑣𝐷 ) extracted on the basis of the different datasets described in Tab. 1 are almost laying on the same surface over the 𝑣𝐺 , 𝑣𝐷 plane (see Fig. 9), suggesting that the dependence of the gate charge function 𝑄𝐺 on both the channel temperature 𝜗 and the charge trapping state x can be here practically neglected for this transistor.

Fig. 12. Drain charge 𝑄𝐷 obtained through (16) over the locus 𝑣𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ), 𝑣𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) with K = L = 512 (black dots). Approximation of 𝑄𝐷 through a thin-plate spline regular surface. Measurement dataset D (see Tab. 1).

B. Drain Charge Function Extraction In order to separate the conductive and displacement drain current components, the two-dimensional auxiliary time domain 𝜏𝐴 , 𝜏𝐵 is uniformly discretized by assuming K = L = 512 intervals within each time period 𝑇𝐴 = 1⁄𝑓𝐴 , 𝑇𝐵 = 1⁄𝑓𝐵 . Moreover, the gate and drain voltage domain was discretized into small rectangular areas with dimensions Δ𝑣𝐺 = 0.1 V, Δ𝑣𝐷 = 1 V. Then, the spectra of the drain current 𝐼𝐷̅ 𝑛,𝑚 and of the gate and drain voltages 𝑉̅𝐺𝑛,𝑚 , 𝑉̅𝐷𝑛,𝑚 , measured at each mixing product frequency 𝑛𝑓𝐴 + 𝑚𝑓𝐵 , are inverse Fourier transformed according to (4) and (5). The number 𝑃𝑖𝑗 of drain current samples 𝑖𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) falling into each elementary area (i, j) have been counted and plotted in Fig. 10. As it can be seen, the number of points tends to increase in the regions were the gate and drain voltages show minor variations in time, but never fall below some tens in each elementary area. This has been considered sufficient for a well-conditioned solution of the over-determined linear system (9), leading to the determination of the conductive (𝑖𝐷,𝑐 ) and displacement (𝑖𝐷,𝑑 ) drain current component separation within each elementary area of the gate and drain voltage domain according to (10), (11). Plots of the two current components are provided in Fig. 11 over the locus 𝑣𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ), 𝑣𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ). On the basis of the spectral components (12) of the ̅ displacement drain current 𝐼𝐷,𝑑 , a frequency-domain 𝑛,𝑚 integration is then performed in order to identify the drain charge function 𝑄𝐷 , first in the frequency domain: 𝑄̅𝐷𝑛,𝑚 =

̅ 𝐼𝐷,𝑑 𝑛,𝑚 𝑗2𝜋(𝑛𝑓𝐴 + 𝑚𝑓𝐵 )

,

and, finally in the two-dimensional auxiliary time domain:

(15)

Fig. 13. Drain charge (𝑄𝐷 ) identified on the basis of the four measured dataset A, B, C, and D (see Tab. 1). 𝑁

𝑀

𝑄𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) = 𝑅𝑒 {∑ ∑ 𝑄̅𝐷𝑛,𝑚 𝑒 𝑗2𝜋(𝑛𝑓𝐴 𝑘∆𝜏𝐴 +𝑚𝑓𝐵 𝑙∆𝜏𝐵 ) }.

(16)

𝑛=1 𝑚=1

The drain charge (16) obtained with the measured dataset D is plotted in Fig. 12 over the locus 𝑣𝐺 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ), 𝑣𝐷 (𝜏𝐴,𝑘 , 𝜏𝐵,𝑙 ) (black dots). As can be seen, the dots almost lay on a surface also in the drain case, although here some residual volume is appreciable. However, this seems reasonable due to some degree of uncertainty involved in the separation of the two current components. Also in this case, the evaluation of the drain charge function 𝑄𝐷 (𝑣𝐴 , 𝑣𝐵 ) on a rectangular grid is carried out with a thin-plate spline approximation of these data (shown in Fig. 12). The outlined procedure has been repeated for each one of four measured datasets (Tab. 1) and the obtained drain charge functions are reported in Fig. 13. As in the case of the gate, the four drain charge functions lay on almost the same surface indicating a negligible dependency of the drain charge from the channel temperature 𝜗 and the charge trapping state x for this transistor. C. Conductive Drain Current Generator GaN FET conductive drain current functions 𝑖𝐷,𝑐 (𝑣𝐺 , 𝑣𝐷 ) extracted from measurement data sets on the basis of (10) are shown in Fig. 14 and Fig. 15. As expected, some deviations

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786

8

In particular, the 𝐹𝐷 [𝑣𝐺 , 𝑣𝐷 , 𝜗, 𝑥] function in (1) is approximated here through an Equivalent-Gate-Voltage (EGV) approach, i.e.,: 𝑒𝑞 𝑖𝐷,𝑐 ≅ (1 + 𝛼𝜗𝑚 ∙ (𝜗 − 𝜗 ∗ )) ∙ 𝐹𝐷 [𝑣𝐺 , 𝑣𝐷 , 𝜗 ∗ , 𝑋̂] ,

(17)

with: 𝑒𝑞

𝑣𝐺 = 𝑣𝐺 + 𝛼𝜗𝑡 ∙ (𝜗 − 𝜗 ∗ ) + 𝛼𝑥 ∙ (𝑥 − 𝑋̂).

Fig. 14. GaN FET intrinsic drain conduction current identified from measured dataset D (Δ𝑣𝐺 =0.25 V, Δ𝑣𝐷 =2.5 V). Baseplate temperature equal to 40°C.

Fig. 15. GaN FET intrinsic drain conduction current identified from the four measured datasets shown in Tab. 1. Deviations are due to thermal and charge trapping state differences associated with the four experimental conditions.

are observed in the currents identified from the four available datasets, due to differences in channel temperature 𝜗 and charge trapping state x associated with the various excitation conditions (see Tab. 1). Unfortunately, extraction of iso-dynamic I/V curves over a sufficiently large portion of the gate and drain voltage plane from sinusoidal-excitation-based data is only feasible at large amplitudes of the signals. Moreover, when dealing with sinusoidal excitations at different amplitude levels, thermal self-heating and charge trappings tend to mix their effects leading to some degree of uncertainty in the separation of the observed drain current deviations due to the different phenomena. From this point of view, identifying conductive drain current models from pulsed characterization data [4] seems a more reliable way in the author’s opinion. However, in the context of this work where the main focus is on the gate and drain charge function extraction, a simplified model is adopted for the conductive drain current generator 𝑖𝐷,𝑐 , which is coherently extracted from the same NVNA-based two-tone measurements data. .

(18)

where 𝜗 ∗ and 𝑋̂ are particular values of the channel temperature and charge trapping state, assumed as references. In the specific case, 𝜗 ∗ and 𝑋̂ are assumed here as the channel temperature and charge trapping state associated with the operating conditions marked as D in Tab. 1. Coherently, 𝑟𝑒𝑓 the conductive drain function 𝑖𝐷,𝑐 (𝑣𝐺 , 𝑣𝐷 ) extracted from the dataset D is assumed as the reference I/V curve 𝐹𝐷 [𝑣𝐷 , 𝑣𝐷 , 𝜗 ∗ , 𝑋̂] used in (17). Three are the model parameters to be identified, namely 𝛼𝜗𝑚 , 𝛼𝜗𝑡 and 𝛼𝑥 . In particular, 𝛼𝜗𝑚 , 𝛼𝜗𝑡 describe the drain current deviations, associated to temperature-dependent carrier mobility and threshold voltage, observed in the conductive drain I/V curves at different baseplate temperatures. By assuming thermal operation above upper-cutoff (thus, 𝜗 = 𝜗𝐵 + 𝑅𝜗 ∙ 𝑃0 ), values 𝛼𝜗𝑚 = -2 mA/°C, 𝛼𝜗𝑡 = 1.5 mV/°C have been extracted on the basis of a thermal resistance around 14°C/W provided by the device manufacturer. As far as the 𝛼𝑥 model parameter and state deviations 𝑥 − 𝑋̂ in (18) is concerned, it is first observed that the state variable x cannot be directly measured, while variations of x with respect to a reference (e.g., 𝑋̂) can be evaluated in terms of I/V curve deviations. To this aim, we recall from Sec. II-B that the kind of two-tone sinusoidal excitation used in this work leads to operation above the upper cutoff frequency of dispersive phenomena. Thus, for any given two-tone characterization condition at fixed amplitude levels, the state x can be assumed as constant during operation with a value depending on combinations of the negative and positive peaks of the gate and drain voltages, namely 𝑣̂𝐺 , 𝑣̂𝐷 , i.e.,: 𝑥 ≅ 𝑋0 (𝑣̂𝐺 , 𝑣̂𝐷 ).

(19)

Different choices can be made for a quantitative evaluation of charge trapping variations on the electrical GaN FET characteristics. In our case, we choose of measuring the state deviations 𝑋0 (𝑣̂𝐺 , 𝑣̂𝐷 ) − 𝑋̂ associated with different two-tone excitation experiments in terms of the dimensionless ratio: 𝑋0 (𝑣̂𝐺 , 𝑣̂𝐷 ) − 𝑋̂ = =

𝐹𝐷 [𝑣̃𝐺 , 𝑣̃𝐷 , 𝜗 ∗ , 𝑋0 (𝑣̂𝐺 , 𝑣̂𝐷 )] − 𝐹𝐷 [𝑣̃𝐺 , 𝑣̃𝐷 , 𝜗 ∗ , 𝑋̂] . 𝐹𝐷 [𝑣̃𝐺 , 𝑣̃𝐷 , 𝜗 ∗ , 𝑋̂]

(20)

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 The voltages 𝑣̃𝐺 , 𝑣̃𝐷 in (20) describe a specific sensing point on the gate and drain voltage plane, where the conductive component of the drain current is evaluated. This sensing point can be, for instance, practically chosen within the portion of the saturation region of the GaN FET I/V curves covered through the two-tone sinusoidal excitation even at relatively low amplitude levels (somewhere near the typical class-AB/class-A bias region). In practice, (20) can be estimated from measured datasets by means of: 𝑟𝑒𝑓

𝑋0 − 𝑋̂ ≅

∗ (𝑣 𝑖𝐷,𝑐 ̃𝐺 , 𝑣̃𝐷 ) − 𝑖𝐷,𝑐 (𝑣̃𝐺 , 𝑣̃𝐷 ) 𝑟𝑒𝑓

𝑖𝐷,𝑐 (𝑣̃𝐺 , 𝑣̃𝐷 )

.

(21)

∗ (𝑣 where 𝑖𝐷,𝑐 ̃𝐺 , 𝑣̃𝐷 ) is the thermally-compensated conductive drain function (i.e., with applied compensation of the channel temperature difference 𝜗 − 𝜗 ∗ ) extracted from any dataset obtained under two-tone excitations at given peaks 𝑣̂𝐺 , 𝑣̂𝐷 of the gate and drain voltages. The charge trapping deviations 𝑋0 − 𝑋̂ estimated with the four two-tone excitations listed in Tab. 1 are plotted in Fig. 16 along with the plane obtained through best fitting procedures over the 𝑣̂𝐺 , 𝑣̂𝐷 domain. This plane actually describes the 𝑋0 (𝑣̂𝐺 , 𝑣̂𝐷 ) − 𝑋̂ deviations for any DUT excitation with peaks 𝑣̂𝐺 , 𝑣̂𝐷 . The 𝛼𝑥 model parameter can finally be extracted in order to obtain the best fit of the measured drain current deviations observed in Fig. 15. A value 𝛼𝑥 = −0.8 𝑉 has been adopted in this work.

Fig. 16. Charge trapping deviations 𝑋0 − 𝑋̂ estimated through (21) for the four excitations listed in Tab. 1. Plane obtained by means of least square approximation of the four points.

(a)

IV. EXPERIMENTAL VALIDATION The 1-mm GaN FET nonlinear model described in the previous Sections has been implemented into the Keysight ADS CAD tool for experimental validation. The reference conductive drain current (Fig. 14, and red solid line in Fig. 15) and the two gate and drain charge functions (red curves referred with D in Fig. 9 and Fig. 13, respectively) have been implemented in terms of Look-Up-Tables (LUT) and linearly interpolated. The model described by (1), (17), (18) has been implemented by means of a Symbolically Defined Device (SDD) and associated schematic equations. Diode-circuit-based peak extraction of the gate and drain voltages has been implemented and executed at run-time similarly to the approach followed in [4]. The obtained quasi-static model, along with the associated quasi-static procedure, has been validated by means of two different CW experiments at the frequency of 2.5 GHz and 5 GHz in a 50-Ω environment, at increasing input power levels (bias: 𝑉𝐺𝑄 = −3.4 𝑉, 𝑉𝐷𝑄 = 30 𝑉). These are meaningful tests for quasi-static model validation, since the GaN FET under test exhibits almost quasi-static behavior up to about 30 GHz [4], as it can be easily verified by examining the intrinsic device small signal parameters (according to the same criteria adopted in [22]). Detailed comparisons between model predictions and measurements are provided in terms of terminal currents loci versus the gate and drain voltages at 2.5 GHz (Fig. 17) and 5 GHz (Fig. 18). Time-domain gate and drain current waveforms are provided in Fig. 19 and 20. We

(b)

(c)

(d) Fig. 17. Measured (circles) and modeled (continuous line) GaN FET intrinsic current loci. Gate current is plotted versus gate (a) and drain (b) voltages. Drain current is plotted versus gate (c) and drain (d) voltages. CW excitation at 2.5 GHz. Available input power 𝑃𝑎𝑣𝑠 : -1 dBm (black), 4 dBm (light blue), 9 dBm (orange), 13 dBm (blue), 17 dBm (green), 19 dBm (red). Intrinsic harmonic loads: 𝑍𝐿,1 =48.6 Ω ∠177°; 𝑍𝐿,2 =45.9 Ω ∠-179°; 𝑍𝐿,3 =49.3 Ω ∠-172°.

9

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786

10

Should operation at much higher frequencies be considered, a well-validated quasi-static model can be a good starting point for the development of a non-quasi-static model (for instance, see the equivalent voltage approach described in [22]). V. CONCLUSION

(a)

(b)

An efficient nonlinear GaN FET model extraction from NVNA measurements has been demonstrated. Iso-thermal and iso-dynamic waveform acquisitions at on-wafer level is achieved by exciting the two DUT ports through single-tone sources at selected frequencies. A nearly full coverage of the gate and drain voltage domain is obtained in a single-shot measurement. Separation of the conductive and displacement drain current components is executed by means of a linearization of the DUT behavior on a dense discretization grid over the voltages domain, and by exploiting the interpolation capabilities of the bi-dimensional Fourier analysis. The method easily allows to assess the dependency on temperature and charge-trapping of the terminal charges and of the conduction current. While these dependencies have been found negligible on the terminal charges, the dependency on thermal and charge trapping state has been included in the conductive current equation through an equivalent-voltage approach. Experimental validation of the proposed model has demonstrated rather accurate predictive capabilities. ACKNOWLEDGMENT

(c)

The authors wish to thank D. Floriot, V. Di Giacomo Brunel, and C. Chang, all with United Monolithic Semiconductors, Villebon-sur-Yvette, France, for the supply of GaN devices and for helpful suggestions and discussions. REFERENCES

(d) Fig. 18. Measured (circles) and modeled (continuous line) GaN FET intrinsic current loci. Gate current is plotted versus gate (a) and drain (b) voltages. Drain current is plotted versus gate (c) and drain (d) voltages. CW excitation at 5 GHz. Available input power 𝑃𝑎𝑣𝑠 : -0.5 dBm (black), 4.5 dBm (orange), 9.5 dBm (blue), 14.5 dBm (green), 19.5 dBm (red). Intrinsic harmonic loads: 𝑍𝐿,1 =45.9 Ω ∠-179°; 𝑍𝐿,2 =54.0 Ω ∠179°; 𝑍𝐿,3 =57.6 Ω ∠-166°.

would like to point out that the results presented in Figs. 17-20 provide validation under operating conditions that are definitely different from those used for model extraction. In addition, we report in Figs. 21 and 22 a two-tone test at 2.5 GHz, with spacing Δ𝑓 =2.5 MHz. The overall agreement between measurements and modeling seems rather satisfying in consideration of the extremely reduced set of measurements used for model extraction.

[1] J. Xu et al., “Dynamic FET model – DynaFET - for GaN transistors from NVNA active source injection measurements,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2014. [2] G. Avolio et al., “A procedure for the extraction of a nonlinear microwave GaN FET model,” Int. J. of Numer. Model., 2016 [3] O. Jardel et al., “An electrothermal model for AlGaN/GaN power HEMTs including trapping effects to improve largesignal simulation results on high VSWR,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 12, pp. 2660-2669, Dec. 2007. [4] A. Santarelli et al., “GaN FET nonlinear modeling based on double pulse I/V characteristics,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 12, pp. 3262–3273, Dec. 2014. [5] D. E. Root, “Future device modeling trends,” IEEE Microw. Mag., vol. 13, no. 7, pp. 45–59, Nov.–Dec. 2012. [6] A. Jarndal and G. Kompa, “Large-signal model for AlGaN/GaN HEMTs accurately predicts trapping- and selfheating-induced dispersion and intermodulation distortion,” IEEE Trans. Electron Devices, vol. 54, no. 11, pp. 2830–2836, Nov. 2007. [7] I. Angelov et al., “On the large-signal modeling of High Power AlGaN/GaN HEMTs,” IEEE MTT-S Int. Microw. Symp. Dig., pp. 1-3, Jun. 2012. [8] O. Jardel et al., "Modeling of trap induced dispersion of large signal dynamic Characteristics of GaN HEMTs," IEEE MTT-S Int. Microw. Symp. Dig., pp. 1-4, Jun. 2013.

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 [9] A. Benvegnù et al., “On-Wafer Single-Pulse Thermal Load– Pull RF Characterization of Trapping Phenomena in AlGaN/GaN HEMTs,” IEEE Trans. Microw. Theory Techn., vol. 64, no. 3, pp. 767-775, Mar. 2016. [10] S. Khandewal, N. Goyal, and T. A. Fjeldly, “A Physics –Based Analytical Model for 2DEG Charge Density in AlGaN/GaN

[11]

[12] [13]

[14]

[15]

(a) [16]

[17]

11

HEMT devices,” IEEE Trans. Electron Devices, vol. 58, no. 10, pp 3622-3625, Oct. 2011. X. Cheng, M. Li, and Y. Wang, “Physics-Based Compact Model for AlGAN/GaN MODFETS with Close-Formed I-V and C-V Characteristics,” IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 2881-2887, Dec. 2009. D.G. Morgan, et al., “Full extraction of PHEMT state functions using time domain measurements”, IEEE MTT-S Int. Microw. Symp. Dig., pp. 823-826, May 2001. M. C. Curras-Francos, “Table-based nonlinear HEMT model extracted from time-domain large-signal measurements,” IEEE Trans. Microw. Theory Techn., vol.53, no.5, pp. 1593–1600, May 2005. Y. Ko et al., “Artificial neural network model of SOSMOSFETS based on dynamic large-signal measurements”, IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, pp. 491501, Mar. 2014. D. E. Root, “Nonlinear charge modeling for FET large-signal simulation and its importance for IP3 and ACPR in communication circuits,” Proc. IEEE Midwest Symp. on Circ. and Syst., vol. 2, pp. 768–772, Aug. 2001. G. Avolio et al., “Millimeter-wave FET nonlinear modelling based on the dynamic-bias measurement technique”, IEEE Trans. Microw. Theory Techn., vol. 62, no. 11, pp. 2526-2537, Nov. 2014. D. Schreurs et al., “Direct extraction of the non-linear model for two-port devices from vectorial non-linear network analyzer measurements,” Proc. Eur. Microw. Conf., pp. 921-926, Sept. 1997.

(b) Fig. 19. GaN FET intrinsic gate (a) and drain (b) current waveforms corresponding to CW validation at 2.5 GHz (same values as in Fig. 17)

Fig. 21. Intermodulation test under two-tone excitation. Fundamental output power and third-order intermodulation (IM3) product (dots – measure, lines – model prediction). 𝑍𝐿 = 50 Ω, 𝑓1 = 2.5 GHz, 𝑓2 = 2.5025 GHz (Δ𝑓 = 2.5 MHz). (a)

(b) Fig. 20. GaN FET intrinsic gate (a) and drain (b) current waveforms corresponding to CW validation at 5 GHz (same values as in Fig. 18).

Fig. 22. Gain and power-added efficiency (PAE) under twotone excitation (dots – measure, lines – model prediction); same conditions as in Fig. 21.

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 [18] P. Roblin, Nonlinear RF circuits and nonlinear vector network analyzers: interactive measurement and design techniques, Cambridge University Press, 2011. [19] D. Niessen et al., “Iso-thermal and Iso-dynamic Direct Charge Function Characterization of GaN FET with Single LargeSignal Measurement,” IEEE MTT-S Int. Microw. Symp. Dig., pp. 1-3, May 2016. [20] F. Verbeyst and M. Vanden Bossche, “Real-time and optimal PA characterization speeds up PA design”, in Proc. Eur. Microw. Conf , pp. 431-434, Oct. 2004. [21] A. Ushida et al., “Intermodulation analysis of nonlinear circuits using two-dimensional Fourier transformation,” Proc. Symp. Nonlin. Theory and Applications (NOLTA), pp.282-285, 2005. [22] A. Santarelli, et al., “A nonquasi-static empirical model of electron devices”, IEEE Trans. Microw. Theory Techn., vol. 54, no. 12, pp. 4021-4031, Dec. 2006.

Daniel Niessen (S’05–M’13) received the M.S. degree (with honors) in telecommunication engineering and Ph.D. degree in electronics, computer science and telecommunications from the University of Bologna, Bologna, Italy, in 2009 and 2013, respectively. From June to December 2012, he was a Visiting Researcher with the Chalmers University of Technology, Göteborg, Sweden. Since 2013, he has been a Research Fellow with the Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna. His research interests include nonlinear characterization and modeling of electron devices and systems (with a special focus on GaN technology), microwave circuit design, and linearization techniques. Gian Piero Gibiino (S’13) received the dual Ph.D. degree in electronic engineering from University of Bologna, Bologna, Italy, and from Katholieke Universiteit Leuven, Leuven, Belgium, in 2016. In 2016, he was a Visiting Researcher with Keysight Technologies, Aalborg, Denmark. Since 2012, he has been with the Department of Electrical Engineering “G. Marconi”, University of Bologna, where he is currently a Research Fellow. His research interests include electron devices and RF power amplifiers modeling, nonlinear microwave measurements, and linearization techniques. Rafael Cignani (M’13) was born in Ravenna, Italy, in 1975. He received the Laurea degree in Telecommunications Engineering from the University of Bologna, Bologna, Italy, in 2000 and the Ph.D. degree in Information Engineering from the University of Ferrara, Ferrara, Italy, in 2004. During his doctoral studies, he collaborated with the Department of Electronics, Computer Science and Systems (DEIS), University of Bologna. He is currently a Graduated Technician with the Department of Electrical, Electronic, and Information Engineering (DEI), University of

12

Bologna. His research activity is mainly oriented to MMIC design and nonlinear circuit modeling and design techniques. Alberto Santarelli (M’97) received the Laurea degree (cum laude) in electronic engineering in 1991 and the Ph.D. in Electronics and Computer Science from the University of Bologna, Italy in 1996. He was a Research Assistant from 1996 to 2001 with the Research Centre for Computer Science and Communication Systems of the Italian National Research Council (IEIITCNR) in Bologna. In 2001, he joined the Department of Electrical, Electronic and Information Engineering (DEI) “Guglielmo Marconi”, University of Bologna, where he currently is an Associate Professor. During his academic career he has been a Lecturer of Applied Electronics, Industrial Electronics, and Electronics for Communications. His main research interests are related to the nonlinear characterization and modeling of electron devices and to the nonlinear microwave circuit design. Prof. Santarelli is a member of the European Microwave Association (EuMA) and the Italian Association of Electrical, Electronics, Automation, Information and Communication Technology (AEIT). Dominique M. M.-P. Schreurs (S'90– M'97–SM'02–F'12) received the M.Sc. degree in electronic engineering and the Ph.D. degree from Katholieke Universiteit Leuven, Leuven, Belgium. She is currently a Full Professor with the Katholieke Universiteit Leuven. She has been a Visiting Scientist with Agilent Technologies, Santa Rosa, CA, USA, ETH Zürich, Zürich, Switzerland, and the National Institute of Standards and Technology, Boulder, CO, USA. Her current research interests include the (non)linear characterization and modeling of active microwave devices, and (non)linear circuit design for telecommunications and biomedical applications. Dr. Schreurs serves on the AdCom of the IEEE MTT Society. She also serves as an Editor-in-Chief of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES and as the Vice-President on the Executive Committee of the ARFTG organization. She was the General Chair of the 2007 and 2012 Spring ARFTG Conference and the Co-Chair of the European Microwave Conference in 2008. She was an MTT-S Distinguished Microwave Lecturer. Fabio Filicori was born in Imola, Italy, in 1949. He received the M.S. degree in electronic engineering from the University of Bologna, Bologna, Italy, in 1974. In 1974, he joined the Department of Electronics, Computer Science and Systems, University of Bologna, initially as Research Assistant, and then becoming an Associate Professor of applied electronics. In 1990, he became a Full Professor of applied electronics with the University of Perugia. In 1991, he joined the Faculty of Engineering, University of Ferrara, where he

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TMTT.2016.2623786 was a Full Professor responsible for the degree course in electronic engineering. He is currently a Full Professor of electronics with the Faculty of Engineering, University of Bologna. During his academic career, he has held courses on computer-aided circuit design, electron devices and circuits, and power electronics. His main research activities are in the areas of computer-aided design (CAD) techniques for nonlinear microwave circuits, electron device nonlinear modeling, sampling instrumentation, and power electronics.

13