CMOS Ring Oscillator with Quadrature Outputs and 100 MHz to 3.5 ...

29th European Solid-State Circuits Conference 2003 (ESSCIRC 2003), Estoril, Portugal, Sept. 16-18, 2003

CMOS Ring Oscillator with Quadrature Outputs and 100 MHz to 3.5 GHz Tuning Range Markus Grözing, Bernd Philipp, Manfred Berroth Institute of Electrical and Optical Communication Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany, Email: [email protected] Abstract A 100 MHz to 3.5 GHz four-stage CMOS ring oscillator with quadrature outputs and oscillator core current consumption roughly proportional to operating frequency is presented. A novel oscillator topology consisting of a chain of four static single-ended CMOS inverters, four additional feedforward inverters and frequency control by steering the total oscillator core current is proposed. The circuit is implemented in a 0.18 µm standard CMOS technology. Oscillator core current consumption is 90 µA at 100 MHz and 9 mA at 3.5 GHz with a 1.8 V supply. Measured phase noise at 4 MHz offset is -114 dBc/Hz at 100 MHz and -106 dBc/Hz at 3.5 GHz oscillation frequency. Quadrature error is better than 3.5° over the 100 MHz to 3 GHz frequency range. 1.

Introduction

Today’s communication standards use a variety of data rates in serial links and many different carrier frequencies in wireless transmission. Moreover, frequency scaling in microprocessors gets important for power aware systems [1]. Therefore, the demand for oscillators operating over a broad frequency range is increasing. Moreover, it is desirable that the current consumption of the oscillator scales with frequency. Low computing power or data rate in a power-saving low-frequency mode of a system should require lower current consumption than the maximum performance mode at high operating frequency. If a frequency source with a programmable divider is used, the oscillator is always operated at fast clock rate and thus high power. An oscillator with broad-band tuning range would offer reduced circuit complexity and additional power savings. Besides the tuning range and power consumption issues, oscillator quadrature outputs are becoming important for image rejection receivers, half-rate clock recoveries and multi-phase processor clocks. Due to the reasons given above, this work aims at developing an oscillator concept that provides a large frequency tuning range, quadrature outputs and current consumption decreasing with lower oscillation frequency without sacrificing phase noise performance. 2.

Quadrature Ring Oscillators

The most basic CMOS ring oscillator employs an odd number of static single-ended inverters as delay cells

(Fig. 1). The transition travelling around the ring has to pass through each inverter twice to arrive at the initial state. Therefore, the oscillation frequency is

f osz =

1 1 . = 2 τ Chain 2 N τ Inverter

Unfortunately, quadrature outputs require a ring with an even number of stages, which has a stable, static operating point (also called “latch-up”) and does not oscillate. There are two methods to solve this problem. The first is true differential signalling by using currentmode logic (CML) delay cells with a tail current source. The second is to add feedforward inverters between nodes with opposite-phase signals. UDD

1

L

H

1

0°

USS Figure 1.

↓L

120°

1 1 1

Figure 2.

1

Static CMOS inverter delay cell (left) and 3-stage single-ended ring oscillator (right).

1 1

240°

H

1

1 1

Quadrature four-stage ring oscillator concept employing feedforward paths.

The CML tail current source offers common mode rejection and forces the differential signals of an N-stage differential oscillator (that has 2N stages if seen as single-ended system) into opposite phase. Latch-up is prevented. For a large frequency range, delay interpolating techniques [2,3] or advanced load circuits and self-biased techniques [4] are necessary. But CML delay cells draw a constant bias current and energy is wasted during the time when no transition takes place. Moreover, signal swing is limited and phase noise performance normalised to power consumption is suboptimal. Ring oscillators with static, single-ended CMOS inverters offer large signal swings. Current consumption is lower because it is limited to the switching time interval. Therefore, the theoretical limit of the phase

29th European Solid-State Circuits Conference 2003 (ESSCIRC 2003), Estoril, Portugal, Sept. 16-18, 2003 UDD

UDD

UDD

UDD

UPMOS

UPMOS

URF_IN

a

b

c

URF_OUT USS

UNMOS USS

Figure 3.

UDD'

Figure 5.

UNMOS USS

USS

U 2,0 V

CMOS inverter current steering for falling (left), rising (middle) and both (right) edges. URF_270° UDD

URF_0°

UPMOS

1,0 V 0V

Icore

92 ns

Figure 6.

USS'

UNMOS

Icore

USS

URF_180°

Core output signal (line, fig. 5 a) and driver’s nd 2 inverter output signal (dash, fig. 5 c).

1 τChain

=

1 Nτ Inverter

.

As there is a rising and a falling transition at any time, the single-ended quadrature ring oscillator draws a nearly constant supply current and minimises switching noise on the supply lines. Frequency Control

Current consumption in static CMOS inverters is mainly due to charging and discharging the node capacitances. The lower the current, the longer the transition time. Therefore, frequency control can be achieved by steering or programming the current through the individual inverters stages. It is applied to one [7] or to all [8] inverters for the falling, the rising or both edges (Fig. 3 ). In [9], a feedforward quadrature oscillator with current steering separately applied to pairs of the main inverters only is proposed. No current steering is applied to the

UPMOS

IFREQ

Total oscillator core current steering.

f osz =

UDD

URF_90°

noise figure of merit is better for full-swing single-ended ring oscillators than for CML ring oscillators [5]. To avoid latch-up in an even-numbered static CMOS inverter ring, additional circuitry has to be added. In [6], a method to increase the operating frequency of ring oscillators with an odd number of delay cells by creating feedforward paths is presented. In fig. 2, the concept of adding feedforwad paths to a ring with an even number of stages is shown. Feedforward inverters are added to a ring of four main inverters between nodes with opposite phases. Therefore, a pair of them can act as a negative-Gm cell or as a regenerative circuit [7], that forces the two signals involved to opposite levels. The feedforward inverters take over the job that is done by the tail current source in a CML oscillator. There is a threshold value for the strength of the feedforward inverters relative to the strength of the main inverters to sustain a stable oscillation. In contrast to a ring with an odd number of inverters, now two transitions are travelling through the ring. Therefore, the oscillation frequency is now given by

t

94 ns

UDD

Figure 4.

3.

Inverter chain driver.

UREF

UREF Uavg

USS

USS

Figure 7.

Ireg

URF_0° URF_90° URF_180° URF_270°

UNMOS

Switching threshold voltage generator (right) and average output voltage regulator (left).

feedforward inverters. With this approach, the feedforward inverter strength relative to the main inverter strength increases for lower frequencies. At lower frequencies, this concept causes the signal shape to degenerate and the main part of the supply current is wasted as shunt current that flows directly from UDD to USS without charging or discharging the node capacitances. As a result, current consumption does not decrease at lower frequencies and phase noise increases. In our new approach we propose steering of the total quadrature oscillator core current Icore. This is done with a PMOS current source connected to the positive supply UDD and an NMOS current sink connected to the negative supply USS (Fig. 4). The core current is controlled by applying appropriate voltages UPMOS and UNMOS to the gates of the current steering transistors. The oscillator core inverter supplies are connected to the internal supplies UDD’ and USS’. With this approach, the optimum strength ratio between main and feedforward inverters is maintained at any core current. As a result, current consumption decreases with lower frequency and signal shape and phase noise performance are relatively constant over the operating frequency range. The reason is that the oscillator core current is mainly consumed for charging and discharging the internal node capacitance at any operating frequency. Moreover, the current source transistors offer supply rejection and attenuate the remaining switching noise. 4.

Duty Cycle Control

When properly dimensioned, the four oscillator core outputs provide sinusoidal signals. According to the requirements for the signal waveform, the signals are either directly applied to the loads or drivers are connected between the oscillator and the load circuits. In

29th European Solid-State Circuits Conference 2003 (ESSCIRC 2003), Estoril, Portugal, Sept. 16-18, 2003 our prototype circuit, three-stage static CMOS inverter chains (Fig. 5) are added to provide a limiting function and the driving capability for the 50 Ω measurement equipment. The inverter chains convert the signal of the core to a square wave signal (Fig. 6). The duty cycle requirement for this signal is usually 50 %. The correct duty cycle is only ensured, if the core signal average value Uavg (average of URF_0°, URF_90°, URF_180° and URF_270°) is equal to the switching threshold of the drivers. As the average value depends on the imperfect matching of the PMOS- and NMOS current sources, a regulator circuit is added to provide broad-band duty cycle control (Fig. 7 right). The control current IFREQ is converted to the control voltage UNMOS with a diode connected transistor. The regulator circuit compares the average output voltage Uavg with a reference voltage UREF and adjusts UPMOS to minimise the deviation between UREF and Uavg. The voltage UREF can be derived from an input-output shorted inverter (Fig 7 left) or from a voltage divider. As the voltage divider for Uavg loads the oscillator core, the oscillation vanishes for low oscillator core current at about 100 MHz. Simulations indicate that the minimum oscillation frequency can be as low as 1 MHz and the duty cycle is significantly enhanced, if the voltage Uavg is derived from intermediate signals of the drivers (Fig. 5 b, c) instead of directly from the core signals (Fig. 5 a, realised in prototype circuit). 5.

Experimental and Simulation Results

Simulations were done using SpectreRF. The measurements were made on an on-wafer probe station. Table 1 shows a phase noise and tuning range comparison of CMOS ring oscillators. Table 2 summarises the measurement and simulation results of this work. Fig. 8 shows the measured oscillation frequency versus the control current IFREQ. The frequency increases roughly proportional to IFREQ and saturates at 3.5 GHz. The simulated current consumption of the oscillator core and the regulator circuit versus oscillation frequency are shown in fig. 9. The currents are roughly proportional to the operation speed. Fig. 10 shows a photograph of the prototype circuit. Phase noise of the free running oscillator was estimated using a Anritsu MS 2668C spectrum analyser. Noise power was measured at 10 kHz resolution bandwidth. To avoid averaging of the carrier power due to the fluctuating centre frequency, it was measured using 3 MHz resolution bandwidth [10]. Phase noise at 4 MHz offset frequency is -106 dBc/Hz at 3.5 GHz and -114 dBc/Hz at 100 MHz oscillation frequency. For a phase noise figure of merit (FOM), the frequency offset has to be normalized to oscillation frequency, and DC power to a constant value. Assuming a 1/f 2-slope of the noise spectrum the following relation is reasonable [11]:   ∆f  2 I U   core DD  FOM = L measured + 10 log     f osz  1 mW   . As the noise spectrum in deep-sub-µm CMOS ring oscillators is dominated by 1/f-noise (resulting in a

1/f 3-slope in the spectrum) for small offset frequencies, the phase noise FOM is calculated for 4 MHz offset frequency. The FOM is -153 dBc/Hz at 3.5 GHz, -155 dBc/Hz at 762 MHz and -150 dBc/Hz at 100 MHz oscillation frequency and deviates ± 3 dB over the operating frequency range. Time domain measurements up to 3 GHz were done using a HP 54750 digitising oscilloscope. Figure 11 shows the 0°- and 90°-driver’s output waveforms at 250 MHz and 2.5 GHz. The duty cycle is 54 % ± 1% for oscillation frequencies down to 300 MHz. The duty cycle error is due to asymmetric core signal waveform in the prototype circuit. The quadrature error was estimated measuring the time difference between the 0°- and 90°- rising edges. The electrical length difference of the 0°- and 90°- measurement paths was estimated using the TDR function of the oscilloscope. The quadrature error is better than 3.5° in the 100 MHz to 3 GHz frequency range. 6.

Conclusion

A novel CMOS quadrature ring oscillator topology with frequency control by overall current steering is proposed. The prototype circuit demonstrates a maximum frequency of 3.5 GHz and large frequency tuning range down to 100 MHz. Quadrature error is smaller than 3.5° over the 100 MHz to 3 GHz range. Power consumption of the oscillator core decreases roughly proportional with decreasing operating frequency. This combination of properties is unique and could ease the design of broadband quadrature splitters, multi-rate clock-recovery circuits and power conscious frequency-scalable clock generators. 7.

References

[1] K.J. Nowka et al: “A 32-bit PowerPC System-on-a-Chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling”, JSSC, vol. 37, no. 11, pp. 1441-1447, Nov. 2002. [2] S. B. Anand, B. Razavi: “A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data”,JSSC, vol. 36, no. 3, pp. 432-439, Mar. 2001. [3] J. Savoj, B. Razavi: “A 10 Gb/s CMOS Clock and Data Recovery Circuit with Half-Rate Linear Phase Detector”, JSSC, vol. 36, no. 5, pp. 761-768, May 2001. [4] J. G. Maneatis: “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, JSSC, vol. 31, no. 11, pp. 1723-1732, Nov.1996. [5] A. Hajimiri, S. Limotyrakis, T. H. Lee: “Jitter and Phase Noise in Ring Oscillators”, JSSC, vol. 34, no. 6, pp. 790-804, June 1999. [6] L. Sun, T. A. Kwasniewski: “A 1.25 GHz 0.35-µm Monolithic CMOS PLL Based on a Multiphase Ring Oscillator”, JSSC, vol. 36, no. 6, pp. 910-916, June 2001. [7] M. Thamsirianunt, T. A. Kwasniewski: “CMOS VCO’s for PLL Frequency Synthesis in GHz Digital Mobile Radio Communic.”, JSSC, vol. 32, no. 10, pp. 1511-1524, Oct. 1997. [8] O. Chen, R. Sheen: “A Power-Efficient Wide-Range Phase-Locked Loop”, JSSC, vol. 37, no. 1, pp. 51-61, Jan. 2002. [9] L. Dai, R. Harjani: “A low-phase-noise CMOS ring oscillator with differential control and quadrature outputs”, 14th Annual IEEE Int. ASIC/SOC Conf. Proc., pp. 134-138, Sept. 2001. [10] B. Razavi: “A Study of Phase Noise in CMOS Oscillators”, JSSC, vol. 31, no. 3, pp. 331-343, Mar. 1996. [11] J.-O. Plouchart et al: “A fully-monolithic SiGe differential voltage-controlled oscillator for 5 GHz wireless applications”, 2000 RFIC) Symposium Diges., pp. 57-60, June 2000. [12] C. Park, B. Kim: “ A Low-Noise, 900-MHz VCO in 0.6 µm CMOS”, JSSC, vol. 34, no. 5, pp. 586-591, May 1999.

29th European Solid-State Circuits Conference 2003 (ESSCIRC 2003), Estoril, Portugal, Sept. 16-18, 2003 Lmin [µm]

UDD [V]

oscillator concept

frequency control: steer / program …

fosz [GHz]

∆f [MHz]

L(∆f) [dBc/Hz]

FOM [dBc/Hz]

fmax [GHz]

f max f min

ref

1,20 0,60 0,50 0,50 0,50 0,35 0,35 0,35 0,25 0,25 0,18

5,0 3,0 3,0 3,0 3,3 3,3 3,3 1,8 2,5 2,5 2,5

3-stage SE 4-stage diff. neg-Gm 3-stage diff. CML Relaxation, diff. n-stage diff, CML 2-stage diff, neg-Gm 4-stage CML, FFP 3-stage SE 19-stage SE 4-stage diff. CML 3-stage diff. CML

1-stage edge current neg-Gm bias voltage CML stage current bias current CML stage current neg-Gm current stage curr. interpolation number parallel stages capacitive load delay interpolation

4-stage SE, FFP

overall core current

-83 -117 -109 -102 -117 -112 -99 -106 -111

-154 -165 -158 -151 -158 -164 -154 -153 -155

2.9 1.6 > 105 1.9 10 ~ 1.3 1.6

1,8

0.1 0.6 5.0 5.0 1.0 1.0 1.0 4.0 4.0

0.93 1.20 2.20 0.92 0.55 0.97 1.65 1.02 1.33 5.43 6.95

0,18

0.93 0.90 2.20 0.92 0.97 1.33 5.43 3.52 0.76

3.52

35

[7] [12] [10] [10] [4] [9] [6] [8] [5] [5] [3] this work

Table 1. Comparison of CMOS ring oscillators (SE: single-ended, CML: current mode logic, FFP: feedforward path). contr. curr. *

osc.. freq. *

core curr. **

PN @ 4 MHz *

FOM@ 4 MHz */**

duty cycle *

quad. error *

IFREQ

fosz

Icore

L

FOM

A

MHz

mA

dBc/Hz

dBc/Hz

%

°

7.5 µ 10 µ 30 µ 100 µ 300 µ 1m 3m 10 m

100 125 301 762 1639 3006 3385 3516

0.09 0.11 0.27 0.80 2.10 6.38 7.95 8.71

-114.3 -114.4 -113.0 -111.3 -107.8 -104.3 -106.0 -106.3

-150.0 -151.2 -153.6 -155.3 -154.3 -151.2 -153.0 -153.2

59.7 57.5 54.3 53.8 53.5 54.8 -

-3.22 -2.07 0.93 -1.02 -0.54 -3.21 -

Figure 10 Chip photograph.

Table 2. Measurement (*) and simulation (**) results.

frequency fosz [MHz]

10000

1000

100 1.00E-05

Figure 8.

1.00E-04 1.00E-03 control current IFREQ [A]

1.00E-02

Frequency tuning by control current.

1.0E-02

current [A]

1.0E-03 1.0E-04 1.0E-05 1.0E-06

100

1000 frequency fosz [MHz]

Figure 9. Core current Icore (line) and regulator current Ireg (dash) versus oscillation frequency.

10000

Figure 11. 0° and 90° free running output waveform at 245 MHz (top) and 2.5 GHz (bottom). Signals are DC-blocked and attenuated by 10 dB. Resolution: 75 mV/div.