Computer Arithmetic andVerilogHDL Fundamentals

Computer Arithmetic andVerilogHDL Fundamentals

Joseph Cavanagh Santa Clara University California, USA

( r eC) CRC Press vf J ^"*"—"^

TayiorS«. Francis Group Boca Raton London New York

CRC Press is an imprint of the Taylor & Francis Group, an tnforma business

CONTENTS Preface

xv

Chapter 1

Number Systems and Number Representations 1.1

1.2

1.3

Chapter 2

1

Number Systems 1.1.1 Binary Number System 1.1.2 Octal Number System 1.1.3 Decimal Number System Number Representations 1.2.1 Sign Magnitude 1.2.2 Diminished-Radix Complement 1.2.3 Radix Complement Problems

1 4 6 8 12 13 15 18 22

Logic Design Fundamentals

25

Boolean Algebra Minimization Techniques 2.2.1 Algebraic Minimization 2.2.2 Karnaugh Maps 2.2.3 Quine-McCluskey Algorithm Combinational Logic 2.3.1 Multiplexers 2.3.2 Decoders 2.3.3 Encoders 2.3.4 Comparators Sequential Logic 2.4.1 Counters 2.4.2 Moore Machines 2.4.3 Mealy Machines Problems

25 32 32 33 39 44 47 53 56 58 60 62 71 78 84

Introduction to Verilog HDL

93

Built-in Primitives User-Defined Primitives Dataflow Modeling 3.3.1 Continuous Assignment Behavioral Modeling 3.4.1 Initial Statement

94 108 118 118 129 129

•

2.1 2.2

2.3

2.4

2.5

Chapter 3 3.1 3.2 3.3 3.4

viii

Contents

3.5

3.6

Chapter 4

3.4.2 Always Statement 3.4.3 Intrastatement Delay 3.4.4 Interstatement Delay 3.4.5 Blocking Assignments 3.4.6 Nonblocking Assignments 3.4.7 Conditional Statements 3.4.8 Case Statement 3.4.9 Loop Statements Structural Modeling 3.5.1 Module Instantiation 3.5.2 Design Examples Problems

Fixed-Point Addition

4.1 4.2 4.3

4.4 4.5 4.6 4.7

Chapter 5

Ripple-Carry Addition Carry Lookahead Addition Carry-Save Addition 4.3.1 Multiple-Bit Addition 4.3.2 Multiple-Operand Addition Memory-Based Addition Carry-Select Addition Serial Addition Problems

Fixed-Point Subtraction 5.1 5.2 5.3 5.4 5.5

Chapter 6

Twos Complement Subtraction Ripple-Carry Subtraction Carry Lookahead Addition/Subtraction Behavioral Addition/Subtraction Problems

Fixed-Point Multiplication 6.1

6.2 6.3

Sequential Add-Shift Multiplication 6.1.1 Sequential Add-Shift Multiplication Hardware Algorithm 6.1.2 Sequential Add-Shift Multiplication — Version 1 6.1.3 Sequential Add-Shift Multiplication — Version 2 Booth Algorithm Multiplication Bit-Pair Recoding Multiplication

129 133 133 133 136 138 141 150 154 154 155 179

183 184 191 201 201 206 212 216 227 234

237 238 243 250 267 271

275 276 278 282 285 289 304

Contents

6.4 6.5 6.6 6.7 6.8

Chapter 7

Array Multiplication Table Lookup Multiplication Memory-Based Multiplication Multiple-Operand Multiplication Problems

Fixed-Point Division 7.1

7.2 7.3

7.4 7.5 7.6

Chapter 8

Sequential Shift-Add/Subtract Restoring Division 7.1.1 Restoring Division — Version 1 7.1.2 Restoring Division — Version 2 Sequential Shift-Add/Subtract Nonrestormg Division SRT Division 7.3.1 SRT Division Using Table Lookup 7.3.2 SRT Division Using the Case Statement Multiplicative Division Array Division Problems

Decimal Addition 8.1 8.2 8.3 8.4 8.5

Chapter 9

Addition with Sum Correction Addition Using Multiplexers Addition with Memory-Based Correction Addition with Biased Augend Problems

Decimal Subtraction 9.1 9.2 9.3 9.4

Chapter 10 10.1 10.2 10.3 10.4

ix

318 329 339 344 353

359 360 362 368 374 382 393 397 402 408 423

427 427 437 444 454 460

463

Subtraction Examples 464 Two-Decade Addition/Subtraction Unit for A+B and A-B ... 467 Two-Decade Addition/Subtraction Unit for A+B, A-B, andB-A 481 Problems 491

Decimal Multiplication Binary-to-BCD Conversion Multiplication Using Behavioral Modeling Multiplication Using Structural Modeling Multiplication Using Memory

493 493 495 498 510

x

Contents

10.5 10.6

Chapter 11 11.1 11.2 11.3 11.4

Chapter 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7

Chapter 13 13.1 13.2 13.3

13.4

Chapter 14 14.1 14.2 14.3 14.4

14.5

Multiplication Using Table Lookup Problems

Decimal Division Restoring Division — Version 1 Restoring Division — Version 2 Division Using Table Lookup Problems

Floating-Point Addition Floating-Point Format Biased Exponents Floating-Point Addition Overflow and Underflow General Floating-Point Organization Verilog HDL Implementation Problems

Floating-Point Subtraction Numerical Examples Flowcharts Verilog HDL Implementations 13.3.1 True Addition 13.3.2 True Subtraction — Version 1 13.3.3 True Subtraction — Version 2 13.3.4 True Subtraction — Version 3 13.3.5 True Subtraction — Version 4 Problems

Floating-Point Multiplication Double Bias Flowcharts Numerical Examples Verilog HDL Implementations 14.4.1 Floating-Point Multiplication — Version 1 14.4.2 Floating-Point Multiplication — Version 2 Problems

524 528

529 529 538 545 550

551 552 554 557 560 561 564 569

571 573 581 584 584 589 593 598 603 608

611 613 614 616 618 618 624 631

Contents

Chapter 15 15.1 15.2 15.3 15.4 15.5

Chapter 16 16.1

16.2 16.3

16.4

Chapter 17 17.1

17.2 17.3 17.4 17.5

17.6

17.7 17.8

xi

Floating-Point Division

633

Zero Bias Exponent Overflow/Underflow Flowcharts Numerical Examples Problems

635 638 641 643 646

Additional Floating-Point Topics Rounding Methods 16.1.1 Truncation Rounding 16.1.2 Adder-Based Rounding 16.1.3 Von Neumann Rounding Guard Bits Verilog HDL Implementations 16.3.1 Adder-Based Rounding Using Memory 16.3.2 Adder-Based Rounding Using Combinational Logic 16.3.3 Adder-Based Rounding Using Behavioral Modeling 16.3.4 Combined Truncation, Adder-Based, and von Neumann Rounding Problems

Additional Topics in Computer Arithmetic Residue Checking 17.1.1 Dataflow Modeling 17.1.2 Structural Modeling Parity-Checked Shift Register Parity Prediction Condition Codes for Addition Logical and Algebraic Shifters 17.5.1 Behavioral Modeling 17.5.2 Structural Modeling Arithmetic and Logic Units 17.6.1 Four-Function Arithmetic and Logic Unit 17.6.2 Sixteen-Function Arithmetic and Logic Unit Count-Down Counter Shift Registers 17.8.1 Parallel-In, Serial-Out Shift Register 17.8.2 Serial-In, Serial-Out Shift Register

649 649 650 651 653 654 654 655 660 668 674 680

685 686 690 693 717 723 738 747 748 753 760 760 764 771 775 775 778

xii

Contents

17.9

Appendix A A.l A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.ll A.12

17.8.3 Parallel-In, Serial-In, Serial-Out Shift Register 17.8.4 Serial-In, Parallel-Out Shift Register Problems

782 787 795

Verilog HDL Designs for Select Logic Functions

8

AND Gate NAND Gate OR Gate NOR Gate Exclusive-OR Function Exclusive-NOR Function Multiplexers Decoders Encoders Priority Encoder Binary-to-Gray Code Converter Adder/Subtractor

801 806 809 811 814 818 822 825 829 833 836 843

Appendix В

Event Queue

B.l B.2 B.3 B.4

Event Handling Event Handling Event Handling Event Handling Assignments

°l

849 for Dataflow Assignments for Blocking Assignments for Nonblocking Assignments for Mixed Blocking and Nonblocking

849 854 857 861

Appendix С

Verilog HDL Project Procedure

865

Appendix D

Answers to Select Problems

867

Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9

Number Systems and Number Representations Logic Design Fundamentals Introduction to Verilog HDL Fixed-Point Addition Fixed-Point Subtraction Fixed-Point Multiplication Fixed-Point Division Decimal Addition Decimal Subtraction

867 869 873 883 887 891 897 903 907

Contents

Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter

Index

10 11 12 13 14 15 16 17

Decimal Multiplication Decimal Division Floating-Point Addition Floating-Point Subtraction Floating-Point Multiplication Floating-Point Division Additional Floating-Point Topics Additional Topics in Computer Arithmetic

xiii

908 912 913 915 918 924 926 932

943