Library of Congress Cataloging-in-Pnblication Data. Digital Computer Arithmetic
Datapath Design Using Verilog HDL. James E. Stine. Additioual material to this ...
DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN USING VERILOG HDL
DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN USING VERILOG HDL
J ames E. Stine
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Pnblication Data Digital Computer Arithmetic Datapath Design Using Verilog HDL James E. Stine
Additioual material to this book cau be dowuloaded from http://extras.spriuger.com. ISBN 978-1-4613-4725-5 ISBN 978-1-4419-8931-4 (eBook) DOI 10.1007/978-1-4419-8931-4
Copyright © 2004 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 2004 Softcover reprint ofthe hardcover Ist edition
AlI rights reserved. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording, or otherwise, without prior written permission from the Publisher, with the exception of any material supplied specificalIy for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.
Printed on acid-free paper.
Contents
ix
Preface l. MOTIVATION 1.1
Why Use Verilog HDL?
1.2 What this book is not : Main Objective 1.3 Datapath Design 2. VERILOG AT THE RTL LEVEL 2.1 Abstraction 2.2 Naming Methodology 2.2.1 Gate Instances 2.2.2 Nets 2.2.3 Registers 2.2.4 Connection Rules 2.2.5 Vectors 2.2.6 Memory 2.2.7 Nested Modules 2.3 Force Feeding Verilog : the Test Bench 2.3.1 Test Benches 2.4 Other Odds and Ends within Verilog 2.4.1 Concatenation 2.4.2 Replication 2.4.3 Writing to Standard Output 2.4.4 Stopping a Simulation 2.5 Timing: For Whom the Bell Tolls 2.5.1 Dela y-based Timing 2.5.2 Event-Based Timin g
1 1 2 3 7 7 10
11
12 12 13
14 14 15 16 18 19 19 21 21 21 22 22 23
DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN
VI
2.6
Synopsys DesignWare Intellectual Property (IP)
24
2.7
Verilog 2001
24
2.8
Summary
26
3. ADDITION
27
3.1
Half Adders
28
3.2
Full Adders
28
3.3
Ripple Carry Adders
30
3.4
Ripple Carry AdderlSubtractor 3.4.1 Carry Lookahead Adders 3.4.1.1 Block Carry Lookahead Generators
31 34 36
3.5
Carry Skip Adders 3.5.1 Optimizing the Block Size to Reduce Delay
40 42
3.6 3.7
Carry Select Adders 3.6.1 Optimizing the Block Size to Reduce Delay Prefix Addition
43 46 47
3.8
Summary
52
4. MULTIPLICATION
55
4.1
Unsigned Binary Multiplication
56
4.2
Carry-Save Concept
56
4.3
Carry-Save Array Multipliers (CSAM)
60
4.4
Tree Multipliers 4.4.1 Wallace Tree Multipliers 4.4.2 Dadda Tree Multipliers 4.4.3 Reduced Area (RA) Multipliers
61 61 65 68
4.5
Truncated Multiplication
71
4.6
Two's Complement Multiplication
78
4.7
Signed-Digit Numbers
82
4.8
Booth's algorithm 4.8.1 Bitwise Operators
86 87
4.9
Radix-4 Modified Booth Multipliers 4.9.1 Signed Radix-4 Modified Booth Multiplication
89 91
4.10 Fractional Multiplication
92
4.11 Summary
93
Contents
Vll
5. DIVISION USING RECURRENCE 5.1 Digit Recurrence 5.2 Quotient Digit Selection 5.2.1 Containment Condition 5.2.2 Continuity Condition 5.3 On-the-Fly-Conversion 5.4 Radix 2 Division 5.5 Radix 4 Division with a = 2 and Non-redundant Residual 5.5.1 Redundant Adder 5.6 Radix 4 Division with a = 2 and Carry-Save Adder 5.7 Radix 16 Division with Two Radix 4 Overlapped Stages 5.8 Summary
103 104 105 106 106 108 112 115 118 119 122 126
6. ELEMENTARY FUNCTIONS 6.1 Generic Table Lookup 6.2 Constant Approximations 6.3 Piecewise Constant Approximation 6.4 Linear Approximations 6.4.1 Round to Nearest Even 6.5 Bipartite Table Methods 6.5.1 SBTM and STAM 6.6 Shift and Add: CORDIC 6.7 Summary
129 131 133 134 136 138 141 142 147 152
7. DIVISION USING MULTIPLICATIVE-BASED METHODS
7.1 Newton-Raphson Method for Reciprocal Approximation 7.2 Multiplicative-Divide Using Convergence 7.3 Summary
161 161 166 168
References
171
Index
179
Preface
The role of arithmetic in datapath design in VLSI design has been increasing in importance over the last several years due to the demand for processors that are smaller, faster, and dissipate less power. Unfortunately, this means that many of these datapaths will be complex both algorithmically and circuitwise. As the complexity of the chips increases, less importance will be placed on understanding how a particular arithmetic datapath design is implemented and more importance will be given to when a product will be placed on the market. This is because many tools that are available today, are automated to help the digital system designer maximize their efficiently. Unfortunately, this may lead to problems when implementing particular datapaths. The design of high-performance architectures is becoming more complicated because the level of integration that is capable for many of these chips is in the billions. Many engineers rely heavily on software tools to optimize their work, therefore, as designs are getting more complex less understanding is going into a particular implementation because it can be generated automatically. Although software tools are a highly valuable asset to designer, the value of these tools does not diminish the importance of understanding datapath elements. Therefore, a digital system designer should be aware of how algorithms can be implemented for datapath elements. Unfortunately, due to the complexity of some of these algorithms, it is sometimes difficult to understand how a particular algorithm is implemented without seeing the actual code. The goal of this text is to present basic implementations for arithmetic datapath designs and the methodology utilized to create them. There are no control modules, however, with proper testbench design it should be easy to verify any of the modules created in this text. As stated in the text, this text is not a book on the actual theory. Theory is presented to illustrate what choices are made and why, however, a good arithmetic textbook is probably required to accompany this text. Utilizing the Verilog code can be paramount along with a textbook on arithmetic and architecture to make ardent strides towards
x
DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN
understanding many of the implementations that exist for arithmetic datapath design. Wherever possible, structural models are implemented to illustrate the design principles. The importance for each design is on the algorithm and not the circuit implementation. Both algorithmic and circuit trade-offs should be adhered to when a design is under consideration. The idea in this text is implement each design at the RTL level so that it may be possibly implemented in many different ways (i.e. standard-cell or custom-cell). This text has been used partially as lecture notes for a graduate courses in Advanced VLSI system design and High Speed Computer Arithmetic at the Illinois Institute of Technology. Each implementation has been tested with several thousand vectors, however, there may be a possibility that a module might have a small error due to the volume of modules listed in this treatise. Therefore, comments, suggestions, or corrections are highly encouraged. I am grateful to many of my colleagues who have supported me in this endeavor, asked questions, and encouraged me to continue this effort. In particular, I thank Milos Ercegovac and Mike Schulte for support, advice, and interest. There are many influential works in the area of computer arithmetic that have spanned many years. The interested reader should consult frequent conference on arithmetic such as the IEEE Symposium on Computer Arithmetic, International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), Proceedings of the Asilomar Conference on Signals, Systems, and Computers, and the IEEE International Conference on Computer Design (ICCD) among others. I would also like to thank my students who helped with debugging at times as well general support: Snehal Ajmera, Jeff Blank, Ivan Castellanos, Jun Chen, Vibhuti Dave, Johannes Grad, Nathan Jachimiec, Fernando MartinezVallina, and Bhushan Shinkre. In addition, a special thank you goes to Karen Brenner at Synopsys, Inc. for supporting the book as well. I am also very thankful to the staff at Kluwer Academic Publishers who have been tremendously helpful during the process of producing this book. I am especially thankful to Alex Greene and Melissa Sullivan for patience, understanding, and overall confidence in this book. I thank them for their support of me and my endeavors. Last but not least, I wish to thank my wife, Lori, my sons, Justyn, Jordan, Jacob, Caden, and my daughter Rachel who provided me with support in many, many ways including putting up with me while I spent countless hours writing the book.
J. E. Stine
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