DESIGN AND COMPARISON OF GaAs AND CMOS REDUNDANT DIVIDER I. Moussa , A. Guyot and P. Rost Integrated System Design -TIMA - INPG 46, Av. Félix Viallet F38031 Grenoble Cedex- France Phone +(33) 76 57 46 16 Fax +(33) 76 47 38 14 e-mail
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Abstract :
This paper presents a combinatorial circuit for fast division Q := A÷D. High speed is achieved thanks first to an improved algorithm and second to its realization in Gallium Arsenide. An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delays with n2 add/subtract cells (called tail) controlled by n controllers (called head). The implementation of the divider circuit has been achieved by using buffering technique and full custom layout methodology that are well suited for high performance designs in GaAs direct-coupled FET Logic (DCFL). Comparison of GaAs and CMOS implementation are given. Index: digital GaAs, division, redundant number systems,
1 . Introduction
In digital signal processing, many algorithms are more stable when using division and square-root extraction. Image processing as well as IEEE floating point implement division. Standard division algorithms rely on the test of the sign of the partial remainder R for each new digit of the quotient, the sign usually demands a carry propagation. The SRT (Sweeney, Robertson, Tocher) [1,2] approach overcomes this problem by using a redundant representation of the quotient Q in order to test only a few most significant digits of the partial remainder. Redundant notation [3] can be used as well to add/subtract the divisor D to the partial remainder R without carry propagation. The division circuit presented in this paper is implemented in a Digital GaAs technology which has remarkably advanced in recent years. The assesement of performance of this technolgy is carried out by comparison with its CMOS equivalent.
2. Range of the remainder Let Q be the quotient Q=A÷D of two normalized positive rationnal numbers 1≤A
