Faster Arithmetic and Logical Unit CMOS Design

Faster Arithmetic and Logical Unit CMOS Design with Reduced Number of Transistors Rachit Patel, Harpreet Parashar, and Mohd. Wajid Deptt. of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan, India {rachit05081gece,harpreet123100,shamsi.shamsi}@gmail.com

Abstract. The Arithmetic and Logic Unit (ALU) is a combination circuit that performs a number of arithmetic and logical operations. Over the past two decades, Complementary Metal Oxide Semiconductor (CMOS) technology has played important role in designing high performance systems because of the advantages that CMOS provides: an exceptionally low power-delay product, the ability to accommodate millions of devices on a single chip. To take the benefits of CMOS technology a novel ALU Circuit is proposed in this paper. An improved and efficient adder circuit called mirror adder [3] is used which helps in decreasing the RC delay. Also a programmable logic circuit is included to configure mirror adder circuit to subtractor circuit depending upon programmable input; this implementation helps in reducing the transistor count and power dissipation, decreasing parasitic capacitance hence increasing speed. Keywords: ALU, CMOS, VLSI, Circuit.

1 Introduction High performance systems and a variety of real time Digital Signal Processing systems derive their performance from VLSI solutions. Since fast arithmetic units are critical to all such high-performance applications [1]. Delay and power dissipation for a circuit also have emerged as the major concerns of designers and depend on the number of transistors are used in the circuit. When the number of transistors is more the capacitance is more due to which the delay is more so here our aim is to reduce the delay and power dissipation [3] [4]. In this paper authors reduced the number of transistor using a programmable adder and subtractor [2]. The factors consider in this paper: number of gates used, performance in terms of speed, delay and parasitic capacitance. The section 2 explains the ALU, the section 3 explains how the mirror adder can be used as subtractor, section 4 gives proposed ALU operational and selection circuits, and section 5 discusses on proposed ALU circuit and design techniques used in it. Finally section 6 concludes the paper.

2 Arithmetic and Logical Operations The arithmetic logic unit (ALU) is the core of a CPU in a computer. An eight function instruction set CMOS ALU Fig.-1 performs Addition, Subtraction, AND, NAND, V.V. Das, J. Stephen, and Y. Chaba (Eds.): CNC 2011, CCIS 142, pp. 519–522, 2011. © Springer-Verlag Berlin Heidelberg 2011

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Fig. 1. Block diagram of an ALU

OR, NOR, XOR and XNOR. Each of these functions is performed on two 1-bit inputs and each of the single bit building blocks can be cascaded together to form a four bit ALU [2]. ADDITION operation is performed using mirror adder which depends upon a programmable input i.e., P when it is equal to 0. SUBTRACTION operation is performed using the same circuitry i.e., mirror adder when the programmable input P = 1. Each of the CMOS ALU functions is performed on a single bit input.

3 Mirror Adder as Subtractor Number of transistors used to design a circuit is an important parameter as it influences overall delay and power dissipation. Also when the number of transistors is more the capacitance is more due to which the delay increases further [4]. Therefore, in CMOS ALU design addition and subtraction is performed using same circuitry in order to reduce the transistor count [3]. The adder block used here is Mirror Adder whose operation i.e. addition or subtraction depends upon a programmable input pin i.e. P. In Fig.-2, SUM = (B`.P + P`.B) + A + P, where P = Cin, P is programmable input. When P=0 then output of adder will be A+B. But when P=1 then output A+B`+1 which is equivalent to A-B [3]. In this way we can use the adder in both ways thereby saving the extra number of gates.

Fig. 2. Block diagram of a programmable adder

4 Proposed ALU Circuitry Figure 3 shows ALU realization using CMOS gates. Left upper part of the figure 3 shows the implementation of various logic gate operations like AND, NAND, OR,

Faster ALU CMOS Design with Reduced Number of Transistors

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NOR, XOR and XNOR whereas left down part shows adder and subtractor implementation using mirror adder with a XOR gate as programmable logic. Mirror adder performs both addition and subtraction on the basis of the value of programmable logic input P [4] [3]. Figure 3 right part shows the selection circuitry implemented using an 8x1 MUX with 3 select lines viz. S0, S1 and S2 which help in selecting the operation that will be performed by the ALU like AND, NAND, addition etc. The 3 control signals S0 (=P), S1 and S2 show the desired output in the order as shown below: Operations AND NAND OR NOR

S2S1S0 0 0 0 0 0 1 0 1 0 0 1 1

Operations XOR XNOR ADDITION SUBTRACTION

S2S1S0 1 0 0 1 0 1 1 1 0 1 1 1

5 Discussion on Proposed Circuit 5.1 Progressive Transistor Sizing The propagation delay calculated using Elmore Delay Model shows that in the MUX circuitry resistance of M96 (R96) in fig. -3 appear 4 times, the resistance of M95 appears 3 times, etc. Consequently progressive scaling of the transistors is beneficial: M96>M95>M94>M93 [3]. This approach reduces the dominant resistance like M96 (R96) and thus the delay. Similarly, same approach can be use for other resistances like M100, M104 and so on.

Fig. 3. ALU Operational circuitry (left) and Selection Circuitry (right)

5.2 Input Reordering In the MUX circuitry, SUBTRACTOR signal is a critical signal as compared to select lines input S0, S1 and S2 as it is coming after passing through a number of logic gates so there will be delay before it gets stable [4]. Putting the critical path transistors closer to the output of the gate can result in a speed up. Therefore, SUBTRACTOR

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signal is placed closer to the output signal. Similarly other critical signals like AND, NAND, OR, NOR etc. are also placed closer to the output to reduce delay [3]. 5.3 Performance With the reduction of number of gates the overall capacitance is reduced. Progressive transistor sizing & input reordering helped in reducing delay. Thus, hence improve the performance [4] [3].

6 Conclusion ALU being the core of any processor has been designed using CMOS because it uses various flexible design techniques to reduce delay, power, cost and to increase speed. Also, CMOS approach helps in accommodating large number of transistors on a single chip. All this improves the performance of the ALU. Mirror adder with programmable logic circuitry is an efficient method used to reduce the transistor count by performing dual function of addition and subtraction using single adder circuitry. Design techniques like Progressive transistor sizing and input reordering is used to reduce the overall delay which in turn increase the performance.

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