Design and Simulation of Moore Logic Circuit based ...

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Design and Simulation of Moore Logic Circuit based ...

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Comment

y1 y2 y3 y4. X. 5 V jksarblock. X. X. CLK. CLK y1 y1 y2 y2 y3 y3 y4 y4. TABLE 3: FIGURE 8: 4. Digital To Analog Circuit. 000. 001. 011. 010. 110. 111. 101. 100.

Design and Simulation of Moore Logic Circuit based SAR Analog to Digital Converter Osama Q.J Al-Thahab Engineering Faculity/Electgrical Department University of Babylon Babylon, Iraq

[email protected]

Hanaa mohsin ali Engineering Faculity/Electgrical Department University of Babylon Babylon, Iraq

[email protected]

Abstract

Keywords:

1. Introduction

2. Types of ADC 2.1 Flash ADC

Logic Encoder

2.2 Digital ramp ADC

FIGURE1:

FIGURE2:

.

2.3 Tracking ADC

FIGURE

2.4 Successive Approximation ADC

.

FIGURE4

3. proposed Moore SAR Logic circuit

FIGURE 5:

0000

0

1 1000 0

0

1

0100 0

0 0001

1100 1

0010

0

0110

1

0

0011

1

1010 1

0101

0 0111

1001

1 1110

1

0

1011

1

1101

1111

FIGURE 6:

previous State y4 y3 y2 y1

Next State X= 0 X= 1

TABLE 1:

J4K4

Input (X= 0) J3K3 J2K2

TABLE 2:

J1K1

J4K4

Input (X= 1) J3K3 J2K2

J1K1

000

001

011

010

110

111

101

100

00 01 11 10

TABLE 3:

X CLK

y1

X y4

y3

y2

y2

y1

y3 y4 SET J

Q

CLK

5V

K

~Q RESET

SET J

Q

CLK K

~Q RESET

SET J

Q

CLK K

~Q RESET

X CLK SET J

Q

CLK K

4. Digital To Analog Circuit

y1

y1 y2 y2 y3 y3 y4 y4

~Q RESET

FIGURE 8:

X CLK

jksarblock

⁄

LSB Do

MSB D1

2R

2R

R

D2 2R

R

D3 2R

2R

y1 y2 y3 y4

Ref

y1 y2 y3 y4

O

R

DAC (b)

FIGURE 9:

5. Comparator

6. Clock

VCC GND

Clouck

FIGURE 10:

7. JK-Counter

O

CLK

O

8. Latch

y1

y3 y2 y1 SET J

VCC 5V

y2 Q

y3

CLK K

~Q RESET

CLK

SET J

Q

CLK K

~Q RESET

SET J

Q

CLK K

CLK

y1

CLK

y1 y2 y2 y3 y3

~Q RESET

JK-counter

y1

Q1

y2

Q2

SET

y3

D

y4

CLK

Q

Q3

~Q

Q4

RESET

CLK

SET D

Q

CLK

~Q

RESET

SET D

Q

CLK

~Q

RESET

SET D

Q

CLK

~Q

RESET

FIGURE 11:

y1 y2 y3 y4 CLK

y1 y2 y3 y4 CLK

Q1 Q2 Q3 Q4

DLatch1

Q1 Q2 Q3 Q4

9. Proposed Moore SAR ADC

10. Results and Discussion

COMPARATOR_VIRTUAL

G T A

B

C

D

X

Vref X CLK

y1

X CLK

y1 y2 y3 y4

y1 y2 y2 y3 y3 y4 y4

y1 y2 y3 y4

O

O

jksarblock

DCD_HEX_DIG_RED

DAC y1 y2 y3 y4 CLK

Q1

y1 y2 y3 y4 CLK

Q1 Q2 Q2 Q3 Q3 Q4 Q4

DLatch1

5V

VCC GND

CLK

CLK

Clouck

y1

CLK

y1 y2 y2 y3 y3

JK-counter

FIGURE 12:

COMPARATOR_VIRTUAL

G T A

B

C

D

X

Vref X CLK

X CLK

y1

y1 y2 y2 y3 y3 y4 y4

y1 y2 y3 y4

y1 y2 y3 y4

jksarblock

O

O

DAC y1 y2 y3 y4 CLK

y1 y2 y3 y4 CLK

Clouck

CLK

CLK

CLK

JK-counter

FIGURE 13

y1

y1 y2 y2 y3 y3

Q1

Q1 Q2 Q2 Q3 Q3 Q4 Q4

DLatch1

5V

VCC GND

3 V

DCD_HEX_DIG_RED

FIGURE 14:

COMPARATOR_VIRTUAL

G T A

B

C

D

Vref y1 y2 y3 y4

y1 y2 y3 y4

O

O

1.5 V

DAC y1 y2 y3 y4 CLK

y1 y2 y3 y4 CLK

DLatch1

FIGURE 15:

Q1

Q1 Q2 Q2 Q3 Q3 Q4 Q4

DCD_HEX_DIG_RED

COMPARATOR_VIRTUAL

G T A

B

C

D

Vref y1 y2 y3 y4

y1 y2 y3 y4

O

O

DCD_HEX_DIG_RED

5 V

DAC y1 y2 y3 y4 CLK

Q1

y1 y2 y3 y4 CLK

Q1 Q2 Q2 Q3 Q3 Q4 Q4

DLatch1

FIGURE 16:

COMPARATOR_VIRTUAL

G T A

B

C

D

Vref y1 y2 y3 y4

y1 y2 y3 y4

5 Vpk 10 Hz 0°

O

O

DAC y1 y2 y3 y4 CLK

y1 y2 y3 y4 CLK

DLatch1

FIGURE 17:

Q1

Q1 Q2 Q2 Q3 Q3 Q4 Q4

DCD_HEX_DIG_RED

11. Conclusion

12. Future work

13. REFERENCES

Engineering.