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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 3, JUNE 2006
Design Aspects of a Switch-Mode Transformer Under Wide Input Voltage Variation Ali I. Maswood, Senior Member, IEEE, and Zee Kum Yoong
Abstract—Proposed is a discrete switch-mode fly-back power supply that combines part of its resonance topology into its switchmode transformer (SMT). The resonant action is generated by the snubber circuit, and an expensive tank circuit is avoided. The “minimum switch on” circuit from the proposed SMT primary and lower auxiliary winding is designed in such a way that it provides a delay of half-resonant cycle before the driver circuit switches on the biasing circuit. This paper presents some practical design aspects of a series of SMTs intended to be used in developed and developing countries where the ac mains voltage is expected to fluctuate from very narrow to wide ranges, respectively. Index Terms—Biasing, fly-back, quasi-resonance, resonance tank, snubber, switched-mode power supply (SMPS), switch-mode transformers (SMTs), zero-voltage switching (ZVS).
Fig. 1.
Switching waveform at drain of power MOSFET T 1.
Fig. 2.
Supply voltage (upper trace) and current (lower trace).
I. I NTRODUCTION
W
ITH the increasing demand for size reduction in switched-mode power supplies (SMPS), the most important element of the SMPS, the switch-mode transformer (SMT), has been the subject of a great deal of attention. Previous works have pointed attention to CAD optimization methods [2], planar designs [8], structures for high-frequency resonant converters, printed winding structures, high frequency, pot core designs, high-power designs, and the effect of geometry on performance [4], [5], [8]. Present-day requirements, however, are for transformers that are cheap, easy to manufacture, efficient, and meet all the relevant safety criteria, and are small with a low profile [3]. However, almost all previous works are based on a narrow ac mains voltage typically around the nominal value of 110 or 220 V with a standard 5% voltage fluctuation. With the increasing demand of SMPS for cheaper TVs manufactured for developing countries, there is a great demand for the technical know how of such design philosophy. This is more so because of the unpredictable and wide ac mains voltage fluctuation usually encountered in such countries. This know how not only applies to TV power supplies, but also to SMTs for PC, telecom, and related applications. Maswood and Song [8] proposed just such an SMT using the planar technology. In their work, the ac mains voltage was expected to swing between 64 and 265 V, which is a common scenario in many Asian countries. Their work, however, found that, unless
Manuscript received April 27, 2004; revised January 7, 2005. Abstract published on the Internet March 18, 2006. A. I. Maswood is with the Centre for Advanced Power Electronics School of Electrical and Electronic Engineering (EEE), Nanyang Technological University, Singapore 639798 (e-mail:
[email protected]). Z. K. Yoong is with Thomson Multimedia Asia Pte Ltd., Singapore 318994. Digital Object Identifier 10.1109/TIE.2006.874420
there is a possibility of acute electromagnetic interference (EMI) problem or space constraint is very important, a planer transformer costing at least twice as much compared to its conventional counterpart is not a feasible option. The economic constraint naturally shifts the choice toward conventional SMT. Apart from the previously published works [1], [3], [8] in which prototypes are constructed based only on calculated SMT parameters, the proposed work initially develops an SMT personal computer simulation program with integrated circuit emphasis (PSPICE) model and incorporates it into the complete PSPICE SMPS topology to check the “system effect.” Instead of designing the SMT as a standalone object, the novelty of this paper lies in the incorporation of part of the SMPS resonance topology into the SMT. Such a fact has mostly been overlooked in previous works. Parameters such as on–off time, MOSFET switching characteristics under resonant switching condition (Figs. 1–3) obtained from the PSPICE model are actually used to fine tune vital transformer parameters before the actual hardware prototype is built. The SMT design to accommodate the free oscillation safe and intelligent (FROSIN) topology is explained in this paper. The SMT location in the SMPS topology is depicted in Fig. 4 as “L1.” The upper output terminal (across C10) is dedicated to the TV video power supply, whereas the lower output
0278-0046/$20.00 © 2006 IEEE
MASWOOD AND YOONG: DESIGN ASPECTS OF AN SMT UNDER WIDE INPUT VOLTAGE VARIATION
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From these fundamental equations, several design equations are derived. These are On time 2 · P · Lp (3) Ton = V2·f where V SMT input dc voltage; Lp SMT primary inductance; f switching frequency; Ton on time; P input power. SMT primary Inductance Fig. 3.
MOSFET and the proposed SMT switching waveforms.
V · Ton . Ip
(4)
2P . V · Ton · f
(5)
Vo · Toff Is
(6)
Lp =
terminal (across C20) serves the audio and other auxiliary power requirement. The SMPS power supply makes use of the snubber oscillation [7], and adjust the turn-on point at approximately half cycle of the LC resonance, also known as quasi-resonance. This concept is similar to the resonant power-supply zero-voltage switching (ZVS) characteristic. The advantages of ZVS are [3]: 1) reduced switching-on loss; 2) reduced EMI problem due to fall time of dv/dt. Having investigated the existing research work, it is evident that a minimum turn-on loss in an SMT can be achieved by: 1) implementing a proper control circuit; 2) snubber capacitor; and 3) transformer-turns-ratio design. Choosing the correct turns ratio, primary/secondary inductances, snubber capacitors, and a specific core type to create the necessary conditions for ZVS remains the principal motivation behind this paper. This is a challenging task, especially when the supply voltage is expected to vary within such a wide range. The SMT ZVS is effected by the snubber plus the MOSFET parasitic capacitances, although the MOSFET parasitic capacitance is much smaller compared to that of the snubber. The required ZVS is obtained by choosing MOSFET STP 3NA80FI provided in the PSPICE device library that closely matches the required capacitance. In the hardware prototype, a very similar commercially available MOSFET STP5NA80FI manufactured by SGS Thomson was employed. Under the SMPS topology, the SMT switch-on transient can be illustrated as in Fig. 5.
Primary winding peak current Ip = Secondary inductance Ls =
where Vo SMT secondary output dc voltage; SMT secondary winding peak current; Is Toff switch-off time. Secondary winding peak current Is =
2Po . Vo · Toff · f
(7)
A. Core Design Core design includes the following steps [2]. 1) Calculate the actual transformer primary current with transformer loss as shown below where Ip peak collector current; Ic core loss current (hysteresis and eddy current); Ip Ip (ideal) + Ic . Normally, Ic < 0.1 × Ip .
II. SMPS T RANSFORMER D ESIGN The two important fundamental equations that are used in switched-mode power supply are [1] Power = Energy × Frequency 2
P = (1/2) LI · f.
(1)
di . dt
(2)
Voltage equation for inductances V =L·
In this case, the effective current I(eff) will be I(eff) = Ton Ip2 + Ip · Ic + Ic2 /3T
(8)
where I(eff) = I(rms). 2) The following information is found from the transformer core material data sheet usually supplied by the manufacturer (Fig. 6): Bs saturation flux density; Br residual flux density; permeability; Ui
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Fig. 4. Complete schematic diagram of the proposed power supply.
Fig. 7.
Transformer saturation characteristic.
where Lp primary inductance, when I = Ip ; Lpo primary inductance, when I = 0. Calculate also
Fig. 5. Minimum-voltage turn-on at half cycle.
H = B/Um .
(12)
4) Determine the required SMT effective core volume. This is actually the minimum effective volume because the actual core volume should be more than this. Minimum V (eff) = Fig. 6. Transformer input (also MOSFET drain) current.
Cvf
core-loss factor (core loss per volume per frequency) B(operating) = Bs − Br .
(9)
Core loss per volume Cv = Cvf · freq.
(10)
3) The increment permeability Um due to SMT saturation is found as Um = Ui · Lp /Lpo
(11)
0.4π · 108 · Lp · Ip B·H
(13)
B and H are obtained from (9) and (12), respectively. 5) Select the minimum core size, a suitable wire, and air gap. The most suitable core that is meant for Asian markets (developing countries with a wide variation of ac mains voltage), where the input ac voltage is expected to swing between 90 and 264 V, is ERL35. A multistrand 0.1 mmφ × 20 wire is chosen for the purpose of reducing the temperature rise and eliminating skin effect. Air gap is important in saturation consideration. However, a compromise between saturation and leakage is the main criterion in air-gap design. The SMT saturation curve (inductance versus current), as shown in Fig. 7, illustrates the effect of air gap in saturation characteristic. In Fig. 7,
MASWOOD AND YOONG: DESIGN ASPECTS OF AN SMT UNDER WIDE INPUT VOLTAGE VARIATION
x-axis represents the dc current into the primary winding, while the y-axis represents the primary inductance. B. Design of Discontinuous Mode Fly-Back Converter The design criteria must include the following. 1) Fixed frequency, or free running, at worst case Ton + Toff is less than 1/f . 2) Typically, on cycle is less than 50% of the duty cycle. 3) Transformer polarity is inverted as compared to forward converter. The design steps are given as the following. 1) Choose an operating frequency. 2) Calculate Ton (max) based on criterion 2) above. 3) Knowing the maximum power required and minimum dc supply input, use (5) to obtain Ip Ip =
2P . V · Ton · f
(14)
4) Choose an appropriate switching transistor. 5) Calculate primary inductance using (14) Lp =
V · Ton . Ip
(15)
6) Determine Toff and dead-zone time using (16) to obtain Is Is =
2Po . Vo · Toff · f
(16)
7) Use Is to calculate the secondary inductance. Ls =
Vo · Toff Is
(17)
where Vo secondary output dc voltage; secondary winding peak current; Is Toff off time. Once the transformer-design approach is completed, the transistor and rectifier diode ratings can be determined. The following section shows the examples of designing a series of transformers with an aim to create ZVS to accommodate the minimum switching loss. III. E XAMPLE Initial design is carried out using PSPICE circuit-simulation package. Two SMTs are designed for European and Asian markets (narrow and wide ac-mains-voltage fluctuations, respectively). The procedure is as follows. Step 1—Power-Transistor Selection [6]: 1) MOSFET Vds (max) = 800 V 2) for Europe, narrow range: 180–264 Vac Id (max) = 3 A
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3) for Asia, wide range: 90–264 Vac Id (max) = 5 A. Step 2—SMT Turns Ratio: Several voltage types to be accommodated in turns-ratio design. These include the following. 1) Vp = peak voltage, a safe margin 90% is provided during high mains. It is important to note that the peak voltage is affected by the ringing due to SMT coupling. 2) Vm = maximum voltage, which is raw B+ (Fig. 1) and reflected voltage. 3) Raw B+ = this is the dc voltage after mains rectifier Raw B+ = Vin (dc). 4) Vr = reflected voltage, which is the secondary voltage seen from the primary. This voltage is equal to the product of the secondary voltage and turns ratio. The following PSPICE-generated waveform shows the estimated voltage points for wide and narrow ranges. Note that there are some differences between wide and narrow ranges due to the transformer types. Orega (slot-type) transformer is used in a narrow range, which gives more ringing than the layer type wide-range SMT. This results in the accommodations of various Vm for various core types. Based on the above information and design with reference to 110-V-system voltage, the turn ratios can be obtained and they are detailed in step 3. Step 3—Calculation of SMT Inductances: The following assumptions are made. Input power Pin = 80 W. Input power is defined as the product of the current supplied to the SMT and the raw-B+ voltage. Secondary output power at system winding Po = 70 W. 10 W used by sound and other processors Pin = ν(t)i(t) = Vin ·
1 Ton · Ip · . 2 T
SMT primary current Ip =
2Pin . Vin TTon
(18)
Note that (18) is similar to (5) as expected. Also, at the SMT, the following two equations can be set: Lp = Ls
Np Ns
2 .
(19)
This is transformer-inductance-to-turns-ratio theory. From electromagnetic induction theory di dt Vin · Ton . Lp = Ip V =L
(20)
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Also, note that (20) is similar to (4). Arranging (18)–(20) to obtain the ratio of Ton /Toff Ton Np V o = · · Toff Ns Vin
Pin . Po
(21)
The total time of one complete switching cycle is the period T . T = Ton + Toff + Ts + Tf + Trr where Ton on time; Toff off time; snubber half-cycle time; Ts MOSFET current-fall time; Tf Trr diode reverse-recovery time. All these instants are in detail shown in the PSPICE generated Fig. 3. The required design parameters for the projected European and Asian markets are presented as follows: 1) narrow-range SMT I/O values operate at 50 kHz at 180 VAC; Vin = 180 × 1.414 − (diode + resistor drop); Vin = 250 V; video output Ub = 110 V; from Fig. 1 estimated Vr = 570 − 370 = 200 V; turns ratio Np /Ns = Vr /Ub = 200/110 = 1.8; estimated Tosc = 5 µs; 2) wide-range SMT I/O values operate at 30 kHz at 90 VAC; Vin = 90 × 1.414 − (diode + resistor drop); Vin = 125 V; video output Ub = 110 V; from Fig. 1 estimated Vr = 620 − 370 = 250 V; turns ratio Np /Ns = Vr /Ub = 200/110 = 2.3; estimated Tosc = 7 µs. A set of calculations has been carried out to determine the proposed SMT parameters for the two selected markets. Calculation begins with (21). 3) calculation for narrow-range SMT parameters Ton 110 80 = 1.8. Toff 250 70 Ton = 0.85Toff Toff = 1.18Ton T = Ton + Toff + Tosc 20 µs = 2.18Ton + 5 µs Ton = 6.88 µs Toff = 8.12 µs 2Pin Ip = Vin TTon = 1.86 A Vin · Ton Lp = Ip 250 × 6.88 µH = 1.86 = 925 µH Ls = 285 µH
4) calculation for wide-range SMT parameters 110 Ton = 2.3. Toff 125
80 70
Ton = 2.16Toff Toff = 0.46Ton T = Ton + Toff + Tosc 33 µs = 1.46Ton + 7 µs Ton = 17.8 µs Toff = 8.2 µs Ip =
2Pin Vin TTon
= 2.37 A Vin · Ton Lp = Ip 250 × 6.88 µH 1.86 = 940 µH
=
Ls = 178 µH. Based on the exact calculated values, the following are the selected commercially viable SMT parameters: 1) narrow-range SMT actual SMT assembled Lp = 890 µH; Ls = 280 µH; core EE29; turns ratio = 1.8; air gap = 0.9 mm; 2) wide-range SMT actual SMT assembled Lp = 980 µH; Ls = 175 µH; core ERL35; turns ratio = 2.38; air gap = 1.4 mm. IV. E XPERIMENTAL R ESULTS To confirm the simulation results, a 80-W experimental prototype is developed in the laboratory. The following waveforms are actually obtained from the prototype. Fig. 8 presents the main switching MOSFET voltage and current waveforms. The upper two waveforms in Fig. 9 illustrate the SMPS video output (depicted as Vb /Ib ) voltage and current, respectively. Whereas, the lower trace presents the current through the audio [depicted as I(Ua )] output terminal. They clearly show the ZVS obtained through the proper selection of the SMT primary/secondary inductances, and the input/output snubber capacitors (MOSFET snubber, C10, C20). The switching characteristics are further illustrated in detail as follows.
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Fig. 10. SMT primary side regulation control circuit (minimum switch on circuit) in schematic of Fig. 4. Fig. 8. MOSFET switching characteristics illustrating turn-on at minimum voltage.
Fig. 9. SMPS output voltage and current waveforms at minimum-voltage turn-on. From top to bottom—video terminal voltage/current and the audio terminal current.
A. Time t1 to t2 At t1 , power MOSFET starts to conduct. At this, time the snubber oscillates at minimum voltage (approximately 100 V). A surge current of 0.7-A peak at t1 is due to the discharging of current from 100 V stored in the snubber capacitor associated with the switching MOSFET shown as T 1 in Fig. 4. Also, the drain current is a linear ramp up until t2 before cutting off the power transistor. During t1 − t2 = on time, the energy in the primary is accumulated. B. Time t2 to t3 Power MOSFET switches off, and the energy is transferred to the SMT secondary (Ua , Ub ). The currents from Ua and Ub windings charge up the capacitors CP10 and CP20. The currents shown in Fig. 9 are affected with the high-frequency ringing due to the coupling of the SMT, and its self-resonance at about 1 MHz. At time t3 , the secondary energy is fully transferred to the load, and no energy is stored in the SMT. After interval t3 , the primary inductance and the snubber capacitors form an LC tank network and oscillates at its natural frequency.
C. Time t3 to t4 Snubber oscillation occurs, and power MOSFET is turned on after half snubber-resonance cycle. Two RC delay circuits control this turn-on delay. The switching frequency, peak current, and peak voltage vary according to the mains and load deviations. A specially designed regulation circuit depicted in Fig. 10 and described in the following paragraph controls these changes. In Fig. 10, current I4 is the main control of the load regulation. I3 and I4 are the controls when mains voltage variation occurs. I2 provides a kick start to Tp22 during startup and also helps CP22 to store more charges during the standby mode. Thus, it controls the minimum on time at low-load conditions. I1 charges CP22 during the snubber oscillation in order to provide a delayed turn on of TP22 as well as the main turn-on transistor TP20 (T 1 in schematic of Fig. 4). High transformer efficiency is achieved when the copper losses are equal to the core losses. For SMT operating at high frequency and under nonideal voltage/current waveforms, optimum efficiency is obtained when the ratio of the core loss to copper loss is equal to 2/X, where X is the slope of the core loss to the flux-density line at a point tangent to the operating flux density. This is obtained from the Watts/pound versus kilo-Gauss characteristic of the selected core material. The efficiencies of the proposed SMTs are 94% for the widerange type and 96% for the narrow-range type. However, the system efficiency will somewhat be lower at around 90%. V. C ONCLUSION This paper presents a systematic and practical approach for the design of the high-frequency SMTs to be used in the proposed soft-switched dual-output TV power supply. Detailed and step-by-step approach is provided to address the needs of the SMT manufacturers, especially in developing countries. In the proposed SMPS topology, correct SMT parameter selections are critical because the secondary reflected voltage determines the snubber peak-to-peak voltage, which affects the minimum turn-on point of the switching transistor. Such SMT is difficult to design especially for applications where the ac mains voltage is expected to fluctuate widely, as is the case described in this paper. Therefore, the primary-to-secondary turns ratio is
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designed to have a compromise between the minimum turn-on point and appropriate switching frequency leading to a low loss and high-efficiency SMPS. Prototypes of the two SMTs are assembled, implemented, and their performances are evaluated. The results obtained are very much in agreement with the predicted ones that have previously been obtained from the simulated SMT and from numerical calculations. Commercial versions of this SMT are already being produced in 14- and 21-in TVs aimed for Asian markets.
[6] H. M. Surya Wanshi and S. G. Tarnekar, “Modified LCLC-type series resonant converter with improved performance,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 143, no. 5, pp. 354–360, Sep. 1996. [7] X. He, W. W. Williams, S. J. Finney, Z. Qian, and T. C. Green, “New snubber circuit with passive energy recovery for power inverter,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 143, no. 5, pp. 403–408, Sep. 1996. [8] A. I. Maswood and L. K. Song, “Design aspects of planer and conventional SMPS transformer, A cost benefit analysis,” IEEE Trans. Ind. Electron., vol. 50, no. 3, pp. 571–577, Jun. 2003.
ACKNOWLEDGMENT
Ali I. Maswood (S’85–M’88–SM’96) received the B.Eng. and M.Eng. degrees (with first class honors) from Moscow Power Engineering Institute, Moscow, Russia, and the Ph.D. degree from Concordia University, Montreal, QC, Canada. Having taught in Canada for a number of years, he joined Nanyang Technological University, Singapore, in 1991, where he is currently an Associate Professor. His research interest is in power electronics, particularly in converter-generated harmonics, novel inverter topologies, advanced pulsewidth-modulation (PWM) switching, and power quality. He has authored several international journal and conference publications on these topics. His work in free oscillation safe and intelligent (FROSIN) switch-mode power supply gave rise to several patents. He is also the chapter-author of Power Electronics, Handbook (Academic, 2002). Dr. Maswood is actively involved in the local IEEE IAS/PELS chapter and in the Steering Committee of the IEEE Power Electronics and Drives (PEDS) Conference.
The authors would like to thank Thomson Multimedia for the support and facilities. Without them, this paper would not have been made possible. R EFERENCES [1] J. Turowski and A. Pelikant, “Eddy current losses and hot spot evaluation in cover plates of power transformer,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 144, no. 6, pp. 435–440, Nov. 1997. [2] D. J. Wilcox, M. Condon, D. J. Leonard, and T. P. McHale, “Time domain modelling of power transformers using modal analysis,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 144, no. 2, pp. 77–84, Mar. 1997. [3] A. J. Forsyth and Y. K. E. Ho, “High performance control of the seriesparallel resonant converter,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 144, no. 2, pp. 131–139, Mar. 1997. [4] G. Ioannidis, E. Xanthoulis, and S. N. Manias, “Analysis and design of a novel fixed-frequency buck-boost zero-current zero voltage switched converter,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 145, no. 1, pp. 33–38, Jan. 1998. [5] G. A. Karvelis and S. N. Manais, “Analysis and design of a fly-back zero-current switched quasiresonant AC/DC converter,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 144, no. 6, pp. 401–408, Nov. 1997.
Zee Kum Yoong, photograph and biography not available at the time of publication.
