Design Considerations and Implementation of a DSP-Based Car ...

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

Design Considerations and Implementation of a DSP-Based Car-Radio IF Processor Michele Sala, Fabrizio Salidu, Fabrizio Stefani, Christian Kutschenreiter, and Andrea Baschirotto, Senior Member, IEEE

Abstract—This paper describes design considerations and the implementation of a software defined radio receiver encompassing intermediate frequency (IF) digitization. The proposed system-on-chip performs the demodulation of both AM and FM stereo signals, digitized at the IF by means of a high dynamic range sigma-delta bandpass A/D converter. The chosen architecture combines hardware and software functions, trading flexible programmability with area occupancy. The software includes also true blind equalization of the FM signals, resulting in the rejection of the neighbor channels and of any other interfering signal, even under severe multipath conditions. The described chip, realized in a 0.18- m CMOS technology, occupies an area of 15.2 mm2 and is enclosed in a 64-pin package. Index Terms—Amplitude modulation, digital signal processors, frequency modulation, IF systems, integrated circuit design, radio broadcast receivers.

I. INTRODUCTION

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URRENTLY, in the wireless broadband communication scenario, the general trend aims at the software-defined radio receiver, as an answer to the request of reconfigurable and multistandard systems [1]. In such architectures, the receiver is capable of modifying the digital processing depending on its configuration. Two different approaches to the embodiment of the software radio concept can be found in literature [2], [3]: the former uses a digital signal processor (DSP), and the latter a field programmable gate array (FPGA). The software radio approach can be adopted in the automotive industry as well, where car radios have to deal with different radio broadcasting standards for the three main markets (Europe, America, and Japan). State-of-the-art solutions face this problem with different hardware platforms. Additionally, the consumer market requires the radio receiver to have more advanced functions than standard AM and FM demodulation: channel and audio equalization, diversity techniques, and MPEG-1 Layer 3 algorithm decoding have become common features, along with integration with multimedia devices,

Manuscript received November 3, 2003; revised January 20, 2004. M. Sala, F. Salidu, and F. Stefani are with the Car Communication Division, STMicroelectronics srl, Cornaredo, 20010 Italy (e-mail: [email protected]; [email protected]; [email protected]). C. Kutschenreiter is with the Car Communication Division, Design and Application GmbH, STMicroelectronics, Grasbrunn 85630, Germany (e-mail: [email protected]). A. Baschirotto is with the Department of Innovation Engineering, University of Lecce, Lecce 73100, Italy (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2004.829402

Fig. 1. Car-radio receiver with IF digitization.

as compact disc (CD) players, phone handsets, and global positioning system (GPS) navigation. A software-configurable radio is the answer to these requests. However, systems designed involving the RF digitization are not practical, even if valuable. In fact, a wide-band analog-to-digital (A/D) converter, providing high resolution over a large bandwidth, consumes large power. This would be a major roadblock that will not disappear with new deep-submicron technologies. Analog preprocessing, like RF-to-IF downconversion, has the advantage of reducing the power consumption of the receiver. Intermediate solutions [4], [5] performing the digitization of the IF have been developed. The direct digitization of the channel at this stage brings several advantages. The most evident is the intrinsic precision of the demodulation process in the digital domain. A second advantage is the simplified design of the analog front-end, as only one FM ceramic filter is adopted. It is intended to protect the A/D converter from strong interfering signals, and its specifications can be relaxed because it does not have to provide full channel selectivity, since the channel filtering is digitally performed with exactly linear phase. Last but not least, the bandwidth of the received FM signal can be adaptively modified, so that an optimum tradeoff between channel selectivity (determined by neighbor channel suppression) and distortion (given by the intrinsic channel bandwidth limitation introduced by the filter in FM) is achieved. Fig. 1 shows the partitioning of the overall receiver system, composed by an RF front-end and an IF signal processor. The RF signal is adjusted in gain by an automatic gain control loop (AGC), which adapts the level depending on field conditions. Next, it is mixed with a locally generated sine wave to obtain an IF-centered version of the desired broadcasted channel. The IF signal is finally filtered by a ceramic bandpass filter, attenuating undesired neighbor channels and out-of-band energy, and thus reducing the dynamic range (DR) requirements for the following stages.

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SALA et al.: DESIGN CONSIDERATIONS AND IMPLEMENTATION OF A DSP-BASED CAR-RADIO IF PROCESSOR

Fig. 2.

Simplified FM demodulator signal flow. Shadowed blocks are implemented in hardware.

Fig. 3.

Simplified AM demodulator signal flow. Shadowed blocks are implemented in hardware.

The car-radio system, in which the IF processor is embedded, operates under severe field conditions, but it is nevertheless required to ensure high-fidelity audio quality. The purpose of this paper is to illustrate such an IF processor, especially focusing on the motivations and design strategies, which have lead to the chosen architecture. The device has been realized in 0.18- m CMOS technology, in 15.2 mm . This paper is organized as follows. Section II presents the functional behavior of the processing, focusing on the signal flow and on the rationale behind the design. Section III critically addresses the system architecture, providing relevant information on the modules. Section IV reports device physical data and major experimental results in the presence of multipath propagation and neighbor channel interference. Finally, in Section V, conclusions are drawn. II. FUNCTIONAL DESCRIPTION Figs. 2 and 3 show the simplified signal flows respectively used in the demodulation of FM and AM signals in the IF-signal processor of Fig. 1; the use of AM rather than FM operating mode is digitally selected.

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A single IF has been used, allowing the processing before detection to be independent from the nature of the modulation scheme. The analog IF signal from the tuner front-end is digitized by a sigma-delta A/D converter. The digital downconverter (DDC) transforms the IF into a quadrature complex baseband signal, whose bandwidth and sample rate have been reduced by filtering and decimation. FM and AM signals have peculiar characteristics depending on the real-world propagation channel; other than additive noise, disturbing both AM and FM, multipath fading is a major problem for FM signals [6], along with neighbor channel interference; therefore, in order to improve reception quality, it is necessary at this point to distinguish between AM and FM. A. FM Processing In the case of FM, the complex baseband signal is equalized prior to demodulation. The lack of a priori knowledge of either the broadcasted signal or the channel impulse response and the unavailability of any training sequence transmission call for blind equalization. This technique recovers the signal on the basis of its statistical properties [7]. The frequency-modulated

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signals have constant modulus, which is the basis for the constant modulus algorithm (CMA) [8]. In the CMA, the coefficients of a finite-impulse response (FIR) filter are adaptively varied in order to compensate the propagation channel transfer function, coping with additive noise, multipath fading distortion, and neighbor channel interference. As a drawback, the CMA is likely to converge to wrong solutions in the real-world radio-broadcasting scenario; in fact, multiple FM signals are present at the equalizer input, getting the CMA to filter out everything but the highest energy signal, being it the desired signal or a neighbor. In the proposed system, an algorithm based on the work of [9] has been conceived to detect and prevent such a condition. As a result of this improved CMA, the bandwidth of the received FM signal is adaptively narrowed by the filter, yielding the suppression of the interfering neighbor channel. A good tradeoff between system performance and computational complexity is the choice of a sixth-order equalizer filter. According to the signal flow shown in Fig. 2, after equalization, the AM/FM detector demodulates the complex baseband signal; the result of the detection is the composite, also known as the multiplex (MPX) signal, which carries the stereo-encoded audio and the Radio Data System (RDS) information [10]. The MPX signal, though equalized, is still affected by the instantaneous spike noise originated by the electromagnetic fields due to fast current variations, and to the high current discharges in the ignition phase of the car engine. The CMA is not able to remove this noise, since the equalizer convergence is not fast enough to react on these stochastic rapid transitions. Therefore, dedicated algorithms for spike detection and suppression have been developed. The spike-detection algorithm uses the stereo MPX signal and the level information to locate spikes; this is accomplished by mean of a first-order adaptive infinite impulse response (IIR) low-pass filter, which produces a trigger signal indicating the starting point and the duration of the spike. The trigger signal is used for substituting the corrupted portion of the MPX signal, with reconstructed data, which are computed by linearly interpolating undistorted samples before and after the spike. Audio information is subsequently retrieved from the processed MPX by the stereo decoder, which also performs typical weak signal-processing functions as stereo channel blending, audio soft muting for low antenna signals, and de-emphasis filtering. After further sample-rate reduction, the digital audio is available for transmission to external devices (such as power amplifiers, D/A converters, or audio processors). B. AM Processing AM bandwidth is about one twentieth of the FM, thus additional filtering and decimation is required after the DDC. AM signals cannot be equalized according to the constant module property, consequently, only demodulation is further necessary. As shown in the flowchart reported in Fig. 3, either the double side-band (DSB) or independent side-band (ISB) demodulation technique can be applied, depending on the received modulated signal quality; ISB improves neighbor channel rejection, selecting and demodulating the sideband with weaker interferer. Both strategies use an AM/FM detector for evaluating the amplitude of the complex baseband signal.

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Fig. 4. Single-chip IF processor hardware architecture.

Similarly to FM signals, engine-injection-related spikes are a concern; hence, spike detection and noise blanking are performed on the audio signal. Moreover, a peculiar problem for AM is the carrier drift from the nominal IF; due to the intrinsic narrow bandwidth of the modulated signal, even a few hundred Hertz mismatch from the nominal IF highly deteriorates the signal quality. The tracking of the actual carrier frequency is obtained by an automatic frequency control (AFC) loop; furthermore, an automatic phase control (APC) is implemented, since ISB requires coherent demodulation. Thanks to the versatility of the system, the stereophonic audio can be extracted as well when in presence of compatible quadrature amplitude modulation (CQUAM) [11], which is the recognized standard for AM stereo. III. SYSTEM ARCHITECTURE The realization of a system capable of the advanced signal processing described in Section II, with an FPGA or uniquely with a powerful DSP, would be possible at expense of cost, area, and power consumption. For this reason, a DSP core together with several application-specific peripherals, which operate as hardware accelerators, compose the proposed system, as shown in Fig. 4. The system is fully synchronous, and all the clocks required by the peripherals are obtained by division of the master clock, generated by the on-chip oscillator, without any phase-locked loop (PLL). This is motivated by the fact that the A/D converter requires a low-jitter timing reference, as we will discuss in Section III-A2, which is not easily obtained by a PLL. The master clock is 74.1 MHz, twice the converter sampling frequency. This frequency value is selected in order to have no harmonics falling in the worldwide FM bandwidth (80–108 MHz). A significant requirement for the architecture is the modularity, i.e., the possibility to have two identical devices connected together. In this configuration, used in applications where high computational power is necessary, one chip acts as a master, and the second one as a slave. The former is responsible to generate the master clock, which is transmitted to the latter. The system, built under these constraints, is still synchronous.

SALA et al.: DESIGN CONSIDERATIONS AND IMPLEMENTATION OF A DSP-BASED CAR-RADIO IF PROCESSOR

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Fig. 5. Simplified A/D converter block diagram.

In the following, we describe the modules composing the system. A. Analog Blocks 1) IF Bandpass Sigma-Delta A/D Converter: The IF A/D converter is based on a multibit second-order sigma-delta bandpass modulator [12], whose block diagram is represented in Fig. 5. The converter is realized with a switched-cap (SC) technique, and it operates at a sampling frequency of 37.05 MHz, with a noise notch frequency centered at the IF. Two selfcalibrating control systems [13], one for the center frequency and one for the quality factor of the loop-filter, ensure in-band noise shaping accuracy, making the converter insensitive to temperature and process deviations from the nominal values. The differential input allows 4.0-V peak-to-peak maximum signal amplitude; the corresponding large impulsive input current, sunk by the SC input branch, is minimized by means of a switched buffer, thus reducing the disturbances injected back to the tuner. The modulator features 78-dB DR and 72-dB peak SNR, considering a 200-kHz FM bandwidth, in spite of the noisy power supply and ground reference due to the digital circuitry. This meets the system requirement for an FM demodulator (at least 75-dB DR). The intermodulation distortion (IMD) is 65 dB , for two in-band tones at 11 dB with respect to the full scale. 2) Clock Generation Unit (CGU) and Oscillator: The module generates all the clock signals for the system. The quartz-driven oscillator, whose block diagram is shown in Fig. 6, operates at the third overtone, generating the 74.1-MHz timing reference with a jitter of about 10 ps rms. This is a key requirement for an IF-sampling system, as it sets an upper bound on the achievable DR [14]; Fig. 7 shows this effect for the case under discussion. High stability over temperature variations is obtained excircuit. In slave mode, the oscillator ploiting a constantbehaves as a buffer, letting an external clock drive the device. The CGU is responsible for both controlling the oscillator and generating all the clocks for the peripherals, under DSP selection of phase relations. The CGU implements a self-trimming algorithm which sets the bias currents used in the oscillator cell; as a consequence, the master clock frequency is unaffected by process parameter variations and aging. 3) Tuner AGC-Keying Digital-to-Analog Converter: This current-steering D/A converter is used to generate an analog

Fig. 6. Architecture of the on-chip oscillator.

Fig. 7. jitter.

Upper bound to the IF A/D dynamic range due to the sampling clock

reference from the digital MPX level; the reference is used by the AGC of the tuner front-end. Since the AGC-keying signal is low-pass filtered in the tuner, the quantization noise is not critical; therefore, it is possible to make use of a standard 8-bit D/A converter. B. Digital Blocks 1) Digital Downconverter (DDC): The DDC module produces the complex baseband signal corresponding to the IF input. The DDC is chosen to be in hardware due to the high 37.05-MHz input data rate. A coordinate rotation digital computer (CORDIC) [15] in vectoring mode is used for downconversion; the CORDIC is an iterative algorithm for calculating trigonometric functions that, in binary arithmetic, does not require any multiplication. The resulting circuit is much simpler than the conventional derotator architecture, which consists of a direct digital frequency synthesizer (DDFS) and a complex multiplier [16]. The DSP can control the frequency

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Fig. 8. DDC transfer function. Top inset: zoom of the passband; bottom inset: zoom of the stop band.

shift with a resolution of 5 Hz to allow automatic tracking of the carrier frequency of the signal; this is an important feature for AM as explained in Section II-B. The DDC shifts the IF signal spectrum toward the null frequency while reducing the sample rate; moreover, it extracts the narrow band of interest from the wide-band input. This is accomplished by cascading a fifth-order cascaded integrator comb (CIC) filter [17] for high decimation, a 62nd-order FIR filter compensating the CIC in-band drop, and a 126th-order FIR, used to select the signal bandwidth of interest (about 260 kHz). The CIC filter decimates the input by a factor of 32 and its order is chosen to yield more than 85-dB alias rejection. Two downsampling equiripple FIR filters further decimate the signal by a factor of two each, resulting in a complex baseband signal at 289.45-kHz rate. The global transfer function is characterized by 1-mdB in-band ripple and 85-dB stop-band attenuation. The former avoids distortion due to induced amplitude modulations; the latter simplifies the design of the analog front-end, since only one expensive external ceramic filter is required. The resulting overall transfer function is shown in Fig. 8. 2) DSP Core: The preferred architecture is a super-Harvard, where the execution unit, memories, and peripherals operate independently and in parallel with the other units, thanks to separate dedicated buses. A transparent three-stage fetch–decode–execute instruction pipeline provides robustness to the software design, allowing latencies and data and instruction exceptions to be unimportant; likewise, the dedicated hardware for the do-loop and repeat commands introduces zero overhead, resulting in efficient and optimized branch operations. It is common practice to pay special attention to arithmetic precision when developing any processing on a fixed-point DSP, as an inappropriate data scaling could compromise its effectiveness. The 24-bit data path, the 56-bit accumulator, and the 48 48-bit double-precision multiplier allow a dynamic range large enough to neglect finite-arithmetic precision errors. As stated in Section I, the design has been driven by the need to have the maximum flexibility in software development, motivating the insertion of separate data and program RAM;

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in particular 12-kB program and 18-kB data RAM are allocated. Moreover, an additional 6-kB ROM is used for storing the startup boot software. However, as a significant portion of the memory space is used to store application software and filter coefficients, cost-effective solutions can be considered. Specifically, though being in contrast with the software radio concept, employing a ROM rather than RAMs is highly suitable for mass production, where the die area is a key issue. According to this option, but keeping the same functionality described in Section I, the program RAM could be reduced to 3 kB needed to run the software controlling the communication with the external world, whereas 6-kB data RAM is used to store intermediate data; as a consequence the ROM is enlarged to 27 kB. This would reduce the active area by 2 mm . Register direct, indirect, and special addressing modes are available. The special addressing category is composed by implicit address, immediate data, immediate short data, absolute address, absolute short address, short jump address, and input–output short address. The register indirect addressing mode allows programmable post-decrement and post-increment and indexing by an offset. The DSP core can access both the data and control registers of the peripherals by reading or writing a data memory location. A dedicated four-line serial interface allows bit-wise control of registers, program memory, and data memory, simplifying software development. 60 million instructions per second (MIPS) are necessary for the channel equalization, 50 MIPS for spike detection and suppression, and 20 MIPS for the weak-signal processing. This motivates the choice of designing a DSP system affording 148 MIPS of computational power. 3) AM/FM Detector: The AM/FM detector computes the amplitude and frequency information of the complex baseband signal, necessary for both AM and FM detection. The hardware implementation allows the demodulation function to be transparent to the application program, saving about 10 MIPS of processing power, which would be needed by a corresponding software routine implemented on the chosen DSP core. The detection is performed by a 24-bit accuracy CORDIC in rotating mode [15], using the arctangent FM demodulation technique. The CORDIC evaluates the phase and amplitude of the input complex number represented in Cartesian form. When the detector is working with FM, the phase signal is differentiated, yielding frequency demodulation. As the master clock frequency is much higher than the sample rate of the data to be processed, the best design choice is a serial realization of the algorithm [18]; in addition, the CORDIC implementation requires only summations and shifts. As a consequence, the resulting digital hardware is compact in size, and it can operate at 74.1 MHz. 4) Hardware Stereo Decoder: The stereo decoder extracts the left and right audio channels embedded in the FM stereo composite signal. A full-software approach would require 25 MIPS of processing power on the DSP core. The 19-kHz pilot tone is recovered by the hardware PLL to generate the 38-kHz subcarrier, which is necessary to decode the stereo MPX signal. Subsequently, the left and right components are decimated by a cascade of 12-tap and 74-tap FIR filters,

SALA et al.: DESIGN CONSIDERATIONS AND IMPLEMENTATION OF A DSP-BASED CAR-RADIO IF PROCESSOR

resulting in more than 85-dB alias rejection, in order to yield an audio sample rate at 36.18 kHz, which is an integer submultiple of the master clock. Additional hardware features of the stereo decoder are the automatic mono/stereo identification depending on the pilot level and the stereo blending for mixing the left and right channels. Likewise, digital filters are realized in hardware to evaluate the field strength used in the spike cancellation routine. High-cut filtering is implemented by a hardware first-order low-pass filter whose cutoff frequency is programmable depending on the signal quality. Emphasis compensation is achieved by a hardware first-order IIR low-pass filter with programmable characteristic, because of the different de-emphasis time constants for the USA, Europe, and Japan. All the relevant parameters used in the hardware module are memory-mapped registers accessible by the processor; this allows run-time trimming of the stereo-decoding functions depending on the whole system and on field measurements. 5) RDS/RBDS Demodulator and Decoder: This module recovers the inaudible data transmitted by most FM radio broadcasting stations, according to the RDS (for Europe) and RDBS (for USA) standards [10]. After bandpass filtering the MPX signal around the 57-kHz subcarrier, and doubling its sample rate by interpolation, the RDS/RBDS demodulator extracts the RDS data clock, RDS data signal, and quality information with selectable sensitivity. The decoder synchronizes the data bit stream to group- and block-wise information, using a flywheel mechanism, and executing also an error detection and correction algorithm. The flywheel mechanism is implemented as a 64-state finite state machine (FSM) introducing hysteresis in data synchronization; depending on the syndrome value and quality information, the FSM decides whether or not to call for a resynchronization. The RDS/RBDS information is then stored in a RAM buffer of 24 locations, ready for transmission to a microcontroller via inter-IC (I2C) bus or serial parallel interface (SPI), to be described in Section III-C2 6) Asynchronous Sample-Rate Converter (ASRC): The ASRC introduces flexibility to the system as it allows transmitting data to external units, whose data rate is different from the DSP one. The transmission is transparent, since there is no need to explicitly program the input and the output data rates; the ASRC achieves this by means of an automatic digital ratio locked loop (DRLL) [19], which evaluates the frequency ratio depending on the external bit clock. C. Digital Interfaces The proposed device is the core of the car-radio system, extensively exchanging data with other ICs. These typically use dedicated transmission protocols, depending on the amount of information to be transferred. The resulting demand for flexibility motivates the presence of several different communication interfaces. 1) Serial Audio Interface (SAI): The SAI is a peripheral devoted to digital audio transmission and reception. It ensembles a three-line bus, consisting of a serial clock, frame clock, and serial data line. Basically, it is an extension of the standard Inter-IC

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Fig. 9. IF processor chip photograph.

Sound (I2S) bus [20], featuring programmable serial and frame clock polarity, and MSB/LSB first selection. Two independent SAI modules have been instantiated for more flexibility; each SAI has a full duplex receive and transmit channel, and it can be selected to be either master or slave. In this way, the system is suitable for applications where the DSP elaborates audio data from an external digital device; moreover, thanks to the ASRC, one SAI channel can transmit to a different clock domain. 2) Inter-IC Bus (I2C) and Serial Peripheral Interface (SPI): These interfaces are commonly used in the car-radio for connection with a microcontroller, responsible for loading the program memory at startup, and for setting and monitoring the parameters of the signal processing. The I2C [21] is a standard bidirectional two-wire protocol used for communicating up to 400 kb/s with other I2C bus-compatible devices. Each I2C module can operate as both a receiver and a transmitter, using a selectable master–slave configuration. The SPI block is a four-line bus for inter-IC control communication, with separate input and output data lines; the use of this interface is in substitute of the I2C, with the drawback of using two more pins, but with the advantage of having a channel bandwidth up to 1 Mb/s. 3) High-Speed Serial Synchronous Interface (HS3I): The HS3I is a proprietary module used to transmit and receive data at 9.25 Mb/s per channel. It allows the use of the IF processor in applications like tuner and antenna diversity [22]. The communication is on a master–slave basis using four wires: a synchronization signal from master to slave and three bidirectional serial data lines. The synchronization signal is a frame clock with a programmable duty cycle; this allows the reduction of the in-band harmonic noise [23]. The protocol does not require the transmission of any bit clock, since the time reference is internally obtained by division of the master clock, which is generated by the on-chip oscillator in the master device and transmitted to the slave. IV. EXPERIMENTAL RESULTS The proposed device has been realized in a 0.18- m CMOS technology, featuring six metal levels, metal–metal capacitors, and double oxide thickness. The latter makes available both 0.18- m 1.8-V and 0.35- m 3.3-V MOS transistors. Fig. 9 shows a picture of the device taken at the microscope on which

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TABLE I DEVICE SUMMARY

Fig. 10. Module-wise breakdown of the current consumption and of the silicon area. DET indicates the AM/FM detector, STE is the Stereodecoder, INT is the set of the interfaces and the sample rate converter, and OSC is the oscillator.

the different modules have been indicated. The die active area is 15.2 mm . Table I reports the technological data of the implemented IC. Fig. 10 shows the module-wise breakdown of the silicon area and of the current consumption of the chip. This latter has been evaluated by simulation with the entire application for FM reception. Given that analog blocks are recognized to be critical for the system performance, the design of both the IF A/D converter and the oscillator has been formerly proven and qualified by dedicated test chips [12]. High-level description and simulation of the system have been used to assess the hardware and software partitioning, and the specifications for each digital module. The performance of the system, composed of an RF front-end for DSP car radios [24] and the proposed IF signal processor, has been verified using standard testing conditions. Multipath propagation and adjacent/alternate channels, which are major causes for FM interference, are considered in this paper, in order to underline the effectiveness of the equalization with respect to a nonequalized solution; the performance of the proposed system is comparable with or better than state-of-the-art analog receivers [25]. Table II reports the detailed testing conditions. The total harmonic distortion plus

TABLE II FM MEASUREMENT CONDITIONS

Fig. 11.

THD+N in multipath condition versus delay time.

noise (THD+N) of the demodulated audio has been measured, on a bandwidth of 15 kHz, since it is a common method to evaluate the audio quality. Fig. 11 shows the THD+N performance versus delay time in multipath conditions, which model the reception in urban and hilly areas; the parameters correspond to a reflection path distance varying from 7.8 to 12 km, with the receiver moving at 55.8 km/h. For short delays, there is a significant 9.8-dB improvement, less impressive for longer delays, due to the limited number of equalizer taps [26]. Fig. 12 represents multipath conditions, where the reflection path is fixed at 2.1 km and the receiver is moving at a speed varying from 11 to 220.2 km/h; in these situations, the equalizer yields up to 9.3-dB THD+N improvement. Figs. 13 and 14 show the behavior of the equalizer under neighbor channel conditions; in both the diagrams, while the desired channel field strength is fixed, the neighbor channel one is varied. When the interferer is weaker than the desired, the equalizer worsens the THD+N of 6–8 dB. This effect is due to the additional phase error induced by the adaptive filter. Nevertheless, adjacent channel suppression (Fig. 13) up to 34 dB and alternate channel suppression (Fig. 14) up to 40 dB is achieved. When the neighbor channel is considerably stronger than the desired, the

SALA et al.: DESIGN CONSIDERATIONS AND IMPLEMENTATION OF A DSP-BASED CAR-RADIO IF PROCESSOR

Fig. 12.

THD+N in multipath condition versus Doppler frequency.

Fig. 14.

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THD+N in alternate channel condition versus RF level.

ACKNOWLEDGMENT The device presented in this paper is the result of the collaboration among the authors and a large number of designers, all of them essential. The authors wish to thank all of them, in particular, P. Ruffino for program management, G. Boarin, P. Kirchlechner, and G. Roither for system definition, F. Adduci, M. Annovazzi, V. Belleville, A. Colaci, V. Colonna, G. Gandolfi, M. Hoidn, R. Kropf, and M. Scheulin for silicon design, M. Bricchi, J. Henkel, A. Hoffmann, and M. Schmidl for software design, M. Frey for system evaluation, S. Galantin and M. Tonella for the applications, F.A. Mancuso, P. Mastromatteo, and P. Volontieri for analog layout, and M. Porta and his team for top-level assembly and back-end.

REFERENCES Fig. 13.

THD+N in adjacent channel condition versus RF level.

equalization fails to converge due to the finite stop-band attenuation achievable by the adaptive filter.

V. CONCLUSION In this paper, a recently developed IF processor has been presented. Compared to analog receivers, the demodulation section has been replaced by a combination of an A/D converter and a DSP with hardware peripherals. The receiver digitally performs the channel filtering better than what is achievable by an analog system in terms of pass-bandwidth, constant group delay, in-band ripple, and stop-band attenuation. Furthermore, advanced signal processing including blind channel equalization is available thanks to the DSP; the equalizer yields multipath distortion mitigation and neighbor channel rejection. The device has been realized in a 0.18- m CMOS technology and it can be considered one step forward in the realization of the software-defined radio receiver in automotive industry.

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[11] Y. Sakaie and B. Premier, “An amplitude modulated stereo system,” IEEE Trans. Broadcast., vol. BC-26, pp. 125–132, Dec. 1980. [12] V. Colonna, G. Gandolfi, F. Stefani, and A. Baschirotto, “A 10.7 MHz self-calibrated SC multibit 2nd-order bandpass SD modulator,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2002, pp. 575–578. [13] G. Gandolfi, V. Colonna, M. Annovazzi, F. Stefani, and A. Baschirotto, “Self-tuning algorithms for high-performance bandpass switched-camodulators,” IEEE Trans. Circuits Syst. I, vol. 51, pp. pacitor 170–174, Jan. 2004. [14] H. Tao, L. Tóth, and M. Khoury, “Analysis of timing jitter in bandpass sigma-delta modulators,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 991–1001, Aug. 1999. [15] J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput., vol. EC-8, pp. 330–334, Sept. 1959. [16] Y. Ahn, S. Nahm, and W. Sung, “VLSI design of a CORDIC-based derotator,” in Proc. IEEE Int. Symp. Circuits and Syst. (ISCAS’98), vol. 2, 1998, pp. 449–452. [17] E. B. Hogenauer, “An economical class of digital filters for decimation and interpolation,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-29, pp. 155–162, Apr. 1981. [18] Y. H. Hu, “CORDIC-based VLSI architectures for digital signal processing,” IEEE Signal Processing Mag., pp. 16–35, July 1992. [19] R. Adams and T. Kwan, “A stereo asynchronous digital sample-rate converter for digital audio,” IEEE J. Solid-State Circuits, vol. 29, pp. 481–488, Apr. 1994. [20] I2S Bus Specification, Philips Semiconductor. (1996, June). [Online]. Available: http://www.semiconductor.philips.com/acrobat/various/ I2SBUS.pdf [21] I2C Bus Specification, Philips Semiconductor. (1996, June). [Online]. Available: http://www.semiconductors.philips.com/buses/i2c/ [22] L. C. Godara, “Applications of antenna arrays to mobile communications, Part I: Performance improvement, feasibility and system considerations,” Proc. IEEE, vol. 85, pp. 1031–1242, July 1997. [23] G. Boarin, F. Adduci, M. Oddicini, and S. M. Crudo, “High speed interface for radio systems,” Eur. Patent 02425547.3, Sept. 2, 2002. [24] TDA7515, RF front end for AM/FM DSP-car radios with IF sampling, STMicroelectronics. (2002, July). [Online]. Available: http:// www.st.com/stonline/books/pdf/docs/8933.pdf [25] TDA7511, AM/FM tuner for car radio and HiFi applications, STMicroelectronics. (2001, Nov.). [Online]. Available: http://www.st.com/stonline/books/pdf/docs/8334.pdf [26] J. R. Treichler, C. R. Johnson, and M. G. Larimore, Theory and Design of Adaptive Filters. Englewood Cliffs, NJ: Prentice-Hall, 2001, p. 204.

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Michele Sala was born in Busto Arsizio (Varese), Italy, in 1975. He received the M.S. degree in electrical engineering and computer science from the University of Illinois, Chicago, and the Dr.Eng. degree in electronics from the Politecnico di Torino, Torino, Italy, in 1999. He joined STMicroelectronics srl, Cornaredo, Italy, in 2000, where he has been engaged in the design and development of hardware and software digital radio systems. He has also contributed to technical papers on the study of electromagnetic fields generated by the lightning discharge. He is currently with the Car Communication Division, STMicroelectronics srl, where he is a Design Engineer.

Fabrizio Salidu was born in Novi Ligure (Alessandria), Italy, in 1975. He received the M.S. degree in electrical engineering and computer science from the University of Illinois, Chicago, in 1999 and the Dr.Eng. degree in electronics from the Politecnico di Torino, Torino, Italy, in 2000. In 2000, he joined STMicroelectronics srl, Cornaredo, Italy, as a Design Engineer. Within the Car Communication Division, he contributed to develop an innovative family of digital-IF car-radio receivers. His current activity is related to the study and implementation of high-end solutions for channel equalization in analog reception.

Fabrizio Stefani was born in Gallarate (Varese), Italy, in 1953. He received the Dr.Eng. degree in nuclear engineering from the Politecnico di Milano, Italy, in 1978. In 1979, he joined SGS-ATES, now STMicroelectronics, Cornaredo, Italy, where he was involved in the design of switch-mode power actuators. He later moved to the design of linear power amplifiers, becoming Design Manager of this section in 1988. In 1994, he took the responsibility of the Car Communication design covering the developments of RF front ends, A/D and D/A converters, and audio signal processing. He holds more than 20 patents and has contributed to several technical papers. He is involved in STMicroelectronics participation in programs at Italian universities, providing seminars and chairmanship of student thesis dissertations.

Christian Kutschenreiter was born in Kolbermoor, Germany, in 1974. He received the Dipl. in electrical engineering with specialization in telecommunications from the University of Applied Sciences of Rosenheim, Germany, in 2001. During his studies, he worked as an Electronic Technician on guided missiles and defense systems at Deutsche Aerospace AG, on single and multi-axis silicon micromachined acceleration/gyro sensors and on strapdown inertial navigation systems at the Daimler-Chrysler Research and Technology Center and at the European Aeronautic and Defense Company R&D. In 2001, he joined STMicroelectronics GmbH, Grasbrunn, Germany, where he has been engaged in system design, simulation and evaluation of digital radio systems. He is currently with the European Automotive Design Center in the department of Integrated Circuits Car-Radio Applications, STMicroelectronics Gmbh, where he is a Design Engineer.

Andrea Baschirotto (M’95–SM’01) was born in 1965 in Legnago (Verona), Italy. In 1989, he graduated in electronic engineering (summa cum laude) from the University of Pavia, Italy. In 1994, he received the Ph.D. degree in electrical engineering from the University of Pavia. In 1994, he joined the Department of Electronics, University of Pavia, as a Researcher (Assistant Professor). In 1998, he joined the Department of Innovation Engineering, University of Lecce, Italy, as an Associate Professor. Since 1989, he has collaborated with STMicroelectronics, Cornaredo, Italy, on the design of ASICs. Since 1991, he has been associated with I.N.F.N. on the design and realization of read-out channels for high-energy physics experiments and space experiments. He collaborated with SMIs for the design of mixed-signal ASICs. His main research interests are in the design of mixed analog/digital integrated circuits, in particular for low-power and/or high-speed signal processing. He has authored or coauthored more than 40 papers in international journals, more than 50 presentations at international conferences, and three book chapters, and holds ten industrial patents. In addition, he has coauthored more than 120 papers within research collaborations on high-energy physics experiments. Dr. Baschirotto was a guest editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II for the special issue on IEEE ISCAS 1998, and he is now serving as an Associate Editor. He has been the Technical Program Committee Chairman for ESSCIRC 2002 and he is a guest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS for ESSCIRC 2003.