Design Considerations And Implementation Of Very Low ... - IEEE Xplore

Design considerations and implementation of very low frequency continuous-time CMOS monolithic f ihers Y.Papananos T. Georgantas Y.Tsividis

Abstract: ‘The design of low frequency continuous-time filters is considered. Problems encountered at such frequencies are discussed, along with possible solutions. Two case histories reporting experimentally verified designs are presented to show that good quality low frequency filters can be designed reliably in CMOS technology.

1

Introduction

It is often believed that as the frequency of operation of a system is reduced the design becomes easier and fewer problems are encountered. This is not true, especially for frequencies below 1 kHz. Some of the problems encountered have already been addressed in [ 1-41, The literature, though, basically deals with the implementation of very large time constants in CMOS technologies [l-41. As far as these authors know, the only high order filtering systems that have appeared operate at frequencies above 1kHz (e.g. [5]). In this paper, an attempt is made to review the specific problems encountered in the design of low frequency filters and to propose various solutions. The dominant problem comes from the large time constants involved: values of resistors and capacitors are limited by the silicon area available, and therefore techniques to overcome this problem have to be investigated. Parasitic elements are another problem directly connected to the large size of the devices. Here, special compensating techniques have to be utilised to eliminate the deterioration in performance due to parasitics. Finally, the flicker noise of active elements gives rise to noise problems and reduces the dynamic range of the systems. 0 TEE, 1997 IEE Proceediizgs online no. 19970908 Paper first received 1 Ith January and in revised form 7th June 1996 Y. Papananos and T. Gcorgantas are with the Department o l Electrical and Computer Engineering, National Technical University of Athens, 157 73 Zographou, Athens, Greece Y. Tsividis was with the National Technical Universitv of Athens and is now with the Department of Electrical Engineering, Cdlumbia University, New York, N Y 10027, USA 68

2 Obstacles to l o w frequency design - a brief review

Element values: The dominant cause of problems in low frequency integrated filters is the size of the filter elements. In such filters, critical frequencies are determined either by RC products [6] or by CIG, ratios [7], where G,,, is the transconductance of a transconductor. Consider, for example, an integrator with a unity-gain frequency of 100Hz. Even if a lOOpF capacitor is used in it (which may be unacceptably large in some integrated filter applications), the required R or IIG, value will be as high as 16MQ. If R is implemented by a triode-operated MOSFET, or if G,, is implemented by a saturation-operated MOSFET (we assume for now, that no resistance multiplication or transconductance reduction techniques are used), we will have

where ,U is the carrier mobility, C‘,, is the oxide capacitance per unit area, V,, is the control voltage at the gate of the transistor, VT is the threshold voltage and L and W are the channel’s length and width, respectively. If, now, pCo, = 70jAIV2 and V C s - VT = 2V, the resulting value of Li W is 2200. Even if a W as small as 1 pm is used (which may not be desirable due to matching considerations), L would be equal to 2.2mm, which is huge by IC standards. Parasitic capacitance: The large MOSFET channel length values discussed above give rise to large channelto-gate and channel-to-substrate parasitic capacitance. This is true in both the triode and saturation regions. As an example, let us consider a MOSFET in the triode region (with zero drain-source voltage), which is easier to model. This device can be viewed as a uniform RC transmission line for small signals [8, 91). The total resistance of this transmission line is the small-signal drain-to-source channel resistance as described in eqn. 1. The total capacitance is the parallel combination of the channel-to-gate oxide capacitance CoxWL and the channel-to-substrate depletion capacitance. It is obvious that this parasitic capacitance is proportional to the channel length L and, therefore, it is dominant in long channel devices which are used in low frequency applications. For the above numerical example, assuming a gate oxide capacitance of lfFipni2 and neglecting substrate capacitance, the parasitic channel capacitance C,, = 2.2pF. IEE Pro? -Cirruits Devices Syst., Vol. 144, No. 2, April I997

From distributed RC' network theory, the transfer funclion of the integrator shown in Fig. 1 (ignore, for the moment, the part shown in broken lines), at frequencies well above the dominant pole frequency of the integrator, can be approximated by [9]

where ('10 = IIRC and cup = 6/RC,. For a given C, w0 is inversely proportional to L through R; however, depends on L through both R and C;, and is thus inversely proportional to 1/L2. Thus

(3) Sincc for low frequency filters L is large, cuIj/cuo can be dangerously small and a need for compensation arises. For our numerical example, cup/cuo 43. Assuming w 1). The transfer function of the circuit is

where A(s) is the gain of the op-amp. As can be seen from this equation, the DC gain of the integrator is reduced by a factor of /3, and this may cause problems in the implementation of high Q filters since it results in a larger phase lead error at coo. A final undesirable effect with electronic multiplication concerns noise. Although the resistor RMS noise voltage is decreased d/3 times, the voltage gain from this noise to the output is increased by B; thus, the output thermal noise voltage is proportional to dp. Active element considerutions: In low frequency applications, the impedances that are being driven are sufficiently higher than the op-amp's output impedance and, therefore, simple op-amps will be adequate. In some cases this can lead to the complete elimination of the output stage of the active element which leads to the replacement of the op-amps by simple OTAs (operational transconductance amplifiers). The high impedance levels of the design may also lead to low power consumption. In ASIC design, where library elements must be used, at low frequencies it is easy to compose a balanced-output op-amp out of two single-ended opamps (one connected as an inverter at the other's output), since the excess phase of an inverter will be negligible at such frequencies. Owing to the low frequencies of operation, the flicker noise of the MOS transistors must be paid special attention. At these frequencies, the input referred noise of the active element is mainly due to the flicker noise which dominates over the thermal noise. However, the llf noise of the MOS transistors operating in the triode region in a perfectly balanced structure is absent [12], at least if the signal excursion is small. 69

3

Case histories

Two design examples based on the MOSFET-C approach are now presented. Different design techniques have been employed, demonstrating the various issues presented in the preceding Section. The experimental chips have been fabricated by Mietec-Alcatel in both cases. single- ended to balanced converter

i

175 f 2.5Hz to reject the harmonics introduced by the 50Hz power network signal; the passband ripple can be large (< 4dB). These specifications were met by a sixth order Butterworth bandpass filter. For low passband sensitivity the leapfrog active filter configuration has been employed, as shown in Fig. 4. A modification [lo] of the biquad structure presented in [9] was used to implement high-Q biquads. Table 1: Measurement results for BP filter chip

1

J

-L

n

Characteristic

Initial Spec.

Measured Results

Passband ripple, d B

40

43

3 dB bandwidth, Hz

5

5

Centre frequency, Hz

175 * 2.5

175

Operating temperature, "C

0-70

0 - 70

THD for 1 V, output, %

1

0.36

Dynamic range, dB

40

63

PSRR (at 100 Hz),dB

40

45

1.5

For the implementation of a balanced op-amp we used two single-ended standard cell op-amps, as discussed in [6]. Since the filter operates at low frequencies, the standard cells provided by the foundry were adequate for this application. Although a very low power dissipation would have been possible at such low frequencies, we did not need to design low power op-amps as the power dissipation specification was not stringent (40mW). All integrating capacitor sizes were chosen to be 50pF. All transistors used as voltage-controlled resistors were chosen to be p-channel devices 3 pm wide and 9 0 0 p long @-channel devices have lower mobility, and thus a smaller channel length can be used). The total chip area is 6 x 4.5mm2. The chip microphotograph is shown in Fig. 5.

11.65

P-

R -rc=l)1

big. 5

Fig.4

Schematic diagram of lecpfiog BPJilter

Capacitances are in pF

3. I

Bandpass filter

An experimental bandpass filter has been designed and implemented in a 5V, 2 . 4 CMOS ~ technology. It is to be used in a system that selects a specific control signal carried over the public electrical network lines. The fundamental frequency of this signal is 175Hz. The filter must meet stringent frequency response requirements (see Table 1) with centre frequency at 175Hz, a bandwidth of 5Hz and 4 0 d B attenuation at 70

Bcindpass jilter microphotograph

The filter tuning system was of the well known indirect type which has proved successful in many commercial products. Our implementation of this scheme is shown in Fig. 6. Despite the fact that the high-Q value (= 35) of the implemented filter should point towards the utilisation of a separate Q tuning system [13], simulation and experimental results show that the filter operates satisfactorily in the temperature range 0 70°C even with the simple tuning system of Fig. 6 (see below). The principle of operation is as follows. The integrated tuning scheme (Fig. 6) references an on-chip resistor (R+J, realised by the same four-transistor combination as the one used for ~

IEE Puoc.-Circuits Devices Syst., Vol. 144, No. 2, April 1997

the filter resistors, to an external high quality resistor (RexJ.Since the gate voltage V,, (see Fig. 2) of one MOSl pair is always tied to the negative supply line, the value of Rthlpis controlled through the voltage V , generated by the tuning circuit. Rthlpis ratio-matched to the filter resistances and situated in close proximity to them; applying the same control voltage V,, to all other MOS resistors on the chip forces them to the desired values. :

:

1

.

L

temperature range. Also the filter's passband is quite constant (-5Hz) at all temperatures. The variation of the filter's gain measured at the centre frequency against temperature is shown in Fig. 8b. It can be seen that the gain is within specifications at all temperatures. The filter's Q is as high as desired and stable. 180,

8

7

1176

P

L

172 1701

0

I

10

20

30

LO

50

I

I

60

70

60

70

a

m U

-L

Fig.6

In(!

01

Tuning system of BPJilter

0

To account for small variations in the nominal values of the fabricated MOS resistors and capacitors, Re,, must be adjusted once until the frequency response is as desired. The low temperature coefficient of Re,, and the integrator capacitors makes further adjustment of to compensate variations due to temperature unnecessary. The scheme works properly in the temperature range of interest for the known variations of several process parameters, as will be demonstrated by the measurements below. The measured frequency response of the filter is shown in Fig. 7 and is as expected from the computer simulations of the circuit. A summary of the measured results is provided in Table 1.

75

Fig. 7

30

175

275

frequency, Hz Frequency response o j BP filter

The measured behaviour of the filter against temperature is shown in Fig. 8. The shifting of the centre frequency and also the upper and lower 3dB frequencies against temperature are shown in Fig. 8a. The measurements cover the entire range from 0 to 70°C and, as can be seen, the centre frequency is quite stable and within the specifications (175 22.5Hz) for the above IEE Proc -CircuitA D ~ V I LSyAt ~ A, Vol 144,No 2 April 1997

Fig.8

I

10

20

,

30

LO 50 temperature, deg C

1

b Measurement hehuviour oj,filteraxinst temperature

Centre frequency and band-edge frequencies againrt temperature h Gain against temperature -e- upper 3 dB frequency -0centre frequency -Alower 3dB frequency U

The above results are very satisfactory taking into account the high Q value realised from this filter, the sensitivities of several filter parameters due to this fact, and the fact that no automatic Q-tuning was used.

3.2

Band-reject filter

3.2.I Filter topology and design: The purpose of the low frequency band-reject filter presented here is to reject strong interference from ambient light during measurements in an optical sensor system [14]. The frequency of the interfering signal is 100 Hz (fundamental frequency of the power resulting from a 50Hz voltage or current), whereas the signal to be measured is between 8 and 15Hz. The latter is a DC voltage chopped at one of the above frequencies and comes from an LED source sensed through a photodiode. The basic filter constraints with respect to the transfer function were: ( a ) flatness in the lower passband to ensure that the passband gain will not vary in the implementation (low Q); (6) a minimum of 40dB attenuation at 100Hz. To absorb integrated element tolerances, a bandreject solution was selected. The BR shape is formed by connecting two symmetrical notch biquads in cascade as shown in Fig. 9. The two notch frequencies are 5Hz apart at -100Hz. A simple notch biquad is then used as a master filter for tuning purposes, as will be explained later on. For each biquad a lowpass symmetrical notch response was used, since the demand is to reject only one frequency; this type of response provides good attenuation at this particular frequency, 71

v

U

T

-b

VC

Fig. 9

VC

Block diagram of band-rejectfilter

while it keeps the complexity of the implementation as low as possible. A recently proposed generic biquad structure [7] was used. This biquad utilises eight resistors in total (four less than the Tow Thomas biquad). As far as the sensitivity is concerned, the two topologies are quite similar: SPICE simulations have shown for both cases a 5dB change in attenuation at the notch frequency when any one resistor's value varies by 0 . 2 % ~

lor

technique illustrated in Fig. 1 was used. The improvement in performance is obvious. Table 2: Measurement results for integrated op-amp Characteristic

Measured Results

DC open loop gain

74dB

Unity gain frequency

2.1 MHz

Input offset voltage

3m V

Output resistance

20 kQ

Slew rate

5viys

CMRR (at 1 kHz)

59dB

Output s w i n g (diff.)

THD (unity gain, 1V,-,

m 73

:;:I

Power supply voltage

+ 2.5V

Power dissipation

3.7 mW ~

,

,

,

,

60

70

80

90

,

,

,

,

,

,

-80

50

4.5v,_, at 1kHz) 0.1%

100 110

120 130 1LO 150

a

m TJ

~~~~

~

The schematic diagram of the op-amp used is shown in Fig. 11. It is a fully balanced structure suitable for MOSFET-C filter implementations and it uses a dual common-mode feedback loop architecture to obtain good output balancing even at high frequencies. The basic measurement results of the op-amp are shown in Table 2. The amplifier has been fabricated using Mietec's 1 . 2 CMOS ~ analogue process.

-

1 ~

In contrast to the previous design example, in this filter we did not employ the structure of Fig. 2; thus, the distributed capacitance effects had to be carefully investigated. The long-channel devices were broken into a number of series-connected transistors. In Fig. 10, the frequency responses of the uncompensated and compensated notch filter are shown. The compensation 12

"SS

L

I

Fig. 11 Fully balunced operational amplifier

In the final design, a capacitor value of 95.5pF was selected. This value kept the total on-chip capacitance IEE Pioc.-Circuits Devices Syst., Vol. 144, No. 2, April 1997

to practically implementable levels while allowing for ~ moderate transistor channel lengths ( L = 3 3 0 for Mietec's 1 . 2 CMOS ~ technology; W was 3pm). This particular L value, along with frequency compensation, limited the frequency response degradation and provided attenuation levels of more than 60dB at the notch frequency, as indicated by simulation. Taking into (account mismatches (.+0.5'1/0 from nominal R and C values), the maximum attenuation deviation observed in simulation was 4dB. The nominal value of the control voltage V , was selected along with the nominal L value for RC tracking, taking into account all fabrication process and temperature variations (0 70°C 1. Considering all possible extreme cases, simulation results proved that the value of V , remained within the acceptable limits for the range of signals considered in the optical measurement application. An indirect tuning scheme was used for automatic tuning. Owing to the steep frequency behaviour of the notch, biquad and to absorb fabrication process tolerances, the main filter was selected, as already reported, to be a band-reject filter consisting of two notch biquads connected in cascade. The zeros of the two biquads are -5Hz apart and around a 100Hz nominal value. The tuning filter is a simple symmetrical notch biquad. The nominal values of the MOS transistors (resistors) were selected in such a way that the notch of the directly tuned filter lies between the two notches of the BR filter. The overall system schematic diagram is shown in Fig. 12. The tuning mech,anism operates as follows. The output of the first op-amp of the tuning biquad shall exhibit 90" phase difference with respect to the pilot signal when locked (at a frequency of 100Hz). The two signals are converted to square pulses through simple inverters and are passed to a phase detection circuit (an exclusive-OR gate). The output of the XOR gate is integrated to produce the control signal V,. Owing to the low frequency range of the system, the integrator's time constant must be very large and therefore the integrating capacitor must be > 100nf. Therefore, the integrating capacitor is externally connected to the chip. As seen in Fig. 12, the control voltage V , is applied to both filters. Two modes of operation are provided, as is now explained. (a) Uninterrupted mode o j operation: Here, the main filter is always in the signal path and the tuning filter is tuned continuously: the tuning loop is always closed. Switches rpl and q2 are closed, allowing the signal to

pass through the BR filter and the pilot signal to pass through the notch filter, respectively. Switch rpp5 is closed. When switches rp3 and rp4 are closed, the tuning loop is activated. At the beginning of a filtering session, cp3 is open (complementary rp3 closed), so the integrating capacitor is discharged. (b) Interrupted mode of operation: In the uninterrupted mode of operation just discussed, the pilot signal can interfere with the signal path and can pass to the output of the main filter. To avoid this effect, the pilot signal can be isolated by opening switch rp2 and turning off the automatic tuning loop by opening switch rp4. The control voltage can then be stored on an external capacitor Choldfor a limited period of time. The external storage capacitor must be large enough so that leakage currents produce negligible droop in the voltage across it, for the period between successive tuning operations. Meanwhile, the switch rpl opens (complementary q1 closes) so the integrating capacitor is discharged. When a new tuning session is about to begin, switches cpl and rp5 are opened, so the signal path is cut off and switches rp2, rp3 and (p4 are closed so the tuning loop is activated again. The control voltage is refreshed on Choldand the filtering session is repeated. The system has been fabricated using Mietec's 1 . 2 ~ analogue CMOS technology. A chip microphotograph is shown in Fig. 13. The BR filter is separated from the notch filter via a grounded stripe to reduce crosstalk. The total silicon area of the system is 2.6 x 3.4mm2. The measured frequency response of the filter is shown in Fig. 14. The filter notch is tunable from 33 to 265Hz (at room temperature). In Fig. 15 the output spectrum of the filter in the uninterrupted mode of operation is shown. The 100Hz frequency component (pilot signal) is seen at the output. In the interrupted mode of operation, this component disappears. The basic measurements on the band-reject filter are shown in Table 3 . 4

Conclusions

Various problems about the integration of very low frequency filters have been reviewed and techniques to overcome them have been discussed. Simulation results and experimental measurements on two fabricated chips implementing L F filtering systems have indicated that high quality, low frequency systems can be implemented reliably in monolithic form using the solutions discussed.

=

extern a I

/

master-out

pilot

(notch) I

VP

I

-$.

Chold

O?

Fig. I>!BR schematic diugvum with automatic tuning IEE ProcCircuits Devices Syst., Vol. 144, No. 2,Aprrl 1997

13

Table 3: Measurement results for BR filter chip

Fig. 13

Characteristic

Measured Results

Supply voltage

c 2.5V

Tunable range

33 - 265 HZ

Attenuation at 100Hz

50dB

Pilot signal feedthrough

-65dB

Second harmonic

-45 d B

Total noise ( I O - 11OHz)

0.6mV

Dynamic range

50dB

5

BR microphotograph

Acknowledgments

This work was supported by ESPRIT projects 5692 HVLSI-DPE and 7101 MInOSS. 6 1

2 3

4 5

I

200

10 frequency, H z

6

Fig. 14 Frequency response ofBRj2ter 7

8 9 10 11

12 13

1

-1201 10

I

100 frequency,

Fig. 15

14

I

150

Hz

Output spectrum oj BRfilter (uninterrupted mode of operation)

14

References SHAH, P.: ‘Design of analogue integrated circuits for very low frequency signal processing’. PhD dissertation, Techn. Univ. Denmark, Nov. 1993 DEGUELLE, W.: ‘Liinitatons on the integration of analog filters for frequencies below 10 Hz’, IEEE-ESSCIR, 1988, pp. 131-134 MUELLER, P., et al.: ‘Design and fabrication of VLSI components for a general purpose analog neural computer’, Analog VLSI implementation of neural systems (Kluwer Academic Publishers, 1989) pp.135-169 STEYAERT, M., KINGET, P., SANSEN, W., and VAN DER SPIEGEL, J.: ‘Full integration of extremely large time constants in CMOS’, Electron. Lett., 1991, 27, (lo), pp. 790-791 KAISER, A.: ‘A micropower CMOS continuous-time low-pass filter’, IEEE J. Solid-state Circuits, 1989, SC-24, (3), pp. 736-743 BANU, M., and TSIVIDIS, Y.: ‘Fully integrated active R C filters m MOS technology’, IEEE J. Solid-State Circuits, 1983, SC18, pp. 644651 VOORMAN, J.O.: ‘Continuous-time analog integrated filters’, in TSIVIDIS, Y.P., and VOORMAN, J.O. (Eds.): ‘Integrated Continuous-Time Filters’, (IEEE Press), pp. 1 5 4 6 TSIVIDIS, Y.: ‘Operation and modeling of the MOS transistor’ (McGraw-Hill Book Company, New York, 1987) KHOURY, J., and TSIVIDIS, Y.: ‘Analysis and compensation of high-frequency effects in integrated MOSFET-C continuous-time filters’, IEEE Trans., 1987, CA-34, pp. 862-875 CZARNUL, Z.: ‘Modification of the Banu-Tsividis continuoustime integrator structure’, IEEE Trans., 1986, CA-33, pp. 714716 ISMAIL, M., and RUBIN, D.: ‘Improved circuits for the realization of MOSFET-capacitor filters’. Proc. IEEE Int. Symp. Circuits and Systems, San Jose, 1986, pp. 1186-1189 VAN DER PLAS, J.: ‘MOSFET-C filter with low excess noise and accurate automatic tuning’, IEEE J. Solid-State Circuits, 1991, SC-26, (7), pp. 922-929 SCHAUMANN, R., and ALI TAN, M.: ‘The problem of onchip automatic tuning in continuous-time integrated filters’,Proc. IEEE Int. Symp. Circuits and Systems, 1989, pp. 106-109 O’LEARY, P.: ‘ Signal processing for sensor systems’, MInOSS Workshop, MInOSS Consortium, Vienna, Nov. 1993

IEE Proc-Circuits Devices Syst., Vol. 144, No. 2,April 1997