Design, Modeling and Characterization of Embedded Capacitors for Decoupling Applications Prathap Muthana, Ege Engin, P.M. Raj, Madhavan Swaminathan, Rao Tummala, Venkatesh Sundaram Georgia Institute of Technology Atlanta, Georgia 30332 Email: prathap, engin, raj, madhavan.swaminathan @ece.gatech.edu
Daniel Amey, Karl Dietz, Sounak Banerji Dupont
IBM Technical Contact: Moises Cases IBM Austin Research Lab Email:
[email protected] Abstract— Surface Mount Discrete (SMD) decoupling capacitors fail to provide decoupling above 100MHz. This paper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from 100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and board capacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/ground planes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented. The performance of 2 different embedded package capacitor technology’s from Dupont and the Packaging Research Center(PRC) will be investigated in this paper.
I. Introduction The International Roadmap for Semiconductors (ITRS) has projected an increase in the power consumption of microprocessors for future technology nodes [1]. For chips with a feature size of 90nm, supply voltage of 1.2V and chip size of 140mm2, the power dissipation is expected to be 84W. Table I shows the variation of different microprocessor parameters for cost performance applications for the 90, 65 and 45nm nodes. The power delivery network (PDN) provides the power supply to the processor. If improperly designed this network could be a major source of noise, such as ground bounce and electromagnetic interference (EMI) [2]. A methodology for designing a good PDN is to define a target impedance for the network that should be met over a broad frequency band [3]. This parameter can be computed by assuming a 5% allowable ripple in the voltage supply and a 50% switching current in the rise and fall time of the processor clock [2]. Target impedance can be calculated as Vcore × 0.05 Z= (1) Iavg × 0.5 where Vdd is the core voltage of the processor and I is the current drawn by the microprocessor from the PDN. The target impedance listing for the 90, 65 and 45nm technology nodes is listed in Table I. The current can be calculated from the power and voltage as P = Vcore Iavg
(2)
TABLE I VARIATION OF PROCESSOR PARAMETERS THROUGH TECHNOLOGY NODES Year 2004 2007 2010
Feature size(nm) 90 65 45
Power(W) Vcore (V) 84 103.6 119
1.2 0.9 0.6
Iavg (A) 70 115.11 198.33
Target Impedance(mΩ) 1.7 0.781 0.302
As the processor is powered through the board and the package, the design of the PDN in both these levels is extremely important. Decoupling capacitors play a very important role in the PDN as they act as charge providers for the switching circuits. The target impedance has to be met over a broad frequency band; the low frequency, mid frequency and high frequency capacitors need to be appropriately placed to meet this requirement. This paper will analyze the performance of mid frequency band decoupling capacitors in the PDN. II. Limitations of SMD’s SMD capacitors provide good decoupling up to around 100MHz. Fig. 2 shows the response of 3 SMD capacitors placed at a port of reference (solid line) in a 10cm by 10cm plane. The response of the same capacitors placed 10mm away from the port is also shown as dashed lines in Fig. 2. It can be clearly seen that the performance of capacitors is dependent on its placement on the plane. The sensitivity of capacitors performance to its placement is also highlighted in [4]. This trend is further magnified in a decoupling capacitor network. To highlight the limitations of SMD’s, a decoupling network was designed to meet the target impedance for the 65nm node. The response of the network is shown in Fig.1. It can be seen that the inductance of the SMD capacitor network dominates the response close to 100 MHz. This problem cannot be addressed by using on-chip capacitors, since the amount of on-chip capacitance that can be added is limited to the real estate on-chip. This is a limitation for using on-chip capacitors at low frequencies. An increase in the amount of decoupling capacitance will increase the cost and the size of the chip [5] . Therefore, the low inductance combined with
Fig. 3.
Fig. 1.
Embedded discrete capacitor in BT laminate
Decoupling limitations of SMD’s
Fig. 4.
Cross section of a discrete capacitor
can be decided by the ESR of each type of capacitor and the target impedance to be met Fig. 2.
Sensitivity of capacitor performance with position.
the low capacitance make on-chip capacitors viable only for high frequency decoupling. For decoupling above 100MHz embedded capacitors in the package have shown good performance. Embedding capacitors in the package, positions them closer to the chip reducing the inductance associated with the capacitors. Reduced inductance coupled with high capacitance improves the decoupling performance. The design of an embedded capacitor network using the Packaging Research Center (PRC) and Dupont’s thick film capacitors will be highlighted in this paper. As shown in this paper, the embedded capacitor array shows decoupling performance degradation at around 2GHz due to its inductive nature. For decoupling frequencies higher than 2GHz, on-chip capacitors would be required. The amount of on-chip capacitance required that would maintain the required target impedance is decided by the frequency response of the decoupling networks on the package and the board at 2GHz. From the table it is evident that the target impedance is decreasing with an increase in the technology nodes. The methodology for meeting the target impedance is to place decoupling capacitors in the PDN. The number and type of decoupling capacitors required depends on the frequency band to be targeted and the equivalent series resistance of each individual capacitor. The number of capacitors of each type
Ncap =
T argetImpedance ESRcap
(3)
The architecture of a possible capacitor array in the package is also described in this paper. The PDN is designed to meet the target impedance of 0.78mΩ for the 65nm technology node as listed in Table I. III. Embedded Capacitor Technology A brief introduction to the discrete capacitor technology used in this paper will be presented in this section. A. Thick film capacitor technology These thick film capacitors are available from Dupont. These capacitors are compatible with the standard FR4/BT laminate printed wiring board technology and can be integrated in BT laminate as shown in Fig. 3. The cross section of the capacitor is shown in Fig. 4. The thickness of the dielectric is in the range of (20um-24um), and the dielectric constant is 3000. The loss tangent of the dielectric at 1MHz is less than 0.05. The top copper electrode and the bottom electrodes are 5um and 30um thick respectively. These capacitors are available on a copper foil with discrete patterned dielectrics and top electrodes. The process ground rules define the maximum and minimum size of the capacitors which translate to 0.5mm and 3mm a side respectively.
Fig. 5.
Fig. 6.
Cross section of a barium titanate capacitor
The measurement set up for characterizing the capacitors. TABLE II
E XTRACTED CAPACITOR PARAMETERS FROM MEASUREMENTS
B. Hydrothermal Capacitors These thin-film Barium Titanate (BaT iO3 ) capacitors are fabricated using a hydrothermal process at the Packaging Research Center(PRC). Nanograined ultra thin crystalline Barium Titanate thin films were synthesized on laminated copper foils using the low cost low temperature (¡ 100oC) hydrothermal process. Hydrothermal synthesis of BaT iO3 involves treating Ti-coated copper clad laminates with Ba2 + ions in highly alkaline solution at 95o C. With this method high K thin films can be integrated into organic packages using standard printed wiring board processes such as lamination and lithography. The resultant 300nm thick films exhibited a dielectric constant close to 300, loss tangent less than 0.06 and a capacitance µF density greater than 1 cm 2 [6]. The size of the grains of the Barium Titanate varies from 60nm to 80nm. The top electrode is 2um thick copper and the bottom electrode is 12um copper with 500nm of Titanium. IV. Capacitor Measurement and Characterization A 2 port frequency domain measurement methodology was used to measure the impedance of the capacitive structures[7]. The method will be briefly described in this section. The measurement equipment included Agilent’s 8720ES vector network analyzer(VNA) with a bandwidth of 50MHz to 20.5GHz and 500um GS-SG cascade probes. A standard SOLT (Short,open,load and thru) calibration was carried out on the probes using the ISS substrates. The basic equations used to characterize these structures are given below– Re(dut) = 25 ×
(Re(S21) × (1 − Re(S21)) − Img(S21)2 ) ((1 − Re(S21)2) + Img(S21)2 ) (4)
Im(dut) = 25 ×
Img(S21) ((1 − Re(S21)2 ) + Img(S21)2 )
(5)
where Re(dut) and Im(dut) are the real and imaginary parts of the device under test. The measurement set up for characterizing the capacitive structure is shown in Fig. 6. Probe1 is the transmitter and probe2 measures the voltage drop across the device in one measurement cycle. The functions of the ports are reversed in the next measurement cycle of the
Capacitor Size(mm×mm) 1.198×1.198 2×2 5×5 10×10
ESC(nF)
ESL(pH)
ESR(mohms)
2.84 8.772 53.93 191
42.6 23.8 22.1 24.1
16 10.36 7.22 5
VNA. S21 is the insertion loss measured across the device at each frequency point. By calculating the real and imaginary parts of the device the impedance profile over the measured frequency band can be obtained. V. Modeling of the capacitive structure The capacitors were modelled using the transmission matrix method (TMM)[8]. This tool has been previously used to model power plane structures[9],[10]. In the transmission matrix method the power plane is divided into unit cells. Each unit cell consists of an equivalent circuit with R, L, C and G components and are cascaded together in a Π or T network. Further details regarding the set up of the transmission matrix can be found in [8]. In modeling the capacitive structures the fringing effects have been ignored because of the large aspect ratio of these structures. Fig. 7 shows the impedance profile of different capacitors that were measured using the 2 port methodology. Fig. 8 shows the extracted dielectric constant value, it remains relatively constant as observed from the figure. Fig. 9 and Fig. 10 show the model to hardware correlation of a 2mm × 2mm and 3mm × 3mm capacitor that were measured and modeled. Ports were appropriately defined in the model to get the correct model to hardware correlation. The definition of the ports corresponded to the exact coordinates of the probes on the measurement structure. The parasitic inductance of the probe set up had to be included in the model to get a good correlation between the model and measurement. The details of the parasitic inductance extraction and model to hardware correlation is given in [11]. The capacitance, inductance and resistance of the various sized capacitors were extracted from the measured results and are listed in Table II. The measurement and modeling results of a 2.1mm diameter circular and a 1mm a side square barium titanate capacitor are shown in Fig. 11.
Fig. 7.
Fig. 8.
The impedance profiles of different sized capacitors. Fig. 9.
Model to hardware correlation of a 2mm × 2mm capacitor.
Fig. 10.
Model to hardware correlation of a 3mm × 3mm capacitor.
The variation of dielectric constant with frequency.
VI. Capacitor integration in a package This section highlights the integration of the Dupont and hydrothermal capacitors in a package. The different enabling technologies have been highlighted in this section. A. Dupont Capacitor Integration Technology This section highlights the technology for the integration of the Dupont capacitors in a package. The cross section of the proposed package is shown in Fig. 12. The package consists of a core of thickness 0.6mm shown in Fig. 13. The core is split into 5 constituents- core 1, core 2, core 9,core 10 and a core laminate. Cores 1, 2, 9 and 10 are BT glass layers that are 100um thick,the thickness of the core laminate is 0.2mm. The total thickness of the structure excluding the metal levels is 600um. The build up layers are added to the core in Fig. 13 to get the complete package stack up in Fig. 12. The thickness of
Fig. 11.
Measured and modeled impedance profiles of BaTiO3 capacitors.
Fig. 14. Fig. 12.
Perspective view of the embedded capacitors in the package.
Cross section of the proposed package with discrete capacitors.
Fig. 13.
Cross section of the core stack up.
each build up layer is 38um. The total thickness of the stack up including the top and bottom metal thickness of 35um each is 814um. The processor and the PWB solder bumps thickness was neglected in calculating the thickness of the package. There are 14 metal layers in the package and the power and ground rails at the top and bottom of the package are connected to each other by thru and blind vias. The thru vias run through the core and are 0.6mm in length. The diameter of the thru vias are 200um and their edge to edge separation is 200um. A thru hole via pair was modeled in Fast Henry to extract the inductance, the value extracted was 280pH for a single pair. The length of the blind vias is dependent on the placement of the discrete capacitor in the package. The blind vias have a diameter of 100um and are spaced 300um apart and the length of the blind vias can vary from 36um to 171um. The associated inductance of the blind vias correspondingly varies from 6pH to 70.6pH respectively.The perspective view of the capacitive network is shown in Fig.14. B. Packaging Research Center Capacitor Integration Technology The package for the hydrothermal capacitors is different in structure as compared to the Dupont ground rules. The
Fig. 15.
Stack up of the package with hydrothermal capacitors.
structure is shown in Fig15. The capacitors are placed at the 2 bottom most layers, the rest of the layers are built up after the capacitor layers are tested. The package dimensions are based on the packaging research center(PRC) ground rules. The capacitors were placed directly under the die shadow as in the previous case with Dupont capacitors. 181 BaTiO3 capacitors of sizes 0.75mm, 1mm and 2.58mm were used in the 2 bottom layers allocated for the capacitors [11]. VII. Frequency and time domain simulations of the decoupling networks The frequency response of the decoupling network using the hydrothermal capacitors and the different decoupling components is shown in Fig.16 The figure shows the frequency band over which each decoupling component is effective. VRM’s are effective till the lower kHz’s region, SMD’s provide decoupling from the kHz region till around 100MHz and onchip capacitance is used above 2GHz. It is evident that a target
Fig. 16. Complete frequency band with hydrothermal capacitors and all the decoupling components.
Fig. 17.
4GHz clock input current pulse to the system .
impedance in the order of 1mohm can be met over a broad frequency range from DC to multiples of the chip operating frequencies using the combination of different decoupling components. The time domain simulations of the decoupling networks involved a current pulse input to the system. The rise time, fall time and time period of the input current pulse was chosen to mimic a 4GHz clock. The rise and fall times of the pulse were 25psec, the time period of the current pulse is 0.25nsec. The amplitude of the current pulse was taken as 115A, which is the average current of a processor for the 65nm node as calculated from the numbers given in [1].The fourier transform of the current pulse was multiplied by the frequency domain response of the PDN with all the decoupling components. The inverse fourier transform of the resultant was taken to give the complete time domain response of the system as shown in [12]. The magnitude of the switching noise with and without the
Fig. 18.
SSN magnitude with VRM,SMD’s and on-chip capacitance.
Fig. 19. SSN magnitude with VRM,SMD’s ,embedded capacitors and onchip capacitance.
embedded capacitors are shown in Fig18 and Fig19 respectively. A 3 fold improvement in the performance is clearly visible in the magnitude of the SSN with and without the embedded capacitors in the package. The frequency domain response of the decoupling network using the different decoupling components and Dupont’s embedded capacitors is shown in Fig.20 VIII. Conclusion The use of embedded discrete capacitors within the package is a feasible solution for decoupling processors above 100MHz. They overcome the limitations of SMDs, primarily in decoupling active circuits in the mid-band frequency. The modeling, measurement and characterization of embedded decoupling capacitors in the design of PDN’s has been investigated in this paper.A significant improvement in the time and frequency domain has also been observed with the use of
Fig. 20. Impedance profile with the VRM,SMD’s,Dupont package and chip capacitors.
these capacitors in the power distribution network. R EFERENCES [1] International Roadmap for Semiconductors(ITRS)- 2004 Update. http://public.itrs.net. [2] SungJun Chun, ”Methodologies for Modeling Simulatneous Swithing Noise in Multi-Layered Packages and Boards”, PhD Dissertation, Georgia Institute of Technology, April 2002. [3] Larry Smith,Raymond Anderson,Doug Forehand,Tom Pelc, Tanmoy Roy, ”Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology”, IEEE Transactions on Advanced Packaging, Vol22, NO. 3,August 1999. [4] Steve Weir ”Does Position Matter? Locating Bypass Capacitors for Effective Power Distribution” TeraSpeed Consulting Group. [5] JoongHoon Kim et al,”Separated Role of On-chip and On-PCB Decoupling Capacitors for Reduction of Radiated Emission on Printed Circuit Boards”, EMC, 2001 [6] Devarajan Balaraman et al,”BaTiO3 films by low-temperature hydrothermal techniques for next generation packaging applications”, Journal of Electroceramics, 13, 95-100, 2004. [7] Istvan Novak and Jason R. Miller,”Frequency Dependent Characterization of Bulk and Ceramic Bypass Capacitors”,Poster Material for the 12th Topical Meeting on Electrical Performance of Electronic Packaging, October 2003, Page(s):101-104 [8] Joong Ho Kim and Madhavan Swaminathan,”Modeling of Irregular Shaped Power Distribution Planes Using Transmission Matrix Method”, IEEE Transactions on Advanced Packaging, Vol 24, NO. 3, August 2001. [9] Jinwoo Choi, Sung-Hwan Min, Joong-Ho Kim, Madhavan Swaminathan, Beyene W and Xingchao Yuan,”Modeling and Analysis of Power Distribution Networks for Gigabit Applications”, IEEE Transactions on Mobile Computing, Vol 2, Issue 4, Oct-Dec.2003, Page(s)299-313. [10] Beyene W, Chuck Yuan, Joong Ho Kim, Madhavan Swaminathan,”Modeling and Analysis of Power Distribution Networks for Gigabit Applications”, Proceedings of the Fourth International Symposium on Quality Electronic Design(ISQED), 2003, Page(s)235-240. [11] Prathap Muthana, Madhavan Swaminathan, Rao Tummala, P.M.Raj, Ege Engin, Lixi Wan, D.Balaraman and S.Bhattacharya,” Design, Modeling and Characterization of Embedded Capacitors for Midfrequency Decoupling in Semiconductor Systems.” Electromagnetic Compatibility,2005,Page(s)638-643. [12] Prathap Muthana,Madhavan Swaminathan,Ege Engin, P.M.Raj and Rao Tummala,”Mid-Frequency Decoupling using Embedded Decoupling Capacitors.” Electrical Performance of Electronic Packaging,2005,Page(s)271-275
