Design of a Rail-to-Rail Folded Cascode Amplifier with ... - ICT.OPEN

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Design of a Rail-to-Rail Folded Cascode Amplifier with Transconductance Feedback Circuit Radu Ciocoveanu, Andreas Bahr, and Wolfgang H. Krautschneider

Abstract—In this work a programmable folded cascode railto-rail operational amplifier (OpAmp) with small settling time and transconductance feedback circuit is proposed. It employs a 130 nm CMOS technology with 1.2 V power supply. The small settling time is required to charge an ADC within a given time frame. The OpAmp achieves a gain bandwidth of 19.95 MHz with a 70 pF load and a minimum settling time of 144 ns while consuming 0.551 mA quiescent current. It can be shown that with 130 nm technology, high performance amplifiers can be realized on very small area.

Ifb

Feedback Module Vinp

Vinp

Vinn

Vin p

Vin n

Ifb

ΔV

Vbp

Vbn

Vbp

Vbn

Vinp

OpAmp Vinp Vbn

ΔV

Vbp

Vout Vinn

Gain

VDD

Gain

I. I NTRODUCTION Gain

T

II. O PAMP AND F EEDBACK M ODULE A RCHITECTURE A. Overall Architecture The programmable amplifier is used in a non-inverting configuration. A resistor string and transmission gates are added to allow the selection of different amplification values. The complete schematic of the programmable OpAmp is shown in Fig. 1.

Vout

Vinn Iab Iab

Index Terms—Small settling time, constant transconductance, rail-to-rail, programmable, operational amplifier.

HE downscaling of the technology has led to lower supply voltages, in order to maintain a constant electric field. With a lower supply voltage, the signal-to-noise ratio has also decreased. To counteract this drawback, it is necessary to make use of the entire signal swing, thus rail-to-rail operation at both the input and output is needed. Rail-to-rail at the input can be achieved by using complementary n-channel and p-channel differential pair, but the drawback is that the gm is varying over the input common mode range, which leads to introduction of distortions, impedes optimal frequency compensation and also leads to a variation of GBW [1]-[3]. Additional circuitry is needed to maintain the gm constant over the input common mode range. In this work, a programmable rail-to-rail folded cascode amplifier in 130 nm technology with 1.2 V power supply voltage using the topology of [1] is presented, along with the feedback module to maintain the gm constant, with the topology shown in [2].

Vout

Gain

40k

20k

10k

10k

Vref

Fig. 1. Complete schematic of the programmable OpAmp.

The inputs of feedback module and folded cascode OpAmp are shared, and the voltages Vbn and Vbp adjust the currents through the input differential pair of the OpAmp, as it is shown in Fig. 1. ∆V is a DC voltage that causes an imbalance in the feedback module, which will lead to the generation of the two control voltages Vbn and Vbp . B. Folded Cascode OpAmp The schematic of the OpAmp is shown in Fig. 2. It has complementary p-channel and n-channel differential pairs to achieve rail-to-rail common mode voltage at the input (transistors MN01, MN02, MP01, MP02), and a class AB output stage to obtain rail-to-rail at the output of the amplifier (transistors MNAB, MPAB), as presented in [1]. Transistors MN03, MP03 are biasing the input differential pair, while transistors MP04, MP05, MP06, MP07 and MN04, MN05, MN06, MN07 are used in the cascode current mirrors. Transistors MP11, MP12 and MN11, MN12 represent the floating current source, which biases both the summing circuit and the class-AB control. Transistors MP09, MP10 and MN09, MN10 bias the gates of the transistors from the floating current source. The current source provides power-supply independent

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quiescent current [1]. In a folded cascode without a floating current source, the current in the summation stage is varying with the common mode voltage at the input, which will cause a change in the voltage that biases the gates of the output transistors, which in turn contributes to the noise and offset of the amplifier. The floating architecture of the class-AB driver prevents that it contributes to the noise and the offset of the amplifier [1]. Cascoded Miller compensation is used in order to make the operational amplifier stable. VDD

MP03

MP05

MP04

Vbp

Isum 2Ip

Iab

Isum

MP06

Vbcp

MP09

The blocs T1 and T2 are transconductance amplifiers and their transconductance values are kept equal by the negative feedback. The outputs of the feedback module are two control voltages Vbn and Vbp that adjust the currents through transistors MN03, MP03 [2]. Depending on the input common-mode, the two control voltages will make the transistors MN03 and MP03 conduct more or less current. The bloc T1 in Fig. 3 is the gmT − R converter and the bloc T2 is the resistive comparator. The gmT −R converter is shown in Fig. 4. The transconductance of the input stage gmT can be expressed as a function of the equivalent small signal resistance req,AB at nodes A and B [2].

MP07 MP10

req,AB =

Res

2 gmT + gds,N M OS + gds,P M OS

[2]

(2)

MPAB

Ip

In

In Vinn

MP11

Ip

MN01

MP12

Iout

C_Miller

Vout

MN02

MP01

VDD

C_Miller

Vinp MN11

MP02

MN12

MNAB

2In

2Ip

Res

Vbcn

MN04

Isum Vbn

Isum MN07

MN06

MN03

MN09

MN05

MN10

Iab

A

B

Fig. 2. Proposed rail-to-rail amplifier [1].

The transconductance of the input stage is defined as gmT = gM N 01 + gM P 01

and it varies by a factor of two over the input common mode range [3]. The variation can be explained as following: when the input common mode is VDD/2, both the NMOS and the PMOS transistors operate, therefore the transconductance is at its maximum in that region. At GND, the NMOS will turn off while the PMOS is still conducting. Because only the PMOS is conducting, the transconductance is half of what it is at VDD/2. At VDD, the PMOS is turned off, while the NMOS is turned on, therefore the transconductance is half of what it is at VDD/2. To keep the transconductance constant over the input common mode range additional circuitry is needed. C. Feedback Module To maintain a constant gmT , the circuit schematic in Fig. 5 is used, as presented in [2]. The functioning principle of the feedback module is shown in Fig. 3. Rail-to-Rail Input Stage

Feedback Module VDD

VDD

Vbp

2Ip

ΔV

+ T1

Δi1

-

Δi2

+

Ip

T2

-

MN01

Vinn

ΔV

In

2In

Vbn

Vinp MP02

2In MN03

−1 gmT = Rref = R1−1 = R2−1 [2]

+

Ip

MN02

MP01

The complete feedback module in Fig. 5 includes a dynamic bias generator that is used to provide a current (Ibias +In −Ip ) for the two current sources M S1 and M S2. It also consists of blocs T1 (gmT − R converter), T2 (resistive comparator) and a folded cascode transimpedance amplifier structure used as current summation stage. T1 and T2 are unbalanced by a DC input voltage ∆V and generate two output currents. In the current summation stage, the summation of currents from T1 and T2 is converted in the two controlling voltages Vbn and Vbp that adjust the tail current sources in both the feedback module and OpAmp [2]. The summation stage in Fig. 5 is a resistive comparator for (gmT +gds,N M OS +gds,P M OS )−1 and Rref . The tail currents will be adjusted until (gmT + gds,N M OS + gds,P M OS )−1 = Rref [2]. Because gds,N M OS and gds,P M OS are small in comparison to gmT , they can be ignored, therefore the equation becomes:

Stage

In

Vbn

Fig. 4. gmT − R converter [2].

Summation

MP03

2Ip

Vbp

2In

(1)

Output Stage

(3)

Two other important conditions have to be met for a good functionality of the feedback module. The minimum value for the reference resistance Rref is given by eq. 4. Rref,min =

Fig. 3. Feedback module functioning principle [2].

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1 gmf

[2]

(4)

3

Dynamic Bias Current Generator 4

:

MP12

1

1

MP13

MP11

:

:

1

2In

In/2

2Ip

:

MN10

Vinp

Ibias/2

1

:

2

4

(Ibias+In)/2

MP23

Vinp

Vb2

R2

C

Vinn

Vbn

B MP27 MP29

1

1

:

Vb3

ΔV MN19

:

MN23

MN20

Vbp

P

MP28

ΔV 4

MP24

MP20

(Ibias+In-Ip)/2 MP26 A

MP25

Ibias

R1

D

MP10

MP22

Vb1

MS4

Ibias

MP18

Ibias+In-Ip Ibias+In-Ip

Ip/2

MP09

Vinn

MS2 MS3

MP19 MN09

Current Summation Stage MP21

2Ip

MS1

MP17

MP16

In/2

1

T2

VDD

Vb1

MP14 MP15

4

T1

1

Cc

MN24

2In

1

MN25

MN18 MN11

MN12

MN14

MN13

MN15

MN16

MN17 MN21

1 1

: :

MN22

4 1

Fig. 5. Circuit schematic of the feedback module [2].

The upper bound of gmT is showed by eq. 5 gmT −max = gmf [2]

(5)

where gmf represents the transconductance of transistors MP26-29 from Fig. 5. Therefore, to achieve a constant and accurate gmT , the maximum gmT is derived as: −1 gmT −max = Rref [2]

The effect of transistor mismatches over gm variation was modeled by Monte Carlo analysis with 100 iterations. As shown in Fig. 7, at input common mode voltage of 0.1 V, the probability of having transconductance variations larger than 7 % decreases exponentially. 25.0

III. S IMULATION R ESULTS AND L AYOUT In order to assess the performances of the system, two of the most important specifications have been analyzed, namely gmT variation and settling time for different amplification values. To verify the transconductance variation, the constant gm stage had the input common mode voltage swept from 0.1 V to 1.1 V . The normalized gmT variation is shown in Fig. 6.

No. of Samples

(6)

Large loop gain has to be maintained for a constant and accurate gmT and therefore Rref which acts like a degeneration resistor, should not be too large. Moreover, the GBW of the feedback module has to be as large as the GBW of the folded cascode amplifier and also enough phase margin is needed to ensure stability of the system [2].

Number = 100 Mean = 4.44895 % Std Dev = 2.60901

20.0

15.0 -3σ

-2σ

-σ

μ

σ

2σ

3σ

10.0

5.0

-3.37809

-769.078m

1.83993

4.44895

7.05796

9.66697

12.2760

0.0 -5.0

-2.5

0.0

5.0 Values (%)

2.5

7.5

10.0

12.5

15.0

Fig. 7. Monte Carlo histogram for normalized transconductance at input common mode voltage of 0.1 V. The probability of values higher than design specification gmT < 9 % is very low.

For an input common mode voltage of 1.1 V, the probability of having transconductance variations larger than 6% decreases exponentially, as shown in Fig. 8. 25.0 Number = 100 Mean = 3.53936 % Std Dev = 2.56730

20.0 1.09

Normalized Total Transconductance

M15: 1.1 1.049334 No. of Samples

M14: 100.0m 982.5156m

1.03

.97 dx: 500.0m dy: 34.96805m s: 69.93611m/

.91

dx: 500.0m dy: 31.85031m s: 63.70061m/

15.0 -3σ

-2σ

-σ

μ

σ

2σ

3σ

10.0

5.0

-4.16253

-1.59523

972.063m

3.53936

6.10666

8.67396

11.2413

0.0 -5.0

.85 0.0

.25

.5 .75 Input Common Mode Voltage (V)

1.0

Fig. 6. gmT variation vs. Vincm . The maximum gmT variation after the post-layout simulation is 3.4%.

-2.5

0.0

2.5

5.0 Values (%)

7.5

10.0

12.5

15.0

Fig. 8. Monte Carlo histogram for normalized transconductance at input common mode voltage of 1.1 V. The probability of values higher than design specification gmT < 9 % is very low.

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Settling time is a critical specification for this design, because the amplifier has to settle to 1/2 LSB within a given time frame, in order for the ADC to sample the value correctly. To measure the settling time, a probe was first added at the moment when the pulse is applied at the input, and a second probe, when the output value of the amplifier is within 1/2 LSB of the final value and time difference between the two was measured.

1.0

V (V)

.75

.5

.25

0.0

-.25 12.5

15.0

17.5

20.0 time (us)

22.5

25.0

Fig. 9. Settling time simulation.

IV. C ONCLUSION The performance comparison of the rail-to-rail amplifier is summarized in table II, showing a lower power consumption than in [4] as well as a smaller settling time, larger slew rate and less area consumption. [3] [2] This paper Process 0.13 µm 0.13 µm 0.13 µm Supply Voltage (V) 1.2 1 1.2 Maximum gmT 13 % 3.4 % 3.4 % variation Load 70 pF 20 kΩ || 95 pF 70 pF DC Gain (dB) 85 60 71.6 Power 1.28 0.187* 0.662 Consumption (mW) GBW (MHz) 4.99 3.7 19.95 Phase Margin 67° 72° 64° Slew Rate (V/µs) 0.9 1.74 7.39 Minimum Settling ≈ 0.464** 0.144 Time (µs) Occupied area 0.109 mm2 0.0289 mm2 0.0231 mm2 (mm2) * Only the power-consumption of folded-cascode amplifier is considered. ** Minimum settling-time achieved for the specified power consumption. In [4], the power consumption is 1.28 mW .

The values for the settling time for the different amplification factors are given in table I. Amplification Value 1 2 4 8

Rise Time

Fall Time

144 ns 490 ns 308 ns 387 ns

329 ns 491 ns 482.95 ns 484.13 ns

TABLE I S IMULATED SETTLING TIME FOR DIFFERENT AMPLIFICATION FACTORS .

TABLE II P ERFORMANCE COMPARISON .

This paper has presented a programmable rail-to-rail amplifier with transconductance feedback technique, with small settling time and good constant transconductance over the input common mode range. The simulated results show good performance of the amplifier, with low power consumption, large slew rate and small occupied area. V. ACKNOWLEDGEMENTS

The area consumption of the layout in Fig. 10 is only 0.0231 mm2 .

This work was supported by the German Research Foundation, Priority Program SPP1665. R EFERENCES

Feedback Module

197.6 µm

Feedback Resistors and Switches

FoldedCascode

[1] R. Hogervorst, J. P. Tero, R. Eschauzier, and P. W. Daly, ”A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries”, IEEE J. Solid-State Circuits vol. 29, no. 12, pp. 15051513, 1994. [2] S. Dai, X. Cao, T. Yi, E. Hubbard, and Z. Hong, ”1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique”, IEEE Trans. VLSI Syst vol. 21, no. 10, pp. 19281935, 2013. [3] Willy M. C. Sansen, Analog Design Essentials, Dordrecht: Springer, 2006, ISBN: 978-0-387-25747-1, URL: http://www.springer.com/gb/1850-9999. [4] J. M. Tomasik, K. M. Hafkemeyer, W. Galjan, D. Schroeder, and W. H. Krautschneider, ”A 130nm CMOS Programmable Operational Amplifier”, in 2008 NORCHIP pp. 2932.

Miller Compensation

117 µm Fig. 10. Layout of the complete rail-to-rail OpAmp with transconductance feedback module.

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