Design of an Ultra-Low Power 32-bit Adder Operating at Subthreshold Voltages in 45-nm FinFET Mohsen Jafari, Mohsen Imani, Mohammad Ansari, Morteza Fathipour, Nader Sehatbakhsh School of Electrical and Computer, Collage of Engineering, University of Tehran, Tehran, Iran E-mail:
[email protected] Abstract— this paper describes the design of an ultimately low power subthreshold 32-bit adder, implemented in 45-nm technology. Low power design is achieved by using FinFET devices which are nowadays a basic component of very scaled and low power circuits. The circuit was tested in all corners and its consumption is as low as 10fJ per computation with 0.4V supply voltage and maximum operating frequency about 260KHz. A very alluring feature of this design is that it could be speed up to 256MHz in 1.13V supply voltage and consuming only 59.05fJ energy per calculation. Another appealing feature of propose design is its stable and reliable operation with 130mV supply voltage by 3.74 KHz operation frequency. In this mode the design consumes only 43.77fW. This multi-mode design could be used in integrated circuit design which uses power management technique to reduce energy consumption by OS software job assignment. The simulations were done by HSPISE 2008.all model are extracted from FinFET 45nm PTM library.
(1) ܱܲܧൌ ܲ ൈ ܴܲܧ Where energy per operation (EOP) is the energy consumption per each operation; P is power consumption of the circuit and PERmin is the minimum achievable period of the adder’s inputs which has been measured for a range of supply voltages in previous section. Therefore, we can specify the voltage in which the circuit has the minimum value of EOP. This point is called minimum energy point and has a great importance in ultra-low power designs. The total power and energy per cycle versus supply voltage level are depicted in Figure1 and Figure2 respectively. As it is depicted in Figure2, total energy per operation cycle has a minimum point at a supply voltage near 0.4V. So, the adder should be operated in such voltage for high workload running time.
Keywords: Sub threshold, FinFET, Adder, Minimum Energy Point I.
INTRODUCTION
Portable devices are essentially depended on power reduction of integrated circuits (ICs) so as not use a heavy back up battery. Some application which are mainly benefit from low-power designs are as wireless micro-sensor networks [1,2], implantable medical electronics [3] and Radio-frequency identification (RFID). Usage of FinFET devices in designing the adders make it possible to shift down energy-delay Pareto-Optimal curve and reach high performance circuit with more than 4 order lower power consumption[4]. It also causes the effective area of the devices decrease very much and also is suitable for now-adays technology [5,6]. In this paper an ultimately low-power carry look-ahead adder was designed using FinFET devices. The library in use is 45nm FinFET PTM[7]. Next in V results are achieved.
II. SPECIFYING THE MINIMUM ENERGY POINT We will measure static and total power consumption of the 32-bit adder for a range of supply voltages. FinFET device availability makes it possible to decrease the supply voltage even under 100mV to find the best minimum operating point. Subtracting static power from the total power gives the dynamic power consumption of the circuit. So we can calculate the energy per operation cycle as:
c 978-1-4673-6040-1/13/$31.00 2013 IEEE
Figure1. Total power consumption for the 32-bit adder
In today technologies static power dissipation plays an important role in total power consumption of the circuit, so it is important to measure these parameters of the circuits. In other words measuring the static power dissipation can further be used in estimating the total power and optimum point of the energy and performance of the design. Static energy per cycle for 32-bit adder is depicted in Figure3. The power minimized in lowest level of supply voltage but as you can see the energy per cycle has a minimum in middle point of the plot about 900 mV where the power is not in its minimum value. Dynamic power (energy) consumption was found based on static power (energy) and total power (energy) consumption. Results are shown in Figure4.
167
Figure2. Total energy per cycle for the 32-bit adder Figure5. Static and dynamic energy per cycle and their contribution in total energy per cycle
III. CONCLUSION
Figure3. Static energy per cycle of the 32-bit adder
Compare the later with Figure3 shows an inverse behavior for Dynamic and Static energy per cycle for proposed 32-bit adder. Dynamic energy and static energy increase and decrease respectively by the increase of the supply voltage. So the total energy per cycle would have a minimum in middle point where the supply voltage is about 400mV. Total energy per cycle which is the sum of dynamic and static energy per cycle is depicted in Figure5.
This paper reintroduces a very low power and multimode 32bit adder with FinFET devices focusing on power management technique. Design and optimization of the design was done in 45nm technology and reliability and stability of it was conserved in different voltage levels. The use of FinFET makes it available to reach ultra-low power in MEP with lowest area. Its appealing characteristics is its as low as 10fJ energy consumption per operation and also being stable trough different modes including high speed low power with normal supply voltage and very low power with lower than 100mV supply voltage utilizing FinFET devices. IV. REFERENCES [1] A. Sinha and A. Chandrakasan, "Dynamic power management in wireless sensor networks," Design & Test of Computers, IEEE, vol. 18, pp. 62-74, 2001. [2] B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, "A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency," in VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on, 2006, pp. 154-155. [3] O. Soykan, "Power sources for implantable medical devices," Medical Device Manufacturing & Technology, pp. 76-79, 2002. [4] X. Wu, F. Wang, and Y. Xie, "Analysis of subthreshold FinFET circuits for ultra-low power design," in SOC Conference, 2006 IEEE International, 2006, pp. 91-92. [5] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, "Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, pp. 232-245, 2010. [6] P. Mishra, A. Muttreja, and N. K. Jha, "FinFET Circuit Design," Nanoelectronic Circuit Design, pp. 23-54, 2011. [7] 45nm FinFET PTM library available: http://ptm.asu.edu/modelcard/45nm_finfet.rar
Figure4. Dynamic energy per cycle of the 32-bit adder
The post-layout simulation shows that the minimum energy point may effect slightly because of increasing dynamic and static power simultaneously. That is because of parasitic capacitance. The minimum energy point is determined by dominant power part.
168
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
