IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998
761
IIR Digital Filter Design Using Minimum Adder Multiplier Blocks A. G. Dempster and M. D. Macleod Abstract—Traditional methods for the design of fixed-point IIR filters suggest the use of wave filters to reduce complexity. The application of multiplier blocks, which exploit redundancy across the coefficients, changes the relationships between structures such that the cascade structure is most efficient. The use of variable wordlength methods results in further complexity reduction. Index Terms— Digital filters, digital filter wordlength effects, limit cycles, multiplication, multiplier circuits, wave digital filters. Fig. 1. Replacing the five multiplier coefficients of a second-order transposed direct form I filter with a single multiplier block.
I. INTRODUCTION Infinite impulse response (IIR) filter complexity, when implemented in application-specific integrated circuits, was dominated by the number of add operations used to implement coefficient multiplication. To reduce this complexity, canonic signed-digit (CSD) representation has been used for the multiplier coefficients. In this paper, we examine the complexity effects of instead applying multiplier blocks to various IIR structures. Complexity is measured as adder cost, the number of adders required to perform the multiplications, the structural additions, and delays (costed at 0.2 adders). II. OPTIMIZED MULTIPLIERS AND MULTIPLIER BLOCKS We have presented optimal [1] and suboptimal [2] algorithms for designing individual shift-and-add multipliers using graphical methods; both algorithms are far superior to CSD or any other method. Where a single data sample is multiplied by several coefficients, a multiplier block [3], [4] can be used. In Fig. 1, the five coefficients of a second-order transposed direct-form IIR filter can be replaced with a single multiplier block. Redundancy between coefficient multipliers can then be exploited as shown in the graph of Fig. 2. Graph representation of multipliers was introduced by Bull and Horrocks [4]. The edges of the graph represent shifts, and the vertices (excluding the input vertex) represent adders (a term we use to also include subtractors). This figure shows the optimal graph for the coefficient set (7, 23, 173), although it could simply be producing multiplication by 173. The multiplications by 7, 23, (and 45) are available “for free.” These graphical methods for both individual multipliers and multiplier blocks are specific types of subexpression elimination (see also [5], [6]), and we have shown [7] that they are the most efficient kind. III. COMPARISON OF STRUCTURES USING MULTIPLIER BLOCKS A. Introduction The coefficient wordlength required for a digital filter is closely related to coefficient sensitivities [8]. Different filter structures can require widely different wordlengths to meet the same filter specification. In particular, the direct form, with its high coefficient Manuscript received March 18, 1997. This paper was recommended by Associate Editor K. K. Parhi. A. G. Dempster is with the School of Electronic and Manufacturing Systems Engineering, University of Westminster, London W1M 8JS, England (e-mail:
[email protected]). M. D. Macleod is with the Department of Engineering, Cambridge University, Cambridge CB2 1PZ, England. Publisher Item Identifier S 1057-7130(98)02154-5.
Fig. 2. Multiplier block producing products of the input with coefficients (7, 23, 173). TABLE I AVERAGE STATISTICAL COST ESTIMATES FOR THE 50 FILTERS OF ORDER 5, WITHOUT THE USE OF MULTIPLIER BLOCKS; THE THREE ESTIMATORS ARE THE ORDER–WORDLENGTH PRODUCT (O–W) AND (1) USING THE OPTIMIZED UNIFORM WORDLENGTH f(1)u g AND THE VARIABLE WORDLENGTH f(1)v g Form Cascade Direct I Direct II Parallel Wave
O-W 49.35 106.46 106.46 126.56 43.10
N=5 (1)u 25.3 40.9 39.9 46.0 27.6
(1)v 24.9 40.3 39.3 45.5 27.6
sensitivities, requires much longer wordlengths than, say, a wave implementation due to its low sensitivity. For elliptic filters, wave and cascade implementations also tend to require fewer coefficient multipliers. This has led to the conclusion [8] that wave structures are most efficient in complexity (e.g., VLSI area). However, for the example transfer function of [8], cascade and parallel structures designed using multiplier blocks [9] are more efficient than wave structures. Here, we present a statistical investigation [10], designing 50 filters of order 5 and comparing the complexity of cascade, parallel, direct, and wave structures using multiplier blocks. An identical study of filters of order 9 [7] gives very similar results to those below. B. Filter Design Methodology 1) Specification: Elliptic filters were selected because they require the lowest order to fulfill a specification, and, for many structures, they require fewer coefficient multipliers. The low-pass filter spec-
1057–7130/98$10.00 1998 IEEE
762
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998
TABLE II AVERAGE RESULTS FOR 50 FILTERS OF ORDER 5, SHOWING STATISTICAL WORDLENGTHS (OF AN ARBITRARY STARTING POINT AND OPTIMAL UNIFORM AND VARIABLE WORDLENGTHS), ACTUAL WORDLENGTHS (AS ABOVE, PLUS SCALED VARIABLE WORDLENGTH), AND THE ADDER COSTS ASSOCIATED WITH THE ACTUAL COEFFICIENTS Form Case Direct I Direct II Parallel Wave
Statistical Wordlength arb. unif. var. 12.34 9.44 8.80 17.09 15.21 14.89 17.09 15.21 14.89 14.67 13.54 13.08 12.61 12.28 12.06
arb. 10.35 15.44 15.44 13.12 8.88
Actual Wordlength unif. var. 8.13 7.93 14.21 13.95 14.21 13.95 12.58 12.38 9.21 9.90
TABLE III AVERAGE ADDER COSTS OF 50 FILTERS OF ORDER 5 WITH ERROR-FEEDBACK LIMIT-CYCLE ELIMINATION [14] Structure Cascade Direct 1 Direct 2 Parallel Wave
MT 22.08 33.24 34.62 32.96 27.17
Round 26.59 35.17 36.55 37.95 27.17
Structure No EF
(1)
for M multipliers, A structural adders, D structural delays, and equivalent adders per delay (we use 0.2); A(w) is the average number of adders expected for optimized multipliers of coefficient statistical wordlength w, interpolated from data in [1]. These costs are also shown in Table I. The wave structure is cheapest using the order–wordlength product, and the cascade structure is cheapest using (1). Direct and parallel structures are more than twice as expensive. A comparison of the uniform and variable columns in Table I shows the saving due to using variable wordlengths. 3) Blocking the Integer Coefficients and Costing the Filter: The “actual” wordlength is the shortest wordlength that allows the specification to be met after rounding the coefficients for the arbitrary filter, that with optimized uniform wordlength and optimized variable wordlength. The scaled variable wordlength [11] is the shortest wordlength resulting from scaling the nonintegral extra bit vector prior to rounding, giving four sets of “actual” integer coefficients that meet specification. Integer coefficients can now be gathered into blocks for the direct, cascade, and parallel forms. Wave designs cannot utilize blocking because their coefficients are each isolated in the filter network. The direct form benefits most by using either a single block (type I) or two blocks (type II). The parallel form also benefits significantly by grouping about half of its coefficients into a single block. The multiplier blocks are designed by the best algorithm available for
arb. 25.52 28.46 29.98 34.65 27.42
Adder Costs unif. var. 22.65 22.23 26.60 26.27 28.13 27.81 34.27 33.71 28.00 28.73
s.v. 21.06 25.54 26.92 31.88 27.17
TABLE IV DATA WORDLENGTH EXTRA BITS REQUIRED TO PROVIDE THE SAME SNR PERFORMANCE AS A WAVE STRUCTURE FOR THE THREE CASES: NO ERROR FEEDBACK (i.e., NO LIMIT CYCLE ELIMINATION), AND LIMIT-CYCLE ELIMINATION FOR BOTH MAGNITUDE TRUNCATE AND ROUNDING QUANTIZERS
ification parameters (p p fp fs ), the passband, and stopband ripples and edges were randomly selected (see, e.g., [11]) such that the order required was 5. Direct, cascade, and parallel forms were designed using standard methods and wave filters using those in [12]. 2) Statistical Wordlengths and Traditional Cost Estimators: The statistical wordlength is that to which the continuous coefficients can be rounded so that there is a (say 95%) probability that the specification is met. We evaluate this for: 1) an arbitrary filter that meets the specification; 2) the optimized wordlength from trading off design margins in the pass- and stopbands; and 3) the variable statistical wordlength, shorter on average due to allowing shorter wordlengths for less sensitive coefficients [11]. Prior to selecting integer coefficients (and applying multiplier blocks), the cost measure as used in [8] is order–wordlength product. The structures compare as shown in Table I. A fairer measure [7] is (1):
C = MA(w) + A + D
s.v. 7.05 13.31 13.31 11.51 8.62
Cascade Direct I Direct II Parallel
2.1 0.3 4.4 2.1
Extra Bits (LC Eliminated) MT Round 2.1 0.2 0.9 0.9 1.7 1.4 2.2 1.1
the task, i.e., for coefficients of wordlength up to 12 bits, MAG [1] for single coefficients, and RAG-n [3] for blocks, with BHM [3] for larger wordlengths. C. Results and Discussion Table II shows the results for application of multiplier blocks, averaged over 50 filters. The rightmost column, the cost of the scaled variable wordlength designs, is of most interest as it contains the most efficient filters of each structure. The cascade form is the most efficient, and the direct forms are slightly superior to the wave structure. Direct form I, despite its extra delays, is more efficient than direct form II. The hierarchy of Table I has been significantly changed by the use of multiplier blocks. The contribution to overall filter complexity made by the structural adders is around half for all structures, similar to the findings for FIR [1], [3], [4]. Optimizing the statistical wordlength (going from arbitrary uniform to optimal uniform) for the cascade form gains about 3 bits on average. This shows that a single example at an arbitrary point [8], [9] is unsatisfactory, and also shows the need to compare many filters at their optimum statistical wordlength. D. Limit-Cycle Elimination These results indicate that one of the serious problems of the highly sensitive direct form, that of the high cost of coefficient multipliers, can be avoided. However, the problem of limit cycles must be addressed. Wave structures are inherently limit-cycle free. For the other filter types, zero-input limit cycles were eliminated using error feedback (EF) [13]. This method feeds back via an FIR stage the difference between the quantizer input and output. The FIR stage was designed for minimum cost, eliminating limit cycles for either magnitude truncation or rounding quantizers. With this enhancement, the results of the final column of Table II are replaced by those in Table III. Direct and parallel forms no longer compete with the most efficient form, which remains the cascade. E. Noise Gain For a given signal-to-noise specification, different structures require different data wordlengths (i.e., the “adders” will have different widths). In Table IV, we compare the extra data wordlength bits
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998
required in addition to those required by the wave structure for the cases with and without limit-cycle elimination. Without EF, the extra data wordlength required for nonwave structures could be significant (2–4 bits), except for the direct form 1. The effect of introducing EF is to reduce the differences in noise performance for rounding, while some simple magnitude-truncation solutions (specifically, the cheap antisymmetric solution [14]) increase noise. The cascade incurs only a 0.2-bit penalty versus the wave structure when limit cycles are eliminated. This means that the hierarchies of Sections III-C and III-D are not greatly affected by a medium to high SNR requirement, where long data wordlengths will mean that these increments are insignificant.
763
A Unified Approach to Class E versus Quasi-Resonant Switch Topologies Bogdan Tomescu
Abstract—A generalized methodology of achieving Class E versus quasiresonant (QR) switching is introduced, and the associated resonant switch topologies are analyzed, with the conclusion that Class E operation can be achieved for a given switching edge if the respective current or voltage is continuously differentiable (C 1 ) through the switching instant. This concept is applied to show how the category of Class E switches includes the QR switches, but contains a wider variety of configurations.
I. INTRODUCTION
IV. CONCLUSIONS 1) The use of multiplier blocks changes the complexity hierarchy for IIR filter structures. The cascade structure, even with errorfeedback limit-cycle elimination, is the most efficient structure of those studied, which included the lattice wave. 2) Multiplier blocks reduce the complexity contribution of IIR multipliers by about 50%. REFERENCES [1] A. G. Dempster and M. D. Macleod, “Constant integer multiplication using minimum adders,” Proc. Inst. Elect. Eng. Circuits, Devices and Systems, vol. 141, pp. 407–413, Oct. 1994. [2] , “General algorithms for reduced-adder integer multiplier design,” Electron. Lett., vol. 31, pp. 1800–1802, Oct. 1995. , “Use of minimum-adder multiplier blocks in FIR digital filters,” [3] IEEE Trans. Circuits Syst. II, vol. 42, pp. 569–577, Sept. 1995. [4] D. R. Bull and D. H. Horrocks, “Primitive operator digital filters,” Proc. Inst. Elect. Eng., pt. G, vol. 138, pp. 401–412, June 1991. [5] R. I. Hartley and K. K. Parhi, Digit-Serial Computation. Norwell, MA: Kluwer Academic, 1995. [6] M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, “Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 151–165, Feb. 1996. [7] A. G. Dempster, “Digital filter design for low-complexity implementation,” Ph.D. dissertation, Cambridge Univ., Cambridge, U.K., June 1995. [8] R. E. Crochiere, “A new statistical approach to the coefficient wordlength problem for digital filters,” IEEE Trans. Circuits Syst., vol. CAS-22, pp. 190–196, Mar. 1975. [9] A. G. Dempster and M. D. Macleod, “Multiplier blocks and the complexity of IIR structures,” Electron. Lett., vol. 30, pp. 1841–1842, Oct. 1994. [10] , “Comparison of IIR filter structure complexities using multiplier blocks,” in Proc. ISCAS’95, Apr./May 1995, vol. 2, pp. 858–861. [11] , “Variable statistical wordlength in digital filters,” Proc. Inst. Elect. Eng. Vision, Image and Signal Processing, vol. 143, pp. 62–66, Feb. 1996. [12] L. Gazsi, “Explicit formulas for lattice wave digital filters,” IEEE Trans. Circuits Syst., vol. CAS-32, pp. 68–88, Jan. 1985. [13] T. I. Laakso, “Elimination of limit-cycles in direct form digital-filters using error feedback,” Int. J. Circuit Theory Appl. vol. 21, no. 2, pp. 141–163, 1993. [14] A. G. Dempster, “The cost of limit-cycle elimination in IIR digital filters using multiplier blocks,” in Proc. ISCAS’97, June 1997, vol. IV, pp. 2204–2207.
The basic QR zero voltage and zero current switches, in a single or multiresonant architecture, are the core of dc/dc soft switching topologies [1]–[3]. In addition, Class E switching, with zero slope at one of the edges, further reduces losses at that switching instant. Initial RF and induction heating applications have been extended to dc–dc conversion, where a Class E amplifier (inverter) is eventually followed through an impedance matching network by a rectifier which can also be Class E [4]–[15]. This paper presents a unified methodology showing how Class E switching can be designed into the QR circuits, often with no extra cost or complexity. II. MODELING CONSIDERATIONS A. Assumptions and Notations In order to point out the main theoretical results, as a first goal of the analysis, the switch and its associated resonant circuit are considered ideal (zero ON/infinite OFF resistance for the switch, no resistive losses for the resonant network). Also, the following assumptions, present in all practical situations, are used throughout the analysis: 1) The resonant capacitor C is open at dc; hence, it may be connected to any terminal of a dc voltage source such as the input Vi or output filter capacitor Cf . 2) The resonant inductor L is shorted at dc; hence, it may be shifted through any node where a dc current source/sink, such as the input Ii or output filter choke Lf is connected. In the following sections and associated figures, the turn ON and turn OFF instants will be denoted by the usual notations tON and tOFF ; and they will be detailed in the circuit examples as tOND , tONS or tOFFD , tOFFS for the diode and main switch, respectively, when a distinction needs to be made. Further refinements, e.g., tON+ , tOND+ , etc., will be used as appropriate in order to specify the moments immediately after or before the respective ON or OFF instants. Similar notations, self-evident in their context, will be employed for the switch (main or diode) current and voltage, e.g., IS (tON+ ), ID (tOFF0) , VS (tOFF+) , etc. Manuscript received August 23, 1996; revised April 20, 1997. This paper was recommended by Associate Editor V. Porra. The author was with the Advanced Power Supplies Group, Texas Instruments Inc., Dallas, TX 75243 USA, and the Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061-0111 USA. He is now with Space Systems/Loral, Palo Alto, CA 94303 USA (e-mail:
[email protected]). Publisher Item Identifier S 1057-7130(98)02142-9.
1057–7130/98$10.00 1998 IEEE
