Design of Sequential Circuits in Multilayer QCA Structure - IEEE Xplore

2013 International Symposium on Electronic System Design

Design of Sequential Circuits in Multilayer QCA Structure Biplab K Sikdar Department of Computer Science and Technology, Bengal Engineering and Science University, Shibpur WB-711103, India, Email: [email protected].

Bibhash Sen, Mrinal Goswami, Samik Some Department of Computer Science and Engineering, National Institute of Technology Durgapur, WB-713209, India, Email: [email protected], {mrinal.goswami21, decoy.samik}@gmail.com.

as an active component, in multi-layered QCA architecture, each layer can be used as an active component. A detailed design and analysis of sequential circuits, with characterization of cell defects in QCA was explored in [2], [4]. The improved designs reported so far in the literature are mostly based on this design. Further extension to these designs is robust memory cell [5]. However, all of these investigations were limited mostly to co-planner QCA layout. The design of layered structure, to synthesize different ip-ops, in QCA technology is yet to be explored. The above scenario motivates us to explore efcient QCA designs in multilayer architecture, concentrating on the analysis of the effect of layer spacing and radius of effect. The state-of-the-art schemes on multi-layered design mostly used the concept for wire crossing only. A scheme for modelling sequential logic around QCA followed by a more feasible counter and register unit has been framed with the target to achieve high device density. The major contributions of this work around multilayer architecture can be summarized as: • Explored the design of cost effective multi-layered sequential logic structure, such as SR, JK, D and T ip-op. • Use of different layers as active circuit component, followed by robust wire crossing, is explored. • Manufacturing defects, such as displacement in cell position, additional cell deposition etc. are examined. • Finally, synthesis of high level complex logic circuits, employing the QCA ip-ops proposed, is realized. The details on proposed sequential logics are introduced in Section III. The characterization of the design, subjected to different cell defects, is done in Section III-B. Section IV reports the design of 4-bit shift register using D ipop. Conclusions are given in last section. The next section provides the basics of QCA.

Abstract—This work targets developing sequential circuits in QCA under multilayer framework. The main goal is to build an efcient methodology to achieve high device density as well as minimum delay in logic realization. This is the rst attempt in its kind of design with active QCA multilayer. The synthesis of conventional SR, JK, D and T ip-ops is reported following the multilayer QCA technology. The characterization of ip-ops is done with achievement of 100% fault tolerance under any kind of additional cell deposition QCA defect. It is established that the proposed multilayer design achieves 77% improvement in device density simultaneously with 50% improvement in delay than that of the existing conventional design approaches. The proposed design further achieves the minimum clock zone (3clock) desired for sequential logic in QCA technology. Keywords-Quantum-dot Cellular Automata (QCA), Multilayer, Sequential logic, Flip-ops, Additional Cell defect, Nanotechnology.

I. I NTRODUCTION Downscaling of CMOS does not necessarily results in corresponding gains in device density. The limitations of CMOS technology, such as high power consumption and difculty in circuit compaction, encourage introduction of Quantumdot Cellular Automata (QCA), an emerging nanotechnology, to create nano-scale devices with high compaction density, capable of performing computation at very high switching speed [1]. The research outcome suggests that QCA (magnetic QCA) can be operational at room temperature. The conventional binary information is represented by the conguration of electrons of QCA cell. The QCA accomplishes logical operations and moves data through pure coulombic interactions among the cells. It implements unique computing paradigms such as memory-in-motion and processing-by-wire [2]. The fundamental QCA logic primitives are the three-input majority gate, wire, and inverter. The growing research on physical characteristic of QCA targets a special design process of QCA circuits. Possibility of multilayer architecture of QCA primitives was explored in [3]. In a multi-layer case, two cells are closest when placed directly one over the other, i.e., on the same location but on separate layers. Also, in multilayer, intermediate layers are used to prevent any possible crosstalk in wire crossing which can occur in coplanar crossover. Unlike CMOS integrated circuit, where only the base layer serves 978-0-7695-5143-2/13 $26.00 © 2013 IEEE DOI 10.1109/ISED.2013.11

II. P RELIMINARIES A quantum dot is a region of low potential, surrounded by a ring of high potential, where an electron is quantummechanically conned (Fig.1(a)). A quantum-dot cellular automata (QCA) cell consists of such quantum dots at each corner of a square and contains two free electrons [1]. The 21

sequential circuits, we detail out next the design of an SR ip-op.

electrons can quantum mechanically tunnel among the dots and settle either in polarization P=-1 (logic 0) or in P=+1 (logic 1) as shown in Fig.1(b). The basic logic structure realized with QCA is the 3-input majority gate, MV(A, B, C) = Maj(A, B, C) = AB+BC+CA ( Fig.1(c)). A majority gate can be programmed, to function as a 2-input AND or a 2-input OR, by xing one of the three input cells to p = -1 or p = +1, respectively. Inverter realized in two different orientations is shown in Fig.1(d). In QCA based logic implementation, two kinds of QCA wires are possible. Figure 1(e) describes the coplanar wire crossing which requires two different orientations, a 90o (xcell) and a 45o (+ -cell) structure. Multilayer wire crossing is shown in Fig.1(f). Timing/ synchronization in QCA is accomplished by the cascaded clocking of four distinct and periodic phases as shown in Fig.1(g). 90degree orientation

Tunnelling Potential

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Quantum Well

Binary ’1’ P = +1

(a)

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The majority gate representation of this SR ipop is, Qt = M aj(S, R, Qt−1 ). The schematic block diagram of the proposed logic is shown in Fig. 2. The basic component in the SR FF is the MV. If the input S is 1 and R is 0, then the stored value of the FF is 1. The output is 0 if R is 1 and S is 0. When both the S and R are same, the output value remains unchanged. Fig. 3(a) shows the QCA layout of the SR FF. It shows two layers are used. In layer 1 (Fig. 3(b)), there are two inputs (S, Qold ), layer 2 (Fig. 3(c)) contains one input (R). The desired outputs Q and Q are obtained from the layer 1 and layer 2 respectively. The simulation result for the proposed SR ip-op is shown in Fig. 4. It can be observed that the output is not surrounded by the other cells and, therefore, can easily be accessed. In other words, this structure does not need any wire crossover to transmit the output signal. Hence, the output can be easily fed to the input of other QCA circuits. The performance of

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Schematic diagram of SR ip-op

A. Proposed SR ip-op

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III. T HE P ROPOSED QCA F LIP - FLOPS

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In [3], the multilayer architecture of QCA primitives, such as majority voter, inverter etc. are reported. In this section, the QCA designs of different FFs are presented. For such a design inverter is not required as inversion can take place within multilayer itself. The input signals get inverted as we move across the layers. To avoid inherent inversion across the layer, upper layer cell is placed in diagonal position of the lower cell. To illustrate the design of multilayer QCA

Figure 3.

QCA layout of proposed SR ip-op

proposed SR ip-op is shown in Table I. It is evident from Table I that the layered structure have more compact cell area as well as less delay than that of single layer design [2]. The performance achieved in [2] was believed to be the best.

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Figure 4.

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Simulation result of the proposed SR ip-op

(b) T ip-op P=1

Table I P ERFORMANCE COMPARISON OF SR FLIP - FLOP Design

Grid area

Cell area Cell count (in μm2 ) In[2] 20X11 0.09 66 proposed SR 10X6 0.02 24 Improvement 72% 77% 63% CZ=Clock zone, 1 Clock Cycle = 4 CZ

J

Q (Layer 1) Q’ (Layer 2)

P=1

Latency (in CZ) 6 3 50%

K

P=1

(c) JK ipop Figure 5. QCA implementation of proposed multilayer model of ip-ops

Two most important aspect of the multilayer QCA structure are the radius of effect and the range of layer separation. Radius of effect determines how tightly the cells are interacting with each other within its induced zone. As the distance between the cells increases, the inuence of neighbour on polarization of a cell decreases. When the centre-to-centre distance between the cells exceeds the radius of effect is nil -that is, no inuence of neighbours on polarization of a cell. The minimum layer separation, beyond which the design ceases to work, is preferred since it reduces the volume of QCA chip. However, fabrication of such a design would be difcult and this would be more prone to faults. Table II reports the range of layer separation and radius of effect within which a design can function correctly.

In[6] In[7] In[8] In[5] proposed D

Table II

In[11] In[6] In[12] proposed JK

Table III P ERFORMANCE COMPARISON OF DIFFERENT FLIP - FLOPS Design

In[6] In[9] In[10] proposed T

L AYER CONSTRAINTS OF SR FLIP - FLOP Parameter Radius of effect Layer spacing

Minimum 12.51 nm 4 nm

Maximum no limit 14.48 nm

Cell area Cell count (in μm2 ) D-ipop 0.20 104 0.13 93 0.08 66 0.05 48 0.04 45 T-ipop 0.20 108 0.06 66 0.09 72 0.04 44 JK-ipop 0.74 419 0.12 80 0.06 50 0.05 57

Latency (in Clock zones) 4 6 6 4 3 4 5 5 3 9 4 4 3

As the initial input to the SR FF (Qn ) is not known, the input SR=10 is assumed for setting Q to 1. The vector SR=00 can test s-at-1 at R. With Qn =1, SR=01 detects sat-1 at S and SR=00 and SR=11 test for any up transition fault. Therefore, if the previous tests (SR=00 or SR=11 with Qn =1) result in a s-at-1 fault at the output, the next tests (SR=00 and SR=11) can detect these stuck-at faults. Finally, SR=10 is applied to test a s-at-0 fault. The fault-free simulation results using the test sequence shows that the circuit behaves as a SR FF, according to the state transition table in Table IV. Therefore, the fault free output sequence d 1 1 1 0 0 0 1 is generated. It plays the role of test bench for detecting the faults of SR FF in QCA. We next analyse the behaviour of proposed design under single missing cell and additional cell defect [4]. In Fig. 3(b) and (c), the x, y co-ordinates are used to identify

The multilayer implementation of other ip-ops are shown in Fig. 5. A detail comparison of the ip-ops synthesized in this work and the state-of-the-art designs is reported in Table III. It can be observed from Table III that the proposed designs outperform all the existing design approaches. B. Characterization of proposed SR ip-op In [4], for detecting the effect of a defect in sequential logic, a test sequence is identied. It has good coverage of actual QCA defects. We introduce similar test sequence to evaluate the performance of proposed design methodology. At logic level, this test sequence detects stuck-at faults (s-at1/0) and up/down transition faults. The test pattern for the SR FF is shown in Table IV.

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Figure 6.

QCA layout of 4-bit shift register

Table IV T EST SEQUENCE FOR MULTILAYER SR F LIP - FLOP

1 1 1 0 0 0 1 output when the device is fault-free. Now, according to the grid position of the cell (SR FF), each single cell is deleted from the design (Fig. 3(b) and (c)) and the corresponding outputs are reported in Table V. If the output is correct, then it is not recorded. Only the faulty outputs are recorded. The design has two cells at postilion 7, 5; one at layer 1 and the other at layer 2. Single additional cell defect: According to the grid position of the cell (SR FF), an additional single cell is inserted into the proposed design and the SR ip-op is simulated. There is no faulty output as reported in the simulation results. Therefore, it is evident that the proposed design has 100% fault tolerance under single additional cell defect. The QCA ip-ops found in literature don’t have such feature.

Current state Test vector Operation Fault free Qn SR output d 10 Set 1 1 1 00 Hold 1 1 1 11 Hold 1 1 1 01 Reset 0 0 00 Hold 0 0 0 11 Hold 0 0 0 10 Set 1 1 1 d Check next state Qn+1 d=don’t care ; Fault free output sequence d 1 1 1 0 0 0 1 Table V S IMULATION R ESULTS FOR MULTILAYER SR FLIP FLOP UNDER S INGLE M ISSING C ELL D EFECT Missing Cell

2,3 3,3 4,1 4,2 4,3 4,4 4,5 4,6 5,1 6,1 7,1 7,3 7,4 7,5 9,3

7,5

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Input S at Layer 3

IV. H IGH LEVEL LOGIC SYNTHESIS Design capability and exibility of the proposed model are further evaluated through implementation of 4-bit register (Fig.6). A 4-bit shift register consists of a chain of four cascading D ip-ops, where the output of one ip-op is connected to the input of the next. The shift register is unidirectional. In a right shift register, the data is shifted one bit position to the right at each clock cycle. The simulation result of the proposed multilayer 4-bit QCA register is shown in Fig. 7. The performance of the design is reported in Table VI.

Output, Fault free Qn =d 1 1 1 0 0 0 1 Layer 1 d 1100101 d 1100101 d 1010011 d 1010011 d 0010010 d 1010010 d 1010011 d 1010011 d 1111111 d 1100101 d 1100101 d 1010101 d 1010101 Qn = Qn d 1110001 Qn = Qn d 1110001 Qn = Qn Qn not stable d 1110001 nofault but Qn not stable Layer 2 d 1110001 Qn = Qn Qn not stable

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Figure 7.

the QCA cells in the cartesian layout of the ip ops. Single missing cell defect: The test vector of SR FF identied in Table IV is loaded into the vector table under coherence vector engine set-up of QCADesigner [13] and the proposed SR ip-op is simulated. It produces the d

Simulation result of the 4-bit shift register

V. S YNTHESIS OF COUPLED SR FLIP - FLOP The most important application of proposed layer architecture is synthesis of two ip-ops simultaneously. Two

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(a) Dual SR FlipFlop

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Figure 8.

QCA layout of coupled SR ipop

Table VI P ERFORMANCE OF 4- BIT SHIFT REGISTER

[3] A. Gin, P. D. Tougaw, and S. Williams, “An alternative geometry for quantum-dot cellular automata,” Journal of Applied Physics, vol. 85, no. 12, pp. 8281–8286, 1999.

Design

Cell area Cell count (in μm2 ) 4-bit shift register In[6] 1.27 395 proposed design 0.22 195 Improvement 82% 50%

[4] J. Huang, M. Momenzadeh, and F. Lombardi, “Analysis of missing and additional cell defects in sequential quantum-dot cellular automata,” Integration, the {VLSI} Journal, vol. 40, no. 4, pp. 503 – 515, 2007. [5] S. Hashemi and K. Navi, “New robust {QCA} d ip op and memory structures,” Microelectronics Journal, vol. 43, no. 12, pp. 929 – 940, 2012.

SR ip-ops are coupled together with common input R in three layer architecture as shown in Fig.8. From layer 1 and layer 3, two state variables Q2 and Q1 are generated and Q is generated form layer 2. This design can also be used simultaneously for different applications and can be controlled with R. The design of such sequential circuit enhances the device density with high throughput. All the designs are veried using QCADesigner ver.2.0.3 [13]. In the coherence vector approximation, we use the following parameters: cell size=10nm, dot size=2.5nm, cell separation=2.5nm, radius of effect=40nm, layer separation=11.5nm, other parameters are set as default.

[6] L. A. Lim, A. Ghazali, S. Yan, and C. C. Fat, “Sequential circuit design using quantum-dot cellular automata (qca),” in Circuits and Systems (ICCAS), 2012 IEEE International Conference on, 2012, pp. 162–167. [7] L. rong XIAO, X. xiong CHEN, and S. yan YING, “Design of dual-edge triggered ip-ops based on dot cellular automata,” Journal of Zhejiang University-SCIENCE (Computers and Electronics), vol. 13, no. 5, pp. 385–392, 2012. [8] A. Vetteth, K. Walus, V. Dimitrov, and G. Jullien, “Quantumdot cellular automata of ip-ops,” N.W., Calgary, Alberta, Canada T2N 1N4, 2003. [9] M. Torabi, “A new architecture for t ip op using quantum-dot cellular automata,” in Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on, 2011, pp. 296–300.

VI. C ONCLUSION In this work, an architecture of sequential logic around QCA (quantum-dot cellular automata) is introduced. The multilayer structures for ip-ops are proposed. The area requirement for such a design is reduced signicantly (77% improvements in cell area). The logic so designed can be operated in 3 clocking zone and, therefore, reduces the delay while in operation (50% improvement). The characterization of devices shows that the design proposed in this work is 100% fault tolerant under cell deposition defect.

[10] E.N.Ganesh, L. Kishore, and M. Rangachar, “Implementation of quantum cellular automata combinational and sequential circuits using majority logic reduction method,” International Journal of Nanotechnology and Applications, vol. 2, no. 1, pp. 89–106, 2008. [11] P. Venkataramani, S. Srivastava, and S. Bhanja, “Sequential circuit design in quantum-dot cellular automata,” in Nanotechnology, 2008. NANO ’08. 8th IEEE Conference on, 2008, pp. 534–537.

R EFERENCES

[12] K. Kong, Y. Shang, and R. Lu, “Counter designs in quantumdot cellular automata,” in Nanotechnology (IEEE-NANO), 2010 10th IEEE Conference on, 2010, pp. 1130–1134.

[1] C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein, “Quantum cellular automata,” Nanotechnology, vol. 4, pp. 49– 57, 1993.

[13] K. Walus, T. Dysart, G. A. Jullien, and R. Budiman, “QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata,” Trans. Nanotechnology, vol. 3, no. 1, pp. 26–29, March 2004.

[2] J. Huang, M. Momenzadeh, and F. Lombardi, “Design of sequential circuits by quantum-dot cellular automata,” Microelectronics Journal, vol. 38, no. 4-5, pp. 525–537, Apr. 2007.

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