Digital Carrier Modulation and Sampling Issues of Matrix Converters

Digital Carrier Modulation and Sampling Issues of Matrix Converters P. C. Loh1, R. J. Rong1, 2, F. Blaabjerg2 and P. Wang1 1

2

School of Electrical and Electronic Engineering Nanyang Technological University 50 Nanyang Avenue, S639798 SINGAPORE

Institute of Energy Technology Aalborg University Pontoppodanstraede 101, DK-9220, Aalborg East DENMARK

Abstract- Although the modulation of ac-ac matrix converters using space vector theory has long been established, their carrierbased modulation principles have only recently attracted some attention. Reasons commonly stated for evaluating the carrierbased alternative include simpler converter control because of its inherent auto-sequencing process, and easier implementation using fast on-chip timers embedded in most modern digital signal processors. Motivated by these likely merits, which have previously been proven for dc-ac inverters, an investigation is now pursued here to develop appropriate digital carrier modulation schemes for controlling conventional and sparse matrix converters with minimized semiconductor commutation count and smooth sextant transitions with no erroneous states produced. For guaranteeing the latter two features, correct digital sampling instants and state sequence reversal must be chosen appropriately, as demonstrated in the paper for the two different topological options, which to date, have not yet been discussed in the existing literature. To validate the concepts discussed, experimental testing on the implemented conventional and sparse matrix laboratory prototypes was performed with their respective results captured and presented in the paper for visual confirmation.

numerous modulation techniques for controlling matrix converters with the common aim being to widen the knowledge pool for matrix converters so as to further propel their wide-spread usages in the industry. Although encouraging, most of the reported modulation schemes are still relatively complex, involving either multiorder matrix computation [1] or two-dimensional vector manipulation [2], and sometime both. Because of that, [3] and [4] have started investigating structurally different carrierbased modulation schemes for controlling conventional (Fig. 1, [1-10]) and sparse (Fig. 2, [4-8, 11]) matrix converters respectively, where it is shown that the auto-state generation process of a carrier-based modulator can comfortably help to simplify the realization of the matrix modulation. Indeed, [3, 4] have clarified some preliminary concepts, but for smoother operation, issues like state placement and sequencing, choices of digital sampling instants and synchronization must also be addressed, but have not yet been collectively explained in both SRA

I.

INTRODUCTION

SYA VAN

Among the different types of converters reported to date, ac-ac matrix converters are known to be the universal energy processors that can theoretically convert any three-phase input ac source to an alternative output supply with variable amplitude and frequency. Besides this generic functionality, matrix converters, being “all-semiconductor” solutions, allow compact and robust converters to be built since bulky inductive storages and electrolytic capacitors with usually a short lifespan are not needed for their proper operations. Although appearing attractive, matrix converters are still not finding wide-ranging applications in the industry, and one reason for that might be their physical complexities with usually eighteen unidirectional semiconductor switches needed for their implementations. (Lower switch count circuitries have indeed been proposed previously, but are almost always attained at the expense of some performance features). Moreover, those switches must ideally be controlled so as to simultaneously produce a three-phase set of sinusoidal output voltages and a second set of sinusoidal input currents, which definitely is more complex than the control of other converter topologies. Because of this tedious but challenging level of complexity, many researchers have since proposed

978-1-4244-1874-9/08/$25.00 ©2008 IEEE

SWA

AC Source

Lf

iR1 iY1

SRB

iR

VRN

iW1

SYB

iY

VYN

VWN

VBN

SWB

iW

SRC

Cf

SYC VCN

SWC

Fig. 1. Conventional matrix converter topology. Bidirectional Rectifier

Traditional Two-Level Inverter ii

AC Source

Lf

SR

SY

SW

iR1 iY1

SA

SB

SC

iR

VRN

VAN VBN

vi

iY

VYN

iW

VWN

VCN

iW1 Cf

SR'

SY'

SW' SA'

SB'

Fig. 2. Sparse matrix converter topology.

231

SC'

iR

Bidirectional Rectifier ii

SY, SR'

SR Cf

SA

SB

SC

VCN

SW,SR'

Cf SY'

iY

SA'

SB'

3

2

5

SR,SW'

θ 1

Null

4

VAN VBN

vi = vRY

Reference Phasor

SY,SW'

Traditional Two-Level Inverter

6

SR,SY'

SW,SY'

SC'

1) Only ON Switches are shown 2) Null = {SR,SR'} OR {SY,SY'} OR {SW,SW'}

Fig. 3. Simplified representation of sparse matrix converter when front-end CSR is in state {SR, SY’}.

Fig. 4. Space vector diagram of input CSR.

SW’} turned ON at any instant. Certainly, the upper and lower switches can be from the same input phase giving rise to a dc freewheeling state, but for imposing the maximum average dclink voltage vi across the rear-end VSI, the switches should preferably be from different phases so that vi always assumes one of the three input line voltages expressed as vJK, where {J, K} = {R, Y, W} and J ≠ K. For example, when SR and SY’ are commanded ON, line voltage vRY (=vRN – vYN) appearing across the R- and Y-phase filter capacitors is imposed across the dclink, as demonstrated in Fig. 3, where only the conducting CSR switches are shown. The drawn circuit in Fig. 3 clearly resembles a traditional two-level VSI, but with a varying input dc source voltage, whose expression can be determined by first considering the duty ratios of the different input CSR states, discussed as follow.

papers. Specifically, it can conveniently be shown that if the sampling instants and state sequences are not chosen correctly, extra device switching is generated undesirably, which to an unfavorable extent, lowers the converter efficiency. In addition, rather than having two different schemes for controlling two different topologies, it certainly is advantageous to have a common set of modulation principles designed for controlling both commonly adopted matrix converters with only minor modifications needed when modifying the topological layout. This latter issue similarly has not yet been pursued, which together with the earlier described issues, form the themes of investigation for this paper. It is expected that the concepts documented in this paper can further smoothen the realization of a simple generic matrix modulator using modern digital signal processors (DSPs) with multiple on-chip timers embedded on a single common wafer used for precise digital carrier generation. For validating the practicality and performance of the presented generic scheme, a laboratory prototype, which can freely be configured as either the conventional or sparse matrix structure, was constructed and tested with the experimental results presented in a later section for confirmation. II. OPERATIONAL PRINCIPLES AND MODULATION OF SPARSE MATRIX CONVERTER The generic carrier-based modulation and sampling concepts discussed in this paper are better explained using the indirect space vector modulation (SVM) theory [2], which is now a well-known method commonly adopted by researchers. While describing the indirect SVM scheme, it is also advantageous to spontaneously describe the sparse matrix topology, which conceptually can be viewed as an indirect alternative approach for realizing ac-ac energy conversion. For illustrating its operating principles, the sparse matrix topological arrangement is drawn in Fig. 2 [4-8], where a bidirectional current-source rectifier (CSR) is shown cascaded to a traditional two-level voltage source inverter (VSI) without any intermediate energy storage element connected in between. This “non-integrated” nature of the sparse matrix converter, where rectification and inversion stages can clearly be distinguished, allows it to be controlled using the properly synchronized indirect SVM scheme with virtually zero switching loss achieved at its input rectification stage. To be precise, the converter can be controlled by first modulating the input CSR front-end with always one upper switch {SR, SY or SW} and one lower switch {SR’, SY’ or

232

A. Control of Bi-Directional CSR As noted from Fig. 4, the front-end bi-directional CSR can typically assume six finite active states and three null states, but as mentioned earlier, the null states should not be used since they lower the maximum average voltage appearing across the dc-link of the rear-end VSI, and hence its “input-tooutput” voltage transfer gain. Therefore, within a single switching cycle, preferably only the two nearest space vectors to the reference current phasor should be used for simultaneously minimizing the switching loss and high frequency input harmonic content. That would imply that for the example shown in Fig. 4, only states {SR, SY’} and {SR, SW’} should be used for producing the reference phasor in sextant 1 (-30°≤θ≤30°), whose phase orientation is synchronized with respect to the measured grid voltages, depending on the specified input power factor. Using only states {SR, SY’} and {SR, SW’} also means that phase R is always clamped to the positive dc rail with only phases Y and W pulse-width modulated to the negative dc-rail by commutating SY’ and SW’. Assuming a unity input power factor and by noting that the sum of a set of balanced input voltages {vR, vY, vW} gives zero, the duty ratios δY and δW used for gating SY’ and SW’ are then determined as [5, 6]: v R = Vm cos(θ R ) ; vY = Vm cos(θ Y ) ; vW = Vm cos(θW ) vY vW − = δ Y + δW = 1 vR vR v cos(θW ) v cos(θ Y ) ; δW = − W = − δY = − Y = − vR cos(θ R ) vR cos(θ R ) v R + vY + vW = 0 ⇒ −

(1)

Clamping of Phase R to Upper DC Rail (Sextant 1 of CSR) 1

δY

0 CSR

CSR Commutations SR,SY'

SR,SY'

SR,SW' SR,SW'

δ1T

δ2T T

(a) 1

δY

CSR Commutations

0 CSR

SR,SY'

SR,SW'

δ1T

δ2T T

SR,SY'

SR,SW'

Unnecessary Commutation

(b) Fig. 5. Input CSR modulation of sparse matrix converter.

where Vm is the input voltage amplitude, and θJ (J = R, Y, W) is the respective phase angular displacement. The same duty ratio expressions given in (1) can equally be used for the fourth 150°≤θ≤210° sextant, during which phase R is clamped to the negative dc rail, while phases Y and W are modulated to the positive dc rail. Further generalizing the expressions for the other sextants, (1) can be rewritten as: v for positive dc rail clamping ⎧−v δ 1 = ⎨ min max ⎩− vmax v min for negative dc rail clamping ⎧ − v mid v max ⎩− v mid v min

for positive dc rail clamping for negative dc rail clamping δ1 ≥ δ 2 vmax = max(v R , vY , vW ) ; vmid = mid(v R , vY , vW ) vmin = min (v R , vY , vW ) (2) where using (2), the division of a switching cycle between the two active states can be effected by using an up/down digital timer for producing the triangular carrier, as illustrated in Fig. 5(a). Instead of the triangular carrier, an alternative saw-tooth wave shape, shown in Fig. 5(b), is proposed in [4], which although still performs the time division well, but will unnecessarily introduce an extra commutation to each carrier cycle, as indicated in Fig. 5(b). This extra switching introduces no additional benefit, and should therefore be avoided, but before adopting the triangular carrier, it is important to prove that the converter can still maintain smooth operation without multi-phase commutations, while crossing from one sextant to the other. For demonstrating that, Fig. 6 gives an example of the reference phasor crossing over from sextant 6 to 1 with two different scenarios likely to happen depending on whether the data sampling is initiated at the peaks or troughs of the triangular carrier. As seen, if the sextant transitional information is fed into the processor upon reaching the first carrier peak, the shorter state of {SW, SY’} before the transition is immediately replaced by state {SR, SW’}, which is the second nearest active state in sextant 1 other than {SR, SY’}. (Note that around the immediate instant of sextant transition, states {SW, SY’} and {SR, SW’} have durations

δ2 = ⎨

near approaching zero since they are further away from the reference phasor, as compared to {SR, SY’}). Ideally, that replacement will not result in any waveform distortion, but practically, four undesirable commutations are needed for turning SW and SY’ OFF, and SR and SW’ ON. Fortunately, these additional commutations can be avoided by sampling at the carrier troughs instead, where an example illustration is also given in Fig. 6. Although the transitional data is now delayed from processing by slightly longer than half a carrier cycle, sampling at the first carrier trough immediately after the sextant transition would give rise to state {SR, SY’} being used continuously throughout the crossover with no additional commutation needed. Therefore, to avoid incurring additional switching loss, the trough sampling approach is recommended as the preferred choice for modulating the input CSR stage of a sparse matrix converter. Before ending the discussion on CSR modulation, the mathematical equation governing the “per-switching-cycle” average dc-link voltage Vi(av) appearing across the rear-end VSI is derived, since it can later be used in the VSI control for canceling out the dc-link variation, as discussed in Section II(B). For that derivation, the observation of measuring vi = v RY and vi = v RW when in states {SR, SY’} and {SR, SW’} respectively is noted. Then, by applying state-space averaging and using (2) to calculate the respective duty ratios, the generalized dc-link voltage Vi(av) is derived as: 3V 2 Vi ( av ) = m for positive rail clamping 2 v max Vi ( av ) =

3Vm2

for negative rail clamping (3) 2 v min where the inverse variation of Vi(av) with respect to either | Vmax | or | Vmax | is clearly indicated, and should ideally be compensated for the rear-end VSI modulation, as discussed in the next section.

B. Control of Rear-End VSI Carrier-based modulation of a traditional VSI with a fixed dc source is by now a well-known technique, where three 120° phase-shifted sinusoids are used for comparison with a common triangular carrier for generating the required VSI gating signals. Although conceptually simple, the adoption of the VSI modulation technique for sparse matrix control would still require some fine-tunings, where the first is to normalize the amplitude Vo of the three-phase sinusoids using (3). The resulting set of references then has a time-varying modulation ratio M(t) embedded, unlike the traditional case where a fixed ratio is used, and is expressed as: M (t ) = Vo (Vi (av ) / 2) vA =

Vo cos(θ A ) + Voff Vi ( av ) 2

v B = M cos(θ B ) +

233

2Voff Vi ( av )

= M cos(θ A ) +

2Voff Vi ( av )

; vC = M cos(θ C ) +

2Voff Vi ( av )

(4)

Clamping of Phase R to Upper DC Rail (Sextant 1 of CSR) 1

δY

CSR 0

CSR Commutations SR,SY'

N0 A1 N1

Rear-End VSI

A1

A2

A1 N0

N0

N0

N0 = {-,-,-} A1 = {+,+,-} A2 = {+,-,-} N1 = {+,+,+}

Fig. 6. Different sampling scenarios during sextant 6 to 1 transition of the input CSR stage.

SR,SY'

SR,SW' SR,SW'

A2

A1

N1

A2 N1 N1 A2

Ref. Va Ref. Vb

+ = Upper DC Rail - = Lower DC Rail

Ref. Vc δ1T

where vX is the normalized output reference with phase angle θX (X = A, B, C), and Voff is the triplen offset commonly

δ2T T

(a)

added to gain an enhanced maximum ratio of 2 3 = 1.15 for M. Using these values, the maximum input-to-output transfer V 2 3 1 3 , which indeed is gain is derived as o = × × = Vm 2 3 2 2 the theoretical maximum gain attainable by a matrix converter. Proceeding on, the second alternation needed is pictorially illustrated in Fig. 7, where synchronization between the input CSR and output VSI is demonstrated. An immediate observation noted from the figure is that the carrier used for the rear-end VSI is different from that of the CSR, since it has rising and falling triangular edges with constantly varying gradients. The intention for having different gradients is to force each triangular edge to span a complete CSR switching state duration expressed as either δ1T or δ2T, where δ1 and δ2 are the CSR duty ratios computed using (2). Synchronizing in this way ensures that a complete inversion state sequence comprising of “N1{+,+,+} ↔ A1{+,+,−} ↔ A2{+,−,−} ↔ N0{−,−,−}” (see notations used in Fig. 7) is placed within each imposed CSR switching state to always give the correct volt-sec average for each VSI half carrier cycle using the applied dc-link voltage corresponding to the assumed CSR state. In addition to tracking accuracy, synchronizing the VSI carrier with the CSR state intervals can conceptually eliminate the CSR switching loss since each CSR commutation instant occurs in state N0{−,−,−}, as demonstrated in Fig. 7(a), during which no dc-link current flows. Alternatively, the inverted carrier shown in Fig. 7(b) can be used with the CSR commutation now occurring within state N1{+,+,+}. Although two carrier options are available, a comment to emphasize here is that they should not be used interchangeably throughout the reference fundamental cycle, like for example, using the carrier in Fig. 7(a) for even CSR sextants {2, 4, 6} and the inverted carrier in Fig. 7(b) for odd sextants {1, 3, 5}. Doing so would cause the rear-end VSI to experience threephase simultaneous switching at instants of sextant transition (or carrier reversal), which obviously has no performance merit. Instead, it introduces uncertainties to the system since the VSI state, during the dead-time duration of the simultaneous switching, is solely determined by the directions of the three-phase current flows. Therefore, carrier reversal

234

Clamping of Phase R to Upper DC Rail (Sextant 1 of CSR) 1

δY

CSR 0

CSR Commutations SR,SY'

N1 A2

Rear-End VSI

N0

A2

A1

N0 = {-,-,-} A1 = {+,+,-} A2 = {+,-,-} N1 = {+,+,+} + = Upper DC Rail - = Lower DC Rail

SR,SY'

SR,SW' SR,SW' A2 N1

N1

N1

A1

A2

N0

A1 N0 N0 A1

Ref. Va Ref. Vb Ref. Vc δ1T

δ2T T

(b) Fig. 7. Rear-end VSI modulation of sparse matrix converter using (a) noninverted and (b) inverted carriers.

should be avoided for the sparse matrix converter, but not the conventional matrix converter, as discussed next. III. OPERATIONAL PRINCIPLES AND MODULATION OF CONVENTIONAL MATRIX CONVERTER Unlike the sparse matrix topology, the conventional “integrated” matrix converter shown in Fig. 1 has no clear distinction between its input rectification and output inversion stages. Instead, its eighteen switches are now arranged to form a 3×3 bi-directional matrix for connecting the output phases to any of the input phases. Therefore, at any instant, only three switches, one each from {SRA, SYA, SWA}, {SRB, SYB, SWB} and {SRC, SYC, SWC}, will be conducting to avoid shorting the input phases and to preserve current continuity of the output phases. Despite its “integrated” nature, the abovedescribed indirect carrier modulation principles can still be used for controlling the conventional matrix converter by introducing some digital mapping logic for combining those intermediate CSR and VSI signals produced by the indirect carrier modulator. As an example, consider switch SRA in Fig. 1, which will turn ON only if indirect signals generated for {SA AND SR} OR {SA’ AND SR’} are ON (see Fig. 2 for the notations used). In logic equation form, that means: SJX = {SX & SJ} | {SX’ & SJ’} J = R, Y, or W and X = A, B or C (5) where “&” and “|” refer to the logical AND and OR operators respectively. Comparing with earlier findings reported in [3], extending from the indirect method presented in Section II gives rise to a simpler carrier-based modulator

CSR transition but no switching for conventional matrix

Intermediate Signals N0 = {-,-,-} A1 = {+,+,-} A2 = {+,-,-} N1 = {+,+,+}

CSR SW, SY'

SR, SY'

VSI

Conventional Matrix

N1

A1

A2

N0

SRA SRB SRC

SRA SRB SYC

SRA SYB SYC

SYA SYB SYC

A2

A1

N1

SWA SWA SYB SWB SYC SYC {SWA,SWB,SWC} δ2T

δ1T T

(a) CSR transition causes unwanted switching of conventional matrix

Intermediate Signals

CSR

N0 = {-,-,-} A1 = {+,+,-} A2 = {+,-,-} N1 = {+,+,+}

VSI

SW, SY'

SR, SY' N0

N1

A1

A2

A1

A2 N0

{SWA,SWB,SWC}

Conventional Matrix

SYA SYB SYC

SRA SYB SYC

SRA SRB SYC

SRA SRB SRC

SWA SWA SWB SYB SYC SYC {SYA,SYB,SYC} δ2T

δ1T T

(b) Fig. 8. Gating signal generation for conventional matrix converter when in Sextant 6 using (a) carrier in Fig. 7(a), and (b) carrier in Fig. 7(b).

for the control of the conventional matrix converter. To be more specific, the method discussed in [3] uses different offset equations for the two CSR intervals in a switching cycle, and a more complex dc-link compensation technique, which certainly are harder to realize in practice. In addition to the add-on logic, re-evaluation of data sampling is recommended to be certain that smooth operation of the converter within each sextant and during sextant transitions is guaranteed over the full fundamental reference cycle. For ensuring that, an important operating criterion to follow is to enforce the use of carrier in Fig. 7(a) for even sextants {2, 4, 6} on the CSR vector diagram in Fig. 4, and carrier in Fig. 7(b) for odd sextants {1, 3, 5}. Doing so ensures that the upper CSR signal SJ (J = R, Y, or W) at instants of CSR commutation in sextants {2, 4, 6} will not cause unwanted switching of the conventional matrix converter if the statuses of the other signals are kept unchanged. As an example, consider the case where the CSR reference phasor is residing in sextant 6 of the vector diagram in Fig. 4. The active states used per switching cycle are then determined as {SW, SY’} and {SR, SY’} with phase Y clamped to the negative dc rail, and the upper signals (SW and SR) of phases W and R commutated at a predefined time instant in each half carrier cycle (see Fig. 8). Despite the occurrence of the SJ transition, the corresponding switches {SWA, SWB, SWC} and {SRA, SRB, SRC} of the conventional matrix converter will not commutate unnecessarily, as demonstrated in Fig. 8(a), if the carrier in Fig. 7(a) is used. The explanation for that is deduced from the observation that all VSI signals SX (X = A, B and C) remain OFF when the CSR signals SJ (J = W and R) transits in state N0{−,−,−} produced by the recommended carrier. With SX = OFF and according to the first term in (5), the transition of SJ is masked out without disturbing the eventual gating signals SJX feeding to the conventional matrix converter. On the other hand, if the carrier in Fig. 7(b) is used

235

instead, the prevailing condition at the instant of SJ transition is SX = ON since the VSI state N1{+,+,+} is assumed throughout the transition, as demonstrated in Fig. 8(b). Having SX = ON and according to (5), the transition of SJ is unfortunately matched to unwanted switching for the conventional matrix converter. Applying the same analysis to the odd sextants {1, 3, 5} on the vector diagram reveals that the transition of SJ’ (positive rail clamping and negative rail modulation) will not cause SJX of the conventional matrix converter to switch unnecessarily if the carrier in Fig. 7(b) is used. The foreseen reason is again deduced from (5), but now using its second term, which states that any transition in SJ’ is hidden by the condition of SX’ = OFF when in state N1{+,+,+}. Therefore, the transition in SJ’ will not propagate to the corresponding switches of the conventional matrix converter, which is precisely what the paper has aimed to achieve. Faced with the above-described carrier reversal requirement, the correct sampling instants must now be determined for the conventional matrix converter so as to avoid multi-phase switching during the carrier inversion process. Again for digital implementation, data sampling can either be performed periodically at the peaks or troughs of the input CSR carrier, from which the atypical VSI carrier is derived. For peak sampling, Fig. 9(a) shows the likely scenario that can occur immediately after transiting from sextant 6 to 1. As seen, the intermediate CSR signals change from SW = SY’ = ON to SR = SW’ = ON, while the VSI signals change from SA = SB = SC = ON to SA’ = SB’ = SC’ = ON. Despite these changes, it can interestingly be shown by substituting the intermediate logic signals to (5) that the conventional matrix converter remains at the same null state with SWA = SWB = SWC = ON throughout the whole sextant transitional process with no multi-phase switching noted (see zoom-IN view in Fig. 9(a)). This indeed is the preferred option, whose smooth transitional advantage can practically be guaranteed by using flip-flop logic to stabilize all gating signals before outputting them simultaneously for driving the matrix converter. By doing this, a slight nanosecond delay is effectively introduced for filtering off any transitional glitches that can realistically happen in practice. For completeness and comparison, Fig. 9(b) shows the case where trough sampling is noted to cause the CSR signals to remain unaltered at SR = SY’ = ON, while the VSI signals change from SA = SB = SC = ON to SA’ = SB’ = SC’ = ON. Substituting these values to (5) clearly reveals that when used for controlling a conventional matrix converter, the converter “jumps” from the null state with SRA = SRB = SRC = ON (all output phases tied to input phase R) to another null state with SYA = SYB = SYC = ON (all output phases tied to input phase Y) at the immediate instant of sextant traversing (see zoom-IN view in Fig. 9(b)). Clearly, the instantaneous switching of null states is unnecessary since the same set of zero three-phase line voltages is still observed at the converter output, implying that there isn’t any gain in performance merit.

and 50 Hz, and to shunt the source from the high frequency switching ripple produced by the converter, a second order filter with Lf = 2 mH and Cf = 36 µF was connected to the source output terminals, as illustrated in Fig. 1 and Fig. 2. For lightly damping off any triggered input resonance, an additional damping resistance of Rf = 10 Ω was also explicitly connected across Lf to get a more recognizable sinusoidal wave-shape for the input current. Beginning with the sparse matrix topology, Fig. 10 shows the CSR and VSI gating signals evaluated using the logic design platform provided by Lattice Semiconductor for its range of complex programmable logic devices. For the CSR signals, they are obtained by “OR-ing” the upper and lower gate signals per input phase (= SJ OR SJ’, where J = R, Y or W) to give a logic of “1” for one switch ON and a logic of “0” for all switches OFF for that particular phase. In addition, for compactness (to meet the page limit without degrading quality), the three CSR signals are drawn in one plot with ONlevels 1.2, 1 and 0.8 used to represent signals feeding directly to input phases R, Y and W respectively. With the four VSI carrier periods explicitly drawn on the diagram, Fig. 10 indeed shows the commutations of the CSR signals only at the peaks of the triangular carrier and only in state N0{−,−,−} of the VSI with zero switching loss expected (see Fig. 7(a)). In addition, no switching complication is noted at the indicated sextant commutation with each VSI signal noted to switch only once in each half carrier cycle before and after the commutation (signals to the lower switches are not shown since they are simply the complement of their respective upper counterparts). After confirming the appropriateness of the gating signals, they were routed to the constructed sparse matrix converter, whose experimentally captured 50 Hz input and 30 Hz output waveforms are presented in Fig. 11. Clearly, the output voltage waveform switches smoothly with no prominent glitches noted throughout the full fundamental cycle. Also noted in the figure is the presence of slight oscillatory ripple superimposed on the input current, which is mainly caused by LC resonance of the lightly damped second-order input filter and the relatively low carrier frequency of 2.5 kHz used for switching the front-end CSR. With the laboratory setup reconfigured as a conventional matrix converter, Fig. 12 shows the intermediate CSR signals and the eventual gating signals SJX (J = R, Y or W and X = A, B or C) produced for driving the converter. As predicted, before the carrier reversal at the indicated sextant commutation, the intermediate CSR signals switch only at the troughs of the carrier, and after the inversion, they switch at the peaks. Also noted in the figure are the once per half carrier cycle switching of SJX, and the avoidance of unnecessary switching at the indicated instant of sextant commutation even though the intermediate CSR signals are changing. With these verified signals now directed to the converter, Fig. 13 shows the corresponding set of recorded experimental results, where a close similarity is noted with those waveforms shown in Fig.

Instant of Sextant 6 to 1 Transition Peak Sampling

1

δR

δY

CSR 0

CSR Commutations SR,SY'

N0 A1 N1

Rear-End VSI

A1

SR,SY'

SW,SY' SR,SW' A2 N1

N0

A2

N0 = {-,-,-} A1 = {+,+,-} A2 = {+,-,-} N1 = {+,+,+}

N1

A1

A2

N0

A2 N1 N0 A1

Ref. Va Ref. Vb

+ = Upper DC Rail - = Lower DC Rail

Ref. Vc δ1T

δ2T T

No switching SWA SWB SYC

Conventional Matrix

SWA SWB SWC

SRA SWB SWC

(a) Instant of Sextant 6 to 1 Transition 1

δY

δR

CSR 0

Trough Sampling CSR Commutations SR,SY' SR,SW' SR,SY'

SW,SY'

N1 A2

A1 N0 N0

Rear-End VSI N0 = {-,-,-} A1 = {+,+,-} A2 = {+,-,-} N1 = {+,+,+}

A2

A1

N1 N0

A2

A1

N1 A1 N0

N1 A2

Ref. Va Ref. Vb

+ = Upper DC Rail - = Lower DC Rail

Ref. Vc δ2T

δ1T T

Six extra switching

Conventional Matrix

SRA SRB SYC

SRA SRB SRC

SYA SRA SYB SYB SYC SYC

(b) Fig. 9. Sampling scenarios during sextant 6 to 1 transition: (a) peak sampling and (b) trough sampling.

Therefore, to avoid the unnecessary switching loss and likely uncertainties associated with the multi-phase switching, peak sampling (rather than trough sampling) is found to merge better with the proper operation of a conventional matrix converter. Notably, this finding is different from the trough sampling requirement demanded by the sparse matrix topology. IV. EXPERIMENTAL RESULTS The proposed generic carrier modulation scheme with the appropriate sampling logic incorporated was programmed to a DSP and a programmable logic device, whose main functionalities are to generate the commutation logic and matching logic expressed in (5), if needed. The resulting controller setup was next interfaced to a constructed matrix prototype that could easily be configured to either the conventional or sparse matrix topology. The resulting system was then powered by an input ac source set to ≈110 V(rms)

236

Fig. 10. Logic signals for driving sparse matrix converter without carrier reversal at sextant commutation.

Fig. 12. Logic signals for driving conventional matrix converter with carrier reversal at sextant commutation.

Fig. 11. Experimental waveforms of sparse matrix converter controlled using generic carrier modulation.

Fig. 13. Experimental waveforms of conventional matrix converter controlled using generic carrier modulation.

11 for the sparse matrix converter. This is expected since the same generic carrier modulator was used for controlling both converters with only minor sampling modification needed for removing unwanted multiphase switching, as discussed in the earlier sections. The conceptual formulations presented in the paper are therefore verified with promising results obtained for both converters.

REFERENCES [1]

A. Alesina and M. Venturini, “Analysis and design of optimum amplitude nine-switch direct ac-ac converters”, IEEE Trans. Power Electron., vol. 4, pp. 101-112, Jan. 1989. [2] L. Huber and D. Borojevic, “Space vector modulated three-phase to three-phase matrix converter with input power factor correction”, IEEE Trans. Ind. Applicat., vol. 31, pp. 1234-1246, Nov/Dec. 1995. [3] Y. D. Yoon, and S. K. Sul, “Carrier-based modulation technique for matrix converter”, IEEE Trans. Power Electron., vol. 21, pp. 1691-1703, Nov. 2006. [4] B. Wang, and G. Venkataramanan, “A carrier-based PWM algorithm for indirect matrix converters”, in Proc. IEEE-PESC’06, 2006, pp. 27802787. [5] L. Wei and T. A. Lipo, “A novel matrix converter topology with simple commutation”, in Proc. IEEE-IAS’01, 2001, pp. 1749-1754. [6] J. W. Kolar, M. Baumann, F. Schafmeister and H. Ertl, “Novel threephase ac-dc-ac sparse matrix converter Part I: derivation, basic principle of operation, space vector modulation, dimensioning”, in Proc. IEEEAPEC’02, 2002, pp. 777-787. [7] M. Baumann, F. Stogerer and J. W. Kolar, “Novel three-phase ac-dc-ac sparse matrix converter Part II: experimental analysis of the very sparse matrix converter”, in Proc. IEEE-APEC’02, 2002, pp. 788-791. [8] C. Klumpner and F. Blaabjerg, “Modulation method for a multiple drive system based on a two-stage direct power conversion topology with reduced input current ripple”, IEEE Trans. Power Electron., vol. 20, pp. 922-929, Jul. 2005. [9] P. W. Wheeler, J. C. Clare, L. Empringham, M. Bland and K. G. Kerris, “A vector-controlled MCT matrix converter induction motor drive with minimized commutation times and enhanced waveform quality”, IEEE IAS Magazine, pp. 59-65, Jan/Feb. 2004. [10] P. W. Wheeler, J. C. Clare, L. Empringham, M. Apap and M. Bland, “Matrix converters”, IEEE Power Eng. Journal, pp. 273-282, Dec. 2002. [11] J. Holtz and U. Boelkens, “Direct frequency converter with sinusoidal line currents for variable speed ac motors”, IEEE Trans. Ind. Electron., vol. 36, pp. 475-479, Aug. 1989.

V. CONCLUSION This paper presents a generic carrier modulation scheme for controlling both conventional and sparse matrix converters. For ensuring their smooth operations, sampling-related complications are analyzed, and suitable sampling instants are identified. Specifically, for the sparse matrix topology, where only a single carrier orientation is used for the full reference cycle, sampling at the carrier troughs is recommended since it avoids multiphase switching. In contrast, peak sampling is noted to give a lower commutation count for the conventional matrix converter, which uses alternate carrier orientations. In spite of that difference, both converters when controlled using the same generic modulator are expected to produce similar input and output waveforms (as confirmed experimentally) so long as the appropriate sampling sequence is digitally programmed to the microprocessor.

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