Digital Circuit Design

DIGITAL DESIGN

Edited by Chu Yu

Digital Circuit Design  Primary Logic Gates

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DIGITAL DESIGN

Edited by Chu Yu

 Boolean Algebra  Commutative law of addition and multiplier: A+B = B+A AB = BA  Associative law of addition and multiplier: A + (B + C) = (A + B) + C A(BC) = (AB)C  Distributive law: A(B + C) = AB + AC (A + B)(C + D) = AC + AD + BC + BD

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DIGITAL DESIGN

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 Sum of Product (SOP)  F(A, B, C) = A’B C’ + AB’C + ABC = (2, 5, 7)

 Product of Sum (POS)  F(A, B, C) = (A’+B+ C’)(A+B’+C)(A+B+C) = (5, 2, 0)

 Exchange Between SOP and POS  (0, 2, 6, 7) = (1, 3, 4, 5)

 Standard Term  The term contains all the input variable.  EX: F(A, B, C) = A’BC + ABC + AC to be not a standard term

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 Dual Theorem 

F D(X1, X2, … Xn, 0, 1, +, •) = F(X1, X2, … Xn, 1, 0, •, +) EX: F = AB + AB ＝ (A+B)•(A+B) = AB + AB

 DeMorgan’s Theorem 

F ‘(X1, X2, … Xn, 0, 1, +, •) = F(X1’, X2’, … Xn’, 1, 0, •, +) Ex: A+B = AB , ABC = A+B+C

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 Shannon Theorem  F (xn-1, xn-2, … ,x0) = xn-1F(1, xn-2, … ,x0) + x’n-1F(0, xn-2, … ,x0)  F(xn-1, xn-2, … ,x0) = [xn-1+F(0, xn-2, … ,x0)] • [x’n-1+F(1, xn-2, … ,x0) ]  F(xn-1, xn-2, … ,x0) = xn-1 xn-2 … x0F(1, 1, … ,1) + xn-1 xn-2 … x’0F(1, 1, … ,0) + … + x’n-1 x’n-2 … x’0F(0, 0, … ,0) 2 n 1

=

a m k 0

k

k

where a0 = F(0,0, … ,0) , a1 = F(0,0, … ,0,1) , … , n-2

a2

= F(1, 1, … ,1,0) , a2

n-1

= F(1, 1, … ,1)

and m0 = x’n-1 x’n-2 … x’0 , m1 = x’n-1 x’n-2 … x0 , … , m2

n-2

n-1

= xn-1 xn-2 … x’0 , m2

= xn-1 xn-2 … x0 Page: 6

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 Variable-Entered Map xy

00

01

10

11

0

B’

0

0

A

1

1

B



1

z

 set all external variables to 0 xy

00

01

10

11

0

0

0

0

0

1

1

0



1

z

y’z

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 set one variable to 1 only, and change “1” in the original map to  xy

00

01

10

11

0

1

0

0

0

1



0





z

B’x’y’  repeat step 2, until all variables are applied xy

00

01

10

11

z

0

0

0

0

0

1



1





z

Bz

xy

00

01

10

11

0

0

0

0

1

1



0





Axy’ F = y’z + Axy’ + Bz + B’x’y’ Page: 8

DIGITAL DESIGN

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DIGITAL DESIGN

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列表法 (The Tabulation Method)

F(w, x, y, z) = w’x’y’ + x’z’ + wy

1. Group binary representation of the minterms according to the number of 1’s contained. 2. The minterms of one section are compared with those of the next section down only. Any two minterms that differ from each other by only one variable can be combined, and the unmatched variable removed. 3. Repeat step 2, until all terms are unchecked. 4. The uncheck terms form the prime implicants. Page: 10

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Selection of Prime Implicants  

x’y’z w’xz’ w’xy  xyz wyz  wx’

1, 9 4, 6 6, 7 7, 15 11, 15 8, 9, 10, 11

1 x

4 x





6 x x



7

8

9 x

10

11

15

yz wx 00 01

11

10

01 1

1

1

11

1

00

x x x

x

x

x x









x x

10 1

1

1

1

1

F(w, x, y, z) = x’y’z + w’xz’ + wx’ + xyz  Each prime implicant is represented in a row and each minterm in a column (marked by one ‘X’ symbol)  Columns containing only a single X mark a check () on the corresponding position of the last row and the X’s corresponding row (essential prime implicant).  Next check each column whose minterm is covered by the selected essential prime implicants. (marked by ‘*’)  A minimum set of prime implicants is chosen that covers all the minterms in the function. Page: 12

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 PLA

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 Example  Design a circuit to implement a function X 2 + 3X + 1, where variable X is a 2-bit input data. Sol:

x1 x0 x1 x0 x1x0 x0 x1 x1x0 x1+x1x0 x1

p3

p2

0 x0  x2 x0 0 3x x1 x0 1 p1 p0

p0 = x0 + 0 + x0 + 1 = 1 p1 = x0 + x0 + x1 = x1 p2 = x0 + x1+ x1x0 + x1 = x0 + x1x0 p3 = x1 + “p2’s carry” p4 = p3’s carry x1

p4

x1x0 x0

HA

HA

p3

p2

x1

1

p1

p0 Page: 16

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 Static Hazard  Since the propagation delay (Tpd) for each of gates is different, the output of the circuit may be occur errors when its input signal is changed.  Example: F(x, y, z) = x’y + xz

x xz x’ x’y x’y+xz

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 K-Map yz 00

x

01

0 1

1

11

10

1

1

1

F = x’y + xz + yz x’ y x z

F

y z Page: 18

DIGITAL DESIGN

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 Flip-Flop Characteristic Table  RS-type FF

 JK-type FF

J K

Q(t+1)

S R

Q(t+1)

0 0 1 1

Q(t) 0 1 Q’(t)

0 0 1 1

Q(t) 0 1 ?

0 1 0 1

0 1 0 1

 T-type FF

 D-type FF

D

Q(t+1)

T

Q(t+1)

0 1

0 1

0 1

Q(t) Q’(t) Page: 19

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 Flip-Flop Stimulus Table  RS-type FF

 JK-type FF Q(t) Q(t+1) J K

0 0 1 1

0 1 0 1

  1 0

0 1  

0 0 1 1

0 1 0 1

0 0 1 1

0 1 0 1

0 1 0 

 0 1 0

 T-type FF

 D-type FF Q(t) Q(t+1)

Q(t) Q(t+1) S R

D

0 1 0 1

Q(t) Q(t+1)

0 0 1 1

0 1 0 1

T

0 1 1 0 Page: 20

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 D-type Flip-Flop  Output changes only on the clock edge

D

D C

D latch

Q

D

Q D latch _ C Q

Q _ Q

C

D

C

Q

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 Exchange of FF’s Each Other  Use of D-type FF to implement T-type FF

T CK

D

Q

CK

Q

Q Q

 Use of SR- or JK-type FF to implement D-type FF D

D

S

Q

Q

R

Q

Q

J

Q

Q

K

Q

Q

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DIGITAL DESIGN

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 Exchange of FF’s Each Other  Use of SR-type FF to implement T-type FF 1 3 2 T

CK 1 3

S CK

Q

R

Q

Q Q

2

 Use of JK-type FF to implement T-type FF

T CK

J CK

Q

K

Q

Q Q

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 Asynchronous Ripple Counter – Mod-6 (method 1)

1 CK

Q

Q0

1 1

Q

Q

Q1

1

J CK K

1

Q

reset

J CK K

reset

reset

1

J CK K

Q

Q2

1

2

3

4

5

0

1

2

CK Q0

Q

Q1 Q2

– Mod-6 (method 2)

1

2

3

4

5

0

1

2

CK Q0

1 CK

J

1

J CK

Q

1

K

Q

Q1

1

J CK

Q

1

K

Q preset

K

Q0

preset

1

preset

CK

Q

Q

Q2

Q1 Q2

Mod-M counter  Evaluate M-1.  FF’s to be 1 input to NAND gate, and NAND connects to FF’s to be 0. Page: 24

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 Down Ripple Counter

1 CK

J

Q0 1

Q

CK

J

Q

K

Q

Q2

CK

1

Q

K

reset

1

reset

K

Q1 1

Q

CK

reset

1

J

Q

CK Q0

0

1

0

1

0

1

0

1

Q1

0

1

1

0

0

1

1

0

Q2

0

1

1

1

1

0

0

0

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 Synchronous Sequential Circuit  Design of a mod-5 counter  State Diagram

1

0

2 4 3

 State Transition

NS

PS

q2 0 0 0 0 1

q1 0 0 1 1 0

q0 0 1 0 1 0

q2 0 0 0 1 0

q1 0 1 1 0 0

q0 1 0 1 0 0

FF’s Input J2K2 J1K1 J0K0

0 0 0 1 1

0 1 0 1 0

1 1 1 1 0

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 K-Map q2 q0 q1 00 01 11 10

J2 K2 0

1

0 0  1

0 1  

q2 q0 q1 00 01 11 10

J1 K1 0

1

0 0  0

1 1  

J2 = q1q0 K2 = 1

q2 q0 q1 00 01 11 10

J0 K0 0

1

1 1  0

1 1  

J1 = q 0 K1 = q0

J 0 = q 2’ K0 = 1

 Implementation

q1

q0 1

J0 CK K0

Q Q

J1 CK K1

q2

Q Q

1

J2 CK K2

Q Q

CK

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 Example II: x

A

1/0

z

001/1 0/0

B

1/0

0/0

C

0/0

1/1

NS, Z PS

X=0

X=1

A

B,0

A,0

B

C,0

A,0

C

C,0

A,1

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NS, Z

PS

X=0

X=1

y1y0

X=0

X=1

J1K1 J0K0

J 1K 1 J 0K 0

A = 00

01,0

00,0

0

1

0

0

B = 01

11,0

00,0

1

0

0

1

C = 11

11,0

00,1

0

0

1

1

y 1y 0 x 00

01

11

10

y 1y 0 x 00

01

11

10

0 0 1

0 

0 1 0

0 

1 0 0

1 

1 0 1

1 

J1 = x’y0

k1 = x

J0 = x’

k0 = x

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y1y0

00

01

11

0

0

0

0

10 

1

0

0

1



x

z = xy1

1

X

J CK K

Q Q

y0 2

3

1

J CK K

Q

y1 1 3

Z

2 Q

CK

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Design of Asynchronous Sequential Circuit  Example of flow tables  A circled entry indicates a stable condition, other non-circled entries denote unstable states.

Two states with two inputs and one output

Four states with one input Page: 31

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Gated–Latch Logic Diagram DG y 00

01

11

10

DG y 00

01

11

10

0

0

0

1

0

0

0

0

1

0

1

1

0

1

1

1

1

0

1

1

Y = DG + G’y

Q = Y = DG + G’y

D Y

Q

G y

Y: next state

y: present state Page: 32

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Gated–Latch Logic Diagram-SR Latch DG y 00

01

11

10

0

0

0

1

0

1

1

0

1

1

DG y 00

01

11

10

Y

y

Y

S R

0 0 1 1

0 1 0 1

0 1 0 

01

11

10

DG y 00

 0 1 0

0

0

0

1

0

0





0



1



0





1

0

1

0

0

S = DG

D

R = D’G

S

Q

G R Page: 33

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Total State  Combine the internal state with the input value together. Gated-latch total states

state a b c d e f

input

output

D

G

Q

0 1 0 1 1 0

1 1 0 0 0 0

0 1 0 0 1 1

Comments Q = D because G = 1 Q = D because G = 1 After state a or state d After state c After state b or state f After state e

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DIGITAL DESIGN

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Primitive Flow Table  Simultaneous transitions of two input variables, such as 0110 or 11  00, are not allowed. We can enter dash marks for this case.  All outputs associated with unstable states are marked with a dash to indicate don’t-care conditions.

DG 00

01

11

10

a

c, -

a, 0

b, -

-, -

b

-, -

a, -

b, 1

e, -

c

c, 0

a, -

-, -

d, -

d

c, -

-, -

b, -

d, 0

e

f, -

-, -

b, -

e, 1

f

f, 1

a,-

-, -

e, Page: 35

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Implication Table  Two states can be combined into one if they can be shown to be equivalent.  Equivalent: if for each possible input, they give exactly the same output and go to the same next states or to equivalent next states.  If the pair of states (c, d) are equivalent, then the pair of states (a, b) will also be equivalent.  If (a, b) imply (c, d) and (c, d) imply (a, b), then both pairs of states are equivalent. (a = b, c = d)

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Example I

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Example II

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Maximal Compatibles without Imply States  Merge Diagrams (The chosen set will cover all the states of the original table)

2 nodes

3 nodes

4 nodes

5 nodes

a

a

b

h

f

b g

e

c

d Maximal Compatible (a, b)(a, c, d)(b, e, f)

c d

f e

Maximal Compatible (a, b, e, f)(b, c, h)(c, d)(g) Page: 42

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Closed Covering Condition a b b, c  c



d b, c  e

d, e 

e



a, d 







b, c 

a

b

c

d

b

d

Implication Table

(a, b)(a, d) (b, c) (c, d, e)

c

Merge Diagram

Closure Table compatibles

(a, b)

(a, d)

(b, c)

(c, d, e)

Implied States (b, c)

(b, c)

(d, e)

(a, d) (b, c)

(a=d) if (b=c), (b=c) if (d=e), (c=d=e) if (a=d)&(b=c)

 Not closed covering condition: (a, b) (c, d, e), because (a, b) imply (b, c) but (b ,c) is not included in the chosen set of (a, b) (c, d, e).  Closed covering condition: A set of compatibles (a, d) (b, c) (c, d, e). Page: 43

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 Example III: Negative-edge-trigged T Flip Flop

state a b c d e f g h

input

output

T

C

Q

1 1 1 1 0 0 0 0

1 0 1 0 0 1 0 1

0 1 1 0 0 0 1 1

Note Initial output to be 0 After state a Initial output to be 1 After state c After state d or state f After state e or state a After state b or state h After state g or state c

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 Original Flow TC a

00

01

11

10

-, -

f, -

a, 0

b, -

b

g, -

-, -

c, -

b, 1

c

-, -

h, -

c, 1

d, -

d

e, -

-, -

a, -

d, 0

e

e, 0

f, -

-, -

d, -

f

e, -

f, 0

a, -

-, -

g

g, 1

h, -

-, -

b, -

h

g, -

h, 1

c, -

-, -

state a b c d e f g h

input

output

T

C

Q

1 1 1 1 0 0 0 0

1 0 1 0 0 1 0 1

0 1 1 0 0 0 1 1

Note Initial output to be 0 After state a Initial output to be 1 After state c After state d or state f After state e or state a After state b or state h After state g or state c

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a b

h g

c

(a, f)(b, g, h) (c, h) (d, e, f)

d

f e

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a = 00

b = 01

d = 10

c = 11

TC y1y2

00

01

11

10

a = 00 10 00 00

01 b = 01 01 01 11 01 c = 11 01 11 11 10 d = 10 10 10 00 10 Transition Table

TC y1y2

00

01

11

10

0 01 1 11 1 10 0

0 1 1 0

0 1 1 0

 1

00

 0

Output Page: 48

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TC y1y2

00

01

11

10

1 01 0 11 0

0 0

0 1

0 0

 

 0

 

00

10



TC y1y2

00

01

11

10

00

0

  0 0

 0 0 1

  0 0

 11 1 10 0 01

S1 = y2TC + y’2T’C’

R1 = y2T’C’ + y’2TC

TC y1y2

00

01

11

10

TC y1y2

00

0

0

0

1

00

 11  10 0

  0

  0

 0 0

10

01

S2 = y’1TC’

00

01

11

10

 01 0 11 0

 0 0

 0 0

0 0 1









R2 = y1TC’ Page: 49

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S1 = y2TC + y’2T’C’ R1 = y2T’C’ + y’2TC

Page: 50