... Sharad Prasad+, Ashok Kapoor+,. Thomas E. Kopley", Tom Dungan", Paul Marcoux". EECS Department, Massachusetts Institute of Technology, Cambridge, ...
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Proc. IEEE 1997 I t . Conference on Microelectronic Test Structures,Vol 10, March 1997
Digital Test Circuit Design and Optimization for AC Hot-Carrier Reliability Characterization and Model Calibration under Realistic High Frequency Stress Conditions Wenjie Jiang, Huy Le, Seokwon A. Kim, James E. Chung, Yu-Jen Wu', Peter Bendix', John Jensen+, Reenie Ardans+, Sharad Prasad+, Ashok Kapoor+, Thomas E. Kopley", Tom Dungan", Paul Marcoux" EECS Department, Massachusetts Institute of Technology, Cambridge, MA 02139 'Research and Development, LSI Logic Corporation, Milpitas, CA 95035 *ICBD Technology Development Center, Hewlett-Packard Company, Palo Alto, CA 94303
ABSTRACT This study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs will be presented and additional new test circuit designs will be demonstrated. The inherent design trade-offs that exist between realistic waveform generation and internal device accessibility will be analyzed and clarified. Recommendations for optimal test-circuit design for hotcarrier reliability characterization and model calibration will be proposed.
INTRODUCTION In order to make accurate assessments of hotcarrier lifetime in a circuit environment, hot-carrier reliability test circuits are necessary to generate the realistic AC stress waveforms which are required for circuit simulation and reliability tool calibration. Test circuits are also needed to provide insight about AC degradation mechanisms and to provide a realistic circuit response to hot-carrier damage. Earlier studies[ 1-61, which focused on AC stressing of single transistors, suffered from inherently unrealistic stress waveforms; some studies also suffer from mismatch between extemal signal sources and the devices under test, and from inductive noise coupling to the power supply terminals[7]. In addition, the different circuit sensitivities to hot-carrier damage could not be obtained from individual AC device measurements. Another option of performing hot-carrier reliability characterization using test circuits which have only been designed for performance evaluation O-7803-3243- 1
alone[S], is also inadequate since, without access to internal device nodes, it is then difficult to delineate between NMOS and PMOS device degradation, and to distinguish between the circuit's effect on creating damage from the circuit's sensitivity to that damage. To address these problems, this study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs will be presented and additional new test circuit designs will be demonstrated. The inherent design trade-offs that exist between realistic waveform generation and intemal device accessibility will be analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration will be proposed.
TEST CIRCUIT DESIGN For general hot-camer reliability characterization, test circuits designed as ring osciliators and inverter chains have advantages because of their relative ease of delay measurement and because of their ability to relate directly the impact of hot-carrier damage to circuit performance. In addition, ring oscillators and inverter chains can easily be designed to cover a wide range of design space by adjusting the transistor sizes, fanouts and the number of stages. Fig. 1 illustrates a general schematic for hotcarrier test circuits designed in the ring-oscillator configuration; these circuits allow internal node access for the devices of a representative stage within the oscillator. Similar test structures were designed for inverter chain circuits as well. The inputs of the inverter chain circuits were driven by an on-chip voltage-controlledoscillator (VCO). For both the ring oscillator and
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inverter chain circuits, no external signal sources were needed; only an external DC power supply was required,
Fig. 1 General circuit schematic of a ring oscillator AC test structure for hot-carrier reliability evaluation. The ring oscillator and inverter chain structures were designed such that the ratio of PMOS and NMOS transistors sizes is (W/L)p/ON&), = 2 in order to have relative equal rise and fall times. In digital CMOS circuits, the typical loading of one stage is about 1 to 5 fanindfanouts. Our test structures were designed to have fanidfanout values ranging from 1 to 15. When laying out the representative inverter stage (indicated as DUT in Fig.l), it is recommended that the W E L L and PWELL of this stage be separated from WELLS of the other stages, if a twin well process is available. This design allows the substrate currents of NMOS and PMOS transistors of the DUT to be measured accurately. The hot-carrier test structures can be laid out small enough to fit into a scribe line. Fig. 2 shows an example of the layout of a ring oscillator test structure.
Fig. 2
Microphotograph of test structure.
TEST CIRCUIT OPERATION For the ring oscillator test circuits (and for the inverter-chain circuits as well), the stress and measurement procedure can be divided into two distinct modes: Stress Mode: In the stress mode, all the DC probing switches (labeled as switches G and D in Fig.
1) are turned off and the circuit is isolated from the external probing pads. The design of these switches will be discussed in the next section. The desired stress supply voltage is then applied to pads VCC and VCCS, generating the internal AC stress voltage waveforms. Measurement Mode: In the measurement mode, the stress voltage waveforms are stopped, either by floating the power supply, VCC, or by disconnecting the ring oscillator via a pass gate. The probing switches are then turned on thereby allowing access to the internal device nodes. By properly biasing the relevant nodes, the degraded internal NMOS, PMOS and the inverter characteristics can be measured for the representative stage within the ring oscillator. The output buffers were designed with a separate power supply in order to reduce inductive noise. During stress, any degradation-induced change in the oscillation frequency is monitored at the buffered output pad (typically using a picoprobe in order to minimize loading). The stage ratio of the output buffer is 3 in our design. (the stage ratio is defined as the width of the next stage divided by the width of the current stage).
INTERNAL NODE SWITCH DESIGN An ideal switch for these hot-carrier reliability test circuits should have the following characteristics: First, it should minimally disturb the circuit during stress in order to maintain as realistic circuit operating conditions as possible. Second, it should be able to pass through a wide range of measurement voltages in order to allow full measurement of the device characteristics before and after each stress. Third, it should be able to measure accurately the voltage at the internal node of interest. Shown in Fig. 3 are four different design implementations (A-D) for the special probing structures to allow internal node access. Note, there is always a design trade off between realism of the AC stress waveforms and accessibility to the intemal devices. It is impossible to access the internal nodes of a circuit without introducing some disturbance to the circuit itself. The goal is to maximize the obtainable information while minimizing the impact on the circuit behavior. Design A : The most straightforward way to access the individual devices within a ring oscillator is to connect the internal nodes directly to probing pads as shown in Fig. 3a [9-111. Although convenient, this direct connection of the probing pads can add very large capacitance to the internal nodes. Fig. 4 shows
that the probing pads can change the voltage waveforms significantly. Thus, this particular test circuit design can only represent the case of extremely large loading; it cannot be used to represent most typical circuit operating conditions and is not suitable for most high frequency stressing. 0
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Fig. 3 Circuit designs of special probing structures for intemal node access. Design B: Using a pass transistor to isolate the probing pad (Fig. 3b) offers a good solution to this problem since it only adds a small capacitance to the circuit (an overlap capacitance and a junction capacitance) while allowing access to the internal nodes. Fig. 5 shows that the effect of the probing pass transistors, when turned off, on the ring oscillator waveforms is very small. Note, that both the TD1 and TD2 pass transistors are necessary, since, during the measurement mode, there is a current flowing through TD2 and the devices under test (DUT) when a voltage is applied to Vddive; because of the ensuing voltage drop across TD2,
TD1 is introduced to measure the real voltage chat exists at node D.
Ideally, on the gate side, there should be no current flowing through TG2 during the measurement mode However, we found that there is an unexpected leakage current going through TG2 and the NMOS device Np (see Fig. 1) of the previous inverter stage when a voltage is applied to Vgdive.This is because
Fig. 5 Comparison of the input and output waveforms of a CMOS inverter in a regular ring oscillator and in a ring oscillator with probing structure as in Fig. 3b (HSPICE simulation results). the input node, INp, of the previous inverter stage must be floating during the measurement mode. This floating node is very unstable and sensitive to capacitive coupling. As the voltage Vgdrive is increased, the transistor N, is gradually turned on due to the coupling of overlap capacitance between drain and gate. Fig. 6 shows this leakage current rises as the voltage Vgdrive increases. The design in Fig. 3b, while allowing a real-
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istic stress waveform, can potentially induce error due to leakage-current-induced inaccuracies in measuring the device node voltage VG (Fig. 7). Note, that this is an inherent problem for this type of test circuit design and other previous designs which are based on the same measurement principle [ 12-161.
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Fig. 6 Leakage current Igdrive as a function of voltage applied at the drain of transmission gate TG2. IGND is the current measured at the source of the NMOS device N, in Fig. 1 .
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on the particular technology), the leakage current can actually limit the maximum applicable voltage that can be applied to the node VG. It is worth emphasizing that this leakage current is not present during the ring oscillator stress mode since all the pass transistors are switched off and no internal nodes are floating. The design in Fig. 3c, although it may have limitation on the range of characterization voltages, does generate realistic stress waveforms and allows more accurate internal device measurements. Design D: Shown in Fig. 3d is another new design with an extra switch gate, TS, introduced to completely cut-off the leakage path that exists during the measurement mode. With no leakage current, the node voltage VG can be accurately measured using just TG1 (no ohmic drop); no limitation also exists on the range of applicable VG values. However, these benefits come at the cost of adding a small on-resistance during the stress mode. In the stress mode, the voltage applied on the gate of the switch transistor TS should be at least one body effected threshold higher than the stress voltage applied on VCC. This is to ensure that the voltage at node G won’t be clamped because of the threshold voltage drop. This is also to ensure that the on-resistance of device TS is kept small. Fig. 8 shows the device TS has minimal effect on the ring oscillator waveform. The design in Fig. 3d, although it produces a small acceptable impact on the stress waveform, allows the most accurate and robust measurement of the internal device nodes.
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Fig. 7 The deviation of the voltage VG (Vgsense) from the applied voltage Vgdrive due to the leakage current.
Design C: In order to solve this leakage current problem, the real voltage that exists at node G, must be directly measured by introducing a new additional pass transistor, TGl, as shown in Fig. 3c; this greatly improves the accuracy of the I-V characterization. However, even with TG1, the leakage current still exists. For sufficiently high leakage current, the voltage VG will appreciably differ from Vgdrive due to the ohmic drop across TG2. If sufficiently high (depending
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Fig. 8 Comparison between the input and output waveforms of the design in Fig. 3c and Fig. 3d (HSPICE simulation results).
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EXPERIMENTAL RESULTS
The LDD devices and test circuits used for this study were fabricated using either a 0.4um (technology A) or a 0.6um (technology B) NWELL CMOS process., Test circuits in both the ring oscillator and inverter-chain configurations were fabricated with an array of different fanouts, number of stages, and structures for internal device node access. For all test circuits, the NMOS and PMOS device widths were 5um and lOum, respectively. Ring oscillator test structures were stressed with periodic interruptions in order to monitor the degradation of the device and inverter characteristics. Take the test structure Fig. 3d as an example. During stressing, the switch gate TS was overdriven by setting the gate voltage of TS to (VStress+ V,h(B)), where V,,,,, is the stress voltage and v,h(B) is the body affected threshold voltage. This was to ensure that waveforms at the input of DUT have full voltage swing. The VCC and VCCS (Fig. 1) of the ring oscillators were connected to Vstress.The power supply of the output buffer was connected to the ring oscillator operational or lower voltage in order to avoid the degradation of the buffer due to stressing. During measurement, the switch gate TS was turned off so that the DUT was isolated from the other stages in the ring oscillator. The probing switches TG1, TD1 and TD2 were then turned on. The Vgdrive becomes the gate voltage of the NMOS (or PMOS) device under test, Vdsence becomes the drain voltage and Iddrive becomes the corresponding drain current of the NMOS (or PMOS). Then Vgdrive,Vdsence and Iddrive can be used to determine the I-V characteristics of the particular DUT. Vgdriveand Vdsencecan also be used to determine the inverter transfer characteristics. Fig. 9 shows typical fresh and degraded internal NMOS and PMOS DC I-V characteristics taken from one stage of a 23-stage, fanout 1, oscillator test circuit after having undergone high-frequency (100 to 350 MHZ) AC stress for 20 hours. The stress voltage is 4.5V. Fig. 10 shows the associated degradation in the inverter transfer characteristics. The complex nature of the devicekircuit interaction in hot-carrier degradation necessitates distinguishing between the different NMOS and PMOS characteristics. For example, Figs. 11 and 12 compare the internal device and circuit performance degradation characteristics for ring oscillator test circuits from technologies A and B. From Fig. 11, it is clear that for technology A, the NMOS device * degradation dominates
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VD, (VI - v,, (V) Fig. 9 AC device degradation before and after 20 hours of stressing in a CMOS inverter ring oscillator (23 stages and fanout 1). The stressing voltage is VCC = 4.5 V. The devices are measured at IVGl = 1, 1.5, 2, 2.5,3 V. The current axies are normalized.
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Fig. 10 DC transfer curve of a CMOS static inverter before and after stressing in a ring oscillator (23 stages and fanout 1) for 20 hours at 4.5 V. that circuit's performance degradation, whereas, for technology B, first the PMOS and then the NMOS device degradation is responsible for that circuit's performance degradation (as observed in the resulting initial speed up and then slow down in the oscillation frequency). Without internal node access, allowing direct device measurements, it would be impossible to determine the root cause for the observed degradation in circuit performance.
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waveforms and can allow more robust and accurate internal device measurements. The degradation characteristics of devices stressed under realistic AC conditions and the impact of hot-carrier damage on circuit performance can be directly obtained.
ACKNOWLEDGMENTS
//measurement condition: Iinrregion , (Vg = 3.0 V, Vd = 0.1V) saturation region (V = 3.0 V, Vd = 3.0 v)
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degradation in a ring oscillator of 13 stages and fanout 2. Freq stands for frequency degradation. Measurement condition; I VG I = 2.5 V, I VD I = 0.2 V in linear region; I VG I = 2.5 V, I V, I = 2.5 V in saturation region. SUMMARY
We have critically analyzed test circuits for AC hot-carrier reliability characterization and have proposed two new AC test structures (Fig. 3c and 3d) which can provide realistic high frequency voltage
This research was supported by DARPA contract DABT-63-95-C-0088, ONR grant N00014-95- 1- 1297 and ARO grant DAAH04-95-1-0459. We would also like to thank the people in LSI Logic and Hewlett Packard for fabricating the circuits and devices used in this study.
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Proceedings of International Conference on Microelectronic Test Structures, vol. 4, No. 1, pp. 241, 1991. J. Winnerl, F. Neppl, A. Lill, G. Roska, and W. Zatsch, "Ring Oscillator Structure for Realistic Dynamic Stress of MOSFETS' and Ineterconnects", in IEEE Proceedings on Microelectronic Test Structures, vol. 1, No. 1, pp. 56, 1988. N.Matsuzaki, A. Watanabe, M. Minami, and T. Nagano, "Increased Hot-Carrier Degradation of NMOSFETs under Very Fast Transient Proceedings of IEEE Stressing", in lntemational Reliability Physics Symposium, pp. 129, 1991. H. Wang, H. De, and R. Lahri, "Improved HotElectron Reliability through Circuit Analysis and Design", in Proceedings of IEEE International Reliability Physics Symposium, pp. 107, 1991. W. Weber, M. Brox, T. Kunemund, H. M. Muhlhoff, and D. Schmitt-Landsiedel, "Dynamic Degradation in MOSFET's --Part 11: Application in the Circuit Environment", IEEE Transactions Electron Devices, vol. 38, No. 8, pp. 1859,1991. E. S. Snyder, D. V. Campbell, S. E. Swanson and D. G. Pierce, "Novel Self-stressing Test Structures for Realistic High-Frequency Reliability Characterization", in Proceedings of IEEE International Reliability Physics Symposium, pp. 57, 1993. K. Quader, "Hot-Carrier Reliability of Integrated Circuits", Ph.D thesis, University of California at Berkeley, 1993. V. Chan, T. Kopley, P. Marcoux, and J. E. Chung, "High-Frequency AC Hot-Carrier Degradation in CMOS Circuits", in Technical Digest of International Electron Devices Meeting", pp. 299, 1994. S . C. Hu and M. P. Brassington, "A New Test Structure for Direct Measurement of HotCarrier Stress Effects on CMOS Circuit Performance", IEEE Transacfions Electron Devices, vol. 38, No. 8, pp. 1958, 1991.
