2014 2014 13th International International Conference Conference onon Information Information Technology Technology
Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion using FPGA Sudip Ghosh, Nachiketa Das,Subhajit Das,Santi P. Maity and Hafizur Rahaman School of VLSI Technology Indian Institute of Engineering Science and Technology(IIEST), Shibpur Howrah,West Bengal, India e-mail:
[email protected] Abstract— The additional operation of retrieval of the cover image at the decoder is necessary for lossless watermarking system. Taking into account this major issue, efficient implementation of reversible image watermarking needs to be addressed. This can be solved using hardware implementation. This paper focus on the digital design with pipelined architecture of reversible watermarking algorithm based on Difference Expansion(DE) which is linear and whose running time is O(n). There are three different digital architectures proposed in this paper namely dataflow architecture, optimized dataflow architecture using pipelining and the modified architecture using pipelining. All the three design is implemented on Xilinx based FPGA. To the best of our knowledge this is the first digital design and pipelined architecture proposed in the literature for reversible watermarking using difference expansion.
loss of the compressed data may crash the whole embedded data. Therefore, schemes belonging to this type lack robustness and are usually designed for data hiding or image authentication. This paper is organized as following: Section I is the introduction, section II mentions the related works, section III focus on the proposed pipelined architecture for reversible watermarking based on difference expansion, section IV highlights the analysis and experimental results, section V concludes the paper followed by the references. II.
Literature on RW are quite rich [1, 2], containing a large number of different concepts, namely difference expansion (DE), least significant bits (LSB) modification, data compression, histogram modification, reversible contrast mapping (RCM) [5][12], human visual system (HVS) [13] based approach, prediction error adjustment etc. along with their various modified forms. Among them, DE [17] and RCM is quite popular one [3, 4, 5] due to its low cost implementation and high embedding capacity.RCM is a simple integer transform that applied on pairs of pixels and their LSBs are used for data embedding. It is perfectly invertible even if the LSBs of the transformed pixels are lost during embedding process. Several watermarking schemes are developed both in software and hardware platform using spatial as well as transform domain approaches. Spatial domain approaches are better suited for hardware realization due to simplicity and low computational burden. A hardware based implementation can be designed on a field programmable gate array (FPGA) board, trimedia processor board or application specific integrated circuit (ASIC). Each one of them has relative merits and demerits. Garimella et al. [6] implemented a fragile invisible watermarking algorithm based on spatial domain approach using standard ASIC design flow with 0.13 m CMOS 2, technology, and has a die size of 3453 × 3453 consumes 37.6 W power. Later on Kougianos et al. [7] made a survey on necessity and different goals of hardware realization of digital watermarking. They suggest that the need of low power, low cost, high performance real time operation, and high security with watermarking done at the data acquisition
Keywords- Digital Design, Pipelined Architecture, Reversible Watermarking, Difference Expansion
I.
INTRODUCTION
Digital watermarking is defined [13] as the imperceptibly altering a work in order to embed information about that work. In recent years, copyright protection of digital content becomes a serious problem due to rapid development in technology. Watermarking is one of the alternatives to copyright protection problem. The general framework of digital watermarking consists of three parts: Encoder, Decoder and a comparator as discussed in[14]. But the main drawback in digital watermarking is that during decoding it needs the original media to get back the watermark. Thus after decoding we would get the watermark but there is no information regarding the original media. This problem is solved when reversible watermarking came into picture. The first idea of reversible image watermarking can be traced back to U.S. Patent from Barton in 1997 and U.S. Patent from Honsinger in 1999 [18],[19].Reversible watermarking(RW) [1] [2] [3] [4] is a novel category of watermarking scheme. It not only can strengthen the ownership of the original media but also can completely recover the original media from the watermarked media. Among the reversible watermarking schemes, Difference Expansion has been favored over the previous data compression schemes. As in data compression, due to data compression techniques it cannot resist the distortions , any 978-1-4799-8084-0/14 $31.00 © 2014 IEEE DOI 10.1109/ICIT.2014.26
RELATED WORKS
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stage, that drives the VLSI implementation of the watermarking schemes. Mohanty et al. [8] developed low-power, high-performance, real-time, reliable and secure watermarking systems. They prototype the watermarking chips in two ways: (i) by using a Xilinx FPGA and (ii) by building a custom integrated circuit. Maity et al. [9] proposed an algorithm that serves the purpose of covert image-in-image communication, and develops its hardware representation using FPGA platform. Mohanty et al. [10] also proposed another VLSI architecture that can insert invisible and visible watermarks in images in the DCT domain using ASIC design flow with 0.25 m technology. Maity et al. [11] proposed fast walsh transform (FWT) based spread spectrum (SS) image watermarking scheme that serves the dual purpose of authentication in data transmission as well as quality of service assessment for digital media. Although, VLSI architecture of several spatial and transform domain conventional watermarking methods are reported, but RW in hardware platform using FPGA is shallow. Hardware implementation using FPGA offers: easiest prototype designing, low investment cost, simpler design cycle, field programmability/ reconfigurability and desktop testing with moderate processing speed. The contributions here are three different proposed architectures and their detailed description of digital design [15][16]and implementation. III.
(3) and are the embedded pixel values. where Likewise, the second module is decoding which also consists of three steps. Here, the first step is to compute the of the embedded pixel values. integer average Mathematically, it is similar to that encoder ,given in (4) (4) In the second step difference value is calculated and the embedded bit is recovered back. Mathematically, it is given in (5)and (6). (5) (6) where is the bit we recovered back and is obtained by flooring (7). (7) The final step is the recovery of the original pixels and ,which is done in the same way in which it has been embedded. The dataflow of the embedder is shown in Fig.1,where the simple operations like additions and subtractions are done by using 8-bit adder and subtractor using two’s complement logic respectively. The floor function is achieved by 1-bit Right shifting.
PROPOSED ARCHITECTURE FOR REVERSIBLE WATERMARKING
The proposed architecture is optimized for a 8-bit gray scale. The source to the encoder which is basically a device providing image pixels as input , can be a storage device like a RAM. As discussed in [17], a specific transformation technique is performed on the image involving a pair of pixels. The technique has two modules-Encoding and Decoding, each of which has three stages.In Encoding module , first integer average is generated using the following equation (1). (1)
Fig.1(Dataflow architecture of Embedder) And the dataflow for the decoder is shown in Fig.2.The processes are similar to embedding but the only difference is (6) which is in the extraction of the embedded bit implemented using a 9-bit subtactor using two’s complement logic and 1-bit left shifting of .
are the original pixel values and is the integer where average. In the second step, the difference value of the two pixel values is calculated and is converted into binary. The bit to be embedded is appended into the binary representation of difference value after LSB, thus extending the difference value to a 9bit value. Mathematically it is obtained using the following equation in (2) ,where is the bit to be embedded. (2) The final step of embedder is embedding of pixel values is done using the following mathematical equation (3).
Fig.2(Dataflow architecture of Decoder)
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Enc
T1 Read from RAM Read b from RAM
T2
T3
T4
T5
T6
T7
T8
Dec
1bit RS = x-y =h
T9
T10
T1 1
T12
T13
T14
T15
h+b
1bit RS =
T16
1bit RS
1bit LS
h’= 2h+b
1bit RS = =
1bit RS =
1bit RS=
1bit LS =2
= +
1bit RS=
=
Fig.3(Timing cycles for Embedding and Decoding) Fig.3 shows the timing cycles of both the Encoding and respectively. The last step is the generation of which is Decoding modules. The integer average is generated in obtained through T14 and T15.Here, is needed as given first three cycles i.e within T3.The second step i.e (9), has been already obtained in T11 but due to pipelining it generation of difference value ( ) of the pixels and and is generated in T15. The hardware optimized architecture of Embedding and the expanded difference value ( ) is done in T3,T4 and T5 decoding module is given in Fig.4 and Fig.5 respectively. cycles instead of T2,T3 and T4,as in T2 both addition and Fig.4 gives the hardware optimized form of embedder. subtraction cannot be done. Since is generated in T5 thus Using pipelining we have used some of the hardware and is final step i.e. embedding of pixel values resources repeatedly since the timing cycles in which they performed through T6, T7 and T8 cycles. The steps in are operating are different. In this embedding module, both like addition, 1-bit right shifting and again addition as given the adders ADD1 and ADD2 have been used twice instead in (3) is done in T6 ,T7 and T8 respectively. And for the of using two more hardware resources.ADD1 is used for required steps i.e. and as given in (3) is done in two timing cycles T2 and T5.In T2, it has been used for T6 and T7 cycle respectively. The second module is the generation of and likewise in timecycle T5,it (ADD1) has decoding part which will start from T9 cycle onwards as been used for generating . and are generated in T8 and T7 respectively.At first the is obtained in T10 through an new integer average in T9 cycle. After this, the difference addition of and value of the embedded pixels is done in T10 as T9 is already engaged with the addition as described earlier. Now is using(7) in T11. This is then 1-bit left obtained from shifted and subtracted from to get (6).After recovering the embedded bit,it is used to recover the original pixels and using (8) and (9) respectively. (8) Fig.4(Optimized pipelining)
(9) The timing cycle for obtaining is done through T14 T15 and T16 .As is generated in T13 ,thus the next operations ), 1-bit right shifting for generation of like addition( and addition ( ) are carried out in T14,T15 and T16
architecture
for
embedder
using
Similarly, ADD2 is used for two timing cycles T6 and and T8.In T6 cycle, it has been used for generating
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lastly in T8 cycle for generating the embedded pixel value .The remaining hardware sources are same as in dataflow. Fig.5 shows the hardware optimized form of decoder. Here, the decoder uses one adder(ADD2) twice because the timing cycles in which the two operations are done is different i.e in timing cycles T14 and T16.In T14 addition of h and b is done and in T16, the final result i.e recovery of the original pixel value x is done. Fig.6 and Fig.7 shows the modified architectures of the Embedder and Decoder respectively. In the above mentioned architectures, for division and multiplication 1bit right shift registers and 1-bit left shift registers have been used which contain 9 D-Flip-flops to carry out the desired division and multiplication respectively. In this modified architecture it has been proposed that for division the 9 D Flip-flops can be replaced by a single D flip-flop if the complemented output is connected to the input and the result to be divided is applied to the clock, shown in fig.6. Similarly, the 9 D Flip-flops for multiplication can also be replaced by a single D Flip-flop, an inverter and an XNOR gate. Here the output is connected to the inverter and the inverted output is divided into two parts , one part is connected to the input and the second part is XNORed with the result to be multiplied .The result from this operation is applied as clock and again going through D-Flip flop and inverter, the required output is obtained from the inverter. The remaining architecture is same as optimized version. It is assumed that the flip-flop has zero initial value. This is shown in Fig.6 and Fig.7 for Embedder and Decoder respectively.
Fig.5(Optimized pipelining)
architecture
for
Decoder
Fig.6(Modified pipelining)
architecture
Fig.7(Modified pipelining)
architecture
IV.
A[1:n] array of integers B[1:n] array of integers Where 0
Output: for i ← 1 to n do key[1]←A[i] for j ← 1 to n do key[2]←B[j] sum←key[1]+key[2] l←sum÷2 difference←key[1]-key[2] key[3]←2*difference newdifference←key[3]+b key[4]←newdifference+b key[5]←key[4]÷ 2 x ←l+key[5] key[6]←newdifference÷2 y ←l-key[6] return x return y
using
Pseudocode for the Decoder: Input: C[1:n] array of integers D[1:n] array of integers Where 0≤n≤255 Output for i←1 to n do key[1]←C[i]
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for
Embedder
using
decoder
using
ANALYSIS AND EXPERIMENTAL RESULTS
Time Complexity: Pseudo-code for Embedder Input:
for
REFERENCES
for j←1 to n do key[2]←D[j] sum←key[1]+key[2] l ←sum÷2 difference ←key[1]-key[2] difference←difference ÷2 b←difference -2*difference key[3]←difference+b key[4]←key[3]÷2 key[5] ←difference÷2 x←l +key[4] y←l -key[5] return x return y
[1] Roberto Caldelli, Francesco Filippini, and Rudy Becarelli,“Reversible watermarking techniques: An overview and a classification,” EURASIP Journal on Information Security, vol. 2010, Article ID 13454. [2] Jen-Bang Feng, Iuon-Chang Lin, Chwei-Shyong Tsai, and Yen-Ping Chu, “Reversible watermarking: Current states and key issues,” Int. Journal of Network Security, vol. 2, pp. 161–171, May 2006. [3] Dinu Coltuc, A. Tremeau, E. J. Delp, and P. W. Wong, “Simple reversible watermarking scheme,” in SPIE: Security, Steganography, Watermarking Multimedia Contents VII, 2005, vol. 5681, pp. 561–568.
This is the required pseudo-code for embedder and decoder. By inspecting the pseudo-code, the number of primitive operations executed by an algorithm can be counted. By analyzing the pseudo-code, the number of primitive operations executed by an algorithm can be counted. Here for both the modules only “n” iterations are necessary to carry on the process of embedding and decoding. Hence, the algorithm is linear and running time is O(n).
[4] Dinu Coltuc, J. M. Chassery, E. J. Delp, and P. W.Wong, “Simple reversible watermarking scheme:further results,” in SPIE: Security, Steganography, Watermarking Multimedia Contents VIII, 2006, vol. 6072, pp. 739–746. [5] Dinu Coltuc and J. M. Chassery, “Very fast watermarking by reversible contrast mapping,” IEEE Signal Processing Letters, vol. 14, pp. 255–258, April 2007.
TABLE I: HARDWARE RESOURCE UTILIZATION Dataflow Optimized Modified Architect Architecture. Architecture ure. (using (using Pipelining) pipelining) Adder 133 76 76 Subtractor 140 140 140 D-Flipflop 405 405 45 XOR NOT
NA NA
NA NA
[6] A. Garimella, M. V. V. Satyanarayan, R. S. Kumar, P. S. Murugesh, and U. C. Niranjan, “Vlsi implementation of online digital watermarking techniques with difference encoding for the 8-bit gray scale images,” in Int. Conf. VLSI Design, 2003, pp. 792–796.
10 2
[7] E. Kougianos, S. P. Mohanty, and R. N. Mahapatra, “Hardware assisted watermarking for multimedia,” Special issue on Circuits and Systems for Real Time Security and Copyright Protection of Multimedia Int. Journal of Comp. Elec. Engg., vol. 35, pp. 339–358, 2009. [8] S. P. Mohanty, E Kougianos, and N. Ranganathan, “Vlsi architecture and chip for combined invisible robust and fragile watermarking,” IET Computers and Digital Techniques, vol. 1, pp. 600–611, Sept 2007.
Table I shows the number of hardware resource used in the proposed architectures.
500 400
[9] S. P. Maity and M. K. Kundu, “Distortion free imagein-image communication with implementation in fpga,” Int. Journal of Elec. and Comm. Engg., 2012,In Press.
Dataflow Architecture
300
Optimized Pipelined Architecture Modified Pipelined Architecture
200 100 0
Adder
Subtractor D-FlipFlop
XOR
[10] S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, “A dual voltage-frequency vlsi chip for image watermarking in dct domain,” IEEE Tran. on Ckt. and Sys.-II: Express Briefs, vol. 53, pp. 394–398, May 2006.
NOT
Fig.8 Resource Utilization chart for proposed architectures V.
CONCLUSION
[11] S. P. Maity, M. K. Kundu, and S. Maity, “Dual purpose fwt domain spread spectrum image watermarking in real time,” Comp. and Elec. Engg, Special issue on Ckts. and Systems for Real-Time Security and Copyright
To the best of our knowledge this is the first digital design and pipelined architecture proposed in the literature for reversible watermarking using difference expansion.
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[12] S.P.Maity,Claude delpha,” A Modified RCM for Reversible Watermarking with FPGA implementation,”IEEE Tran. On EUVIP,2013. [13] C. S. Tsai and C. C. Chang, “A repeating color watermarking scheme based on human visual model,” Eurasip Journal on Applied Signal Processing, vol. 13, pp. 1965–1972, 2004.
[17] J. Tian, “Reversible data embedding using a difference expansion,” IEEE Transactions on Circuits Systems and Video Technology, vol. 13, no. 8, pp. 890–896, Aug. 2003.
[18] J. M. Barton, Method and apparatus for embedding authentication information within digital data, US Patent: 5646997, 1997
[14] S.P.Mohanty,”Digital Watermarking: A Tutorial Review,”,1999. [15] “Digital Circuits and Design”,Third Edition, by S.Salivahanan, S.Arivazhagan,Vikas Publishing House Pvt. Ltd.
[19]C. W. Honsinger, P. Jones, M. Rabbani et al., Lossless recovery of an original image containing embedded data, US Patent: 6278791, 2001
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