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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 2, MAY 2013

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Digital Implementation of Selective Harmonic Elimination Techniques in Modular Current Source Rectifiers Johan I. Guzman, Member, IEEE, Pedro E. Mel´ın, Student Member, IEEE, José R. Espinoza, Member, IEEE, Luis A. Morán, Fellow, IEEE, Carlos R. Baier, Member, IEEE, Javier A. Muñoz, Member, IEEE, and Gonzalo A. Guiñez, Member, IEEE

Abstract—Modular current source converters (MCSCs) have been proposed as an alternative method for increasing the power range of medium voltage PWM AC drives. MCSCs are built by stacking parallel current source converters. Two advantages that make MCSCs attractive are: (a) extended current/voltage ratings beyond the device ratings and (b) simplicity in balancing the DC link current in each module. This can be accomplished using two optimized modulating patterns that have been proposed for such topologies: (a) multilevel selective harmonic elimination (MSHE) and (b) displaced selective harmonic elimination (DSHE). Both techniques are based on SHE patterns but there are slight differences in their digital implementation due to the way they generate the harmonic cancellation. Furthermore, when these techniques are used in the rectifier stage, it is reported that MSHE and DSHE do not eliminate all the unwanted harmonics due to practical issues such as changes in the modulating indexes to control the DC link currents. This work compares the operation of DSHE and MSHE when used in rectifiers of an MCSC in terms of execution time, robustness to poor sampling frequency, and quality of harmonic profiles on AC input currents under different operating conditions. Experimental results are presented to validate the theoretical considerations.

Normalized input rectifier current per phase a and th CSC. th harmonic modulating index for the th CSC. Displacement factor for the th, CSC. Relative displacement factor for DSHE. Displacement angle for the th, CSC. Group Synchronization reference, CSC. Synchronization references for the th, CSC. Fundamental index reference for the th, CSC. Equivalent VSC states signals for the th, CSC. Null state occurrence signal for the th, CSC. Null state distributing signals for the th, CSC.

Index Terms—AC drives, digital control, PWM, selective harmonic elimination.

Gating signals for the th, CSC.

NOMENCLATURE

I. INTRODUCTION

Vector of switching angles for the th CSC. th element of the vector of switching angles. Modulation index for the th CSC. AC inputs currents. AC inputs currents for the th CSC. Manuscript received December 01, 2011; revised March 21, 2012, May 11, 2012; accepted July 09, 2012. Date of publication July 25, 2012; date of current version January 09, 2013. This work was supported by the Chilean Government under Project FONDECYT 111-0794 and Project FONDECYT 11110491. Paper no. TII-11-959. J. I. Guzman, C. R. Baier, and J. A. Muñoz are with the Department of Industrial Technologies, University of Talca, Talca 747-C, Chile (e-mail: [email protected]; [email protected]; [email protected]). P. E. Mel´ın, J. R. Espinoza, and L. A. Morán are with the Electrical Engineering Department, Concepción University, Barrio Universitario, Concepción, 4070409, Chile (e-mail: [email protected]; [email protected]; [email protected]). G. A. Guiñez is with División el Teniente, CODELCO, Chile (e-mail: [email protected]). Digital Object Identifier 10.1109/TII.2012.2210232

T

HE use of AC drives based on current source converters presents advantages such as simplicity and robustness in applications like large AC drives for low dynamics [1]–[7]. On the other hand using digital based platforms improves the performance of PWM based AC drives [8]. Recent publications have shown that AC drives built with modular structures extend the equipment voltage and current ratings beyond the limits of semiconductors [9]–[16]. In particular, AC drives with DC link based modules connected in parallel permit us to extend voltage and current using simple control schemes [17]. These structures are called modular current source converters (MCSC). They allow the use of multilevel modulating techniques reducing both compared the input current distortion and semiconductors to an equivalent monolithic AC drive. These features help to comply with the IEEE-519 recommendations on harmonic distortion [10]. Selective harmonic elimination (SHE) is the most widelyused modulating technique in medium voltage PWM current source based topologies as well as often used in large power voltage source topologies [18]–[26]. The literature shows two

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Fig. 1. AC drive based on two modular current source converters

.

types of SHE appropriate for MCSC: (a) multilevel selective harmonic elimination (MSHE) [27] and (b) displaced selective harmonic elimination (DSHE) [28]. Both share the same basic approach, i.e., solving a set of nonlinear equations to generate gating patterns. In fact, the implementation of MSHE and DSHE on digital systems follows similar rules. Thus, to compare the digital implementation of both MSHE and DSHE it is necessary to evaluate the performance in terms of (a) processing time and (b) deviation of harmonic elimination from ideal gating patterns. While MSHE and DSHE generally offer near-ideal performance when used in inverters, they show reduced performance when they are used in rectifiers. This is due to the inherent change of the modulating indexes necessary to equalize the DC link currents among the modules. This issue will cause the appearance of unintended harmonics, generating a risk of unwanted oscillations on the supply input currents due to the mandatory presence of the second-order input filter (Fig. 1). In this work, a generalized MCSC topology is described and the common characteristics of SHE, MSHE, and DSHE are presented to forward its digital implementation. Specifically, the MSHE and DSHE algorithms are implemented and compared with the SHE one in terms of execution time, robustness to poor sampling frequency, and quality of harmonic profiles on supply currents under different operating conditions. II. CURRENT SOURCE BASED MODULAR TOPOLOGIES Some authors propose using a monolithic rectifier feeding parallel connected inverters when parallel structures are used in AC drives. In this case, modified vector modulating techniques are used to balance the DC link currents [9]. By contrast, in the MCSC approach controlled DC link current structures are connected in parallel, Fig. 1. In an MCSC built with modules, every module is composed of a rectifier, an integrated DC link inductor, and an inverter. Each rectifier controls both the

DC link current magnitude and the supply displacement power factor whereas the inverter shapes the output line currents to accord with external requirements for amplitude, frequency and phase. The control schema proposed in [17] shows individual controllers for each DC link current. It assures a homogeneous current distribution among the modules while synchronization is performed by a robust digital PLL. Additionally, an auxiliary algorithm provides a displacement reference for the rectifiers gating patterns in order to operate with a unitary displacement power factor (UDPF). The whole system resembles a large equivalent AC drive for the AC mains and the output load. An example of an MCSC built with 2 modules is shown in Fig. 1. III. SHE BASED MODULATING TECHNIQUES MODULAR TOPOLOGIES

FOR

The use of optimized firing patterns for SHE presents several advantages over other modulating techniques. Conventional SHE is simple and several authors have presented different approaches for implementing the algorithms in digital systems. The main drawback to SHE is the high amplitude of the first group of unwanted harmonics. This drawback can be minimized using MSHE, which eliminates additional unwanted harmonics without increasing the switching frequency; however, MSHE requires identical modulating indexes and DC link currents among the modules for proper operation. Fulfilling this condition is straightforward in the inverters. However, it is more complicated for the rectifier converters since they continuously change their modulating indexes in order to comply with the control requirements. An interesting option for generating a multilevel modulated current for the rectifiers in a MCSC is displacing the conventional SHE patterns among the modules instead of using MSHE. The displacement is calculated to minimize a specific

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dominant harmonic on the total input current. This technique is called Displaced Selective Harmonic Elimination (DSHE). In addition to the dominant harmonic elimination, (a) all other harmonics are reduced or at least left the same and (b) in the case of strong asymmetric operation among the modules, the DSHE still provides better-or at least equal-current waveforms than standard SHE. The normalized line current pattern for phase of the converter is defined as the relation between the AC rectifier current and the DC link current , thus (1)

Fig. 2. Switching angles as a function of the modulation index for conventional SHE.

The amplitude for the th harmonic component of the normalized line current is considered as the -order modulation index. Given the commutation angle vector defined as

harmonics. The main drawback to this approach is the high amplitude of the first set of harmonics as reported in [26].

(2)

B. Modular Selective Harmonic Elimination (MSHE) in MCSC

are the independent where angles in a pattern with quarter wave symmetry, an arbitrary harmonic in can be defined as , which is a function of and the harmonic order

(3) A. Conventional SHE in MCSC Using SHE in MCSC results in a simple and robust modulating technique. The modulators generate the same angles to for each converter. The resulting input currents are similar to the ones produced by an equivalent rectifier. For instance, let’s find the angles for and (two modules) in order to eliminate the 5th and 7th harmonics and control the fundamental. Defining as the desired fundamental modulation index for each rectifier, the vectors and are obtained by solving (4) such that the fundamental is equal to and the harmonics 5 and 7 are cancelled out. Thus, the equations to be solved for each rectifier are (4) where equation systems are identical

, 2. Note that the i.e., (5)

In other words, the system has only three degrees , it is found that of freedom. Particularly, for rad. The complete trajectories for the individual angles as a function of the modulation index are depicted in Fig. 2. Note that adding up gating patterns calculated for different modulating indexes does not change the value of the unwanted

The MSHE technique uses a different approach to generate gating patterns. Instead of eliminating the harmonics on each converter, the harmonics are eliminated from the sum of the gating patterns. Thus, for each module there exist degrees of freedom associated with each independent commutation angle. If angles are used to control the fundamental modulating indexes of each converter, then it is possible to eliminate harmonics from the sum of the gating patterns [27]. Then, to solve the system, it is necessary to find the vectors to that solve the equation set given by equalities. For instance, for the 5th, 7th, 11th, and 13th harmonics add up to zero in the total AC current , changing the first unwanted harmonic from the 11th to the 17th as compared with conventional SHE. Like conventional SHE, the function depends upon the commutation angle vectors and the order of the harmonic as stated in (2)–(3). In this case, the vectors and are obtained by solving (3) such that the fundamental components are equal to the desired modulation index for both rectifiers and the 5th, 7th, 11th, and 13th harmonics add up to zero. Hence, the equations to be solved are

(6)

where and , resulting in six degrees of freedom. For and rad. The angles and for other modulation indexes are plotted in Fig. 3. The main drawback to MSHE running on rectifiers is the degradation of the harmonic elimination feature during asymmetric changes in the modulating indexes among the modules. These asymmetric changes are natural in controlled rectifiers; thus, unwanted harmonics and input filter oscillations may appear. On the other hand, no such problems are found if MSHE

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is the modulation index factor and where the displacement factor given by

is

(10) Thus, the amplitude of each current harmonic ratio of respect to is given by

with

(11) In the ideal situation where all the modulating indexes are the same becomes a function of the summation of the displacement factors (12)

Fig. 3. Switching angles as a function of the modulation index for the MSHE . (a) Upper-module. (b) Lower-module.

Then, the procedure to calculate the synchronization references for each module can be summarized as: a) Set , the dominant harmonic of the SHE. b) Calculate the relative displacement angle for the th module to add up to zero in the dominant harmonic of the SHE in a -modular scheme

patterns are used in inverters (CSI) because they work with fixed patterns. C. Displaced Selective Harmonic Elimination (DSHE) in MCSC If current source rectifiers are connected in parallel to the same input filter, the total AC modulated current is obtained by adding up the individual rectifier currents . Then, the input current for phase becomes (7) If the DC currents of the current source rectifiers are controlled to follow the same reference , the expression for the current harmonics in can be written as (8) where is the displacement function and displacement for the th rectifier. If the current harmonic ratio of then

is the relative is defined as (9)

(13) and the relative c) Given the group displacement angle displacement angle for the th module , then the displacement for the th rectifier is calculated as (14) Thus, the relative gain for any th order harmonic when a th order harmonic is eliminated is given by (15), shown at the bottom of the page. The plot of with respect to the normalized order harmonic in Fig. 4 shows the effects of the number of modules in the harmonic reduction. D. THD and Asymmetric Modulating Indexes Rectifiers operate by dynamically changing the modulating . indexes in order to regulate the DC link currents ( The above condition does not guarantee identical modulating indexes for all the rectifiers, resulting in a degradation in the intended harmonic elimination and therefore in the THD of the AC current in the rectifiers. An important question is which technique is less affected by asymmetric modulating indexes.

(15)

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Fig. 4. Relative gain for an arbitrary th harmonic order when a haris eliminated. is plotted for normalized . (a) Two monic of order . (b) Three cells . (c) Four cells . cells

This question can be studied in each technique with THD in mind. For symmetric modulating indexes in MSHE, where one has

Fig. 5. THD of total rectifier input for different modulating indexes in two cells using MSHE technique.

(16)

In the first -1 nontriple harmonics do not exist because those harmonics are not present in SHE, and the first unwanted harmonic group is highly attenuated. Then, the THD can be approximated by

where is the first characteristic harmonic for the ideal gating pattern and is described by (9). Thus, the THD for symmetric modulating indexes can be written as

(20)

(17) In the case of asymmetric modulating indexes in MSHE, where the expression for THD in (17) is not true due to nontriple odd harmonics. The THD for this condition is defined by

where the first unwanted harmonics are given by . Now, considering asymmetric modulating indexes, the approximation given by (20) is not true and it is replaced by the general expression

(21)

(18)

On the other hand, for symmetric modulating indexes in , with given by (13), the THD DSHE, where is defined by

(19)

Contrary to MSHE, the -1 lowest order harmonics do not appear on the input current pattern. The effects of asymmetries on the modulating indexes can easily be drawn for two cells in order to illustrate the phenomena.Figs. 5 and 6 show the THD for different modulating indexes using two converters and MSHE and DSHE techniques, respectively. The dotted line indicates symmetric modulating indexes . MSHE presents regions where slight changes in the modulating indexes can produce considerable changes in THD. For example, operating at the modulating index and shifting to [0.6, 0.5] changes the THD from 42% to 89.8%. By contrast, the transitions for MSHE are moderate. In fact, for the conditions described above, the THD changes from 41.2% to 44.9%. Thus, under normal operation of modular rectifiers, THD in the DSHE technique is lower than THD in the MSHE technique. In brief,

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Fig. 6. THD of total rectifier input for different modulating indexes in two cells using DSHE technique.

with modular rectifiers operating normally, DSHE outperforms MSHE in terms of THD.

Fig. 7. Gating pattern generation for phase a in an equivalent VSC; (a) comwith commutation angles y parison of synchronization signal (b) gating pattern for phase a.

IV. GENERALIZED IMPLEMENTATION ON DIGITAL SYSTEMS The gating block provides the firing signals for the semiconductor devices using the commutation angles calculated in the previous sections. This section presents generalized algorithms for using in real time operation of SHE/MSHE/DSHE on MCSC. A. Implementing a Generalized SHE/MSHE/DSHE Gating Block The logic behind the gating block is common for SHE, MSHE, and DSHE. The core of this gating block is the SHE modulator shown in (Fig. 7). The modulator requires three input signals: (a) a fundamental modulating index reference to define the amplitude, (b) a common synchronization signal, and (c) a displacement angle associated with each rectifier to define the displacement of the gating pattern. The switching angles are functions of and calculating them online is expensive in terms of processing time. The results of solving the equations described in Section II can either be stored in lookup tables or replicated using approximation functions. Thus, in each sampling time the th commutation angle for the th rectifier is computed using a polynomial approximation of order and stored on the th vector . The polynomial approximation is expressed as

Fig. 8. Flow chart of the algorithms on a DSP6713.

function of the number of samples and the sample period . This function is restricted to the dominium and is given by (23)

(22)

(24)

A tenth-degree polynomial provides a good trade-off between accuracy and speed, resulting in errors lower than 1 degree. The synchronization signal is provided by a modified PLL as described in [29]. There, the frequency of the pattern is given by the slope of the ramp function , which is defined as a

As this approach works with a fixed number of samples is changed in order to match the operating frequency of the digital system with the AC mains. Additionally, for each rectifier, three auxiliary angles: , and , are calculated considering the displacement of each

GUZMAN et al.: DIGITAL IMPLEMENTATION OF SELECTIVE HARMONIC ELIMINATION TECHNIQUES

Fig. 9. Setup schema for testing SHE, MSHE and DSHE under symmetric and asymmetric conditions on the rectifier stage of a MCSC with variable load and and . operation capability for

Fig. 10. SHE (Ch. 1) . THD 68%, 5 A/div. 3)

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, 200 v/div, (Ch. 2)

THD 15%, 5 A/div, (Ch.

TABLE I CALCULATION TIME FOR DSP6713

TABLE II SETUP PARAMETERS

Fig. 11. MSHE operation with symmetrical modulating indexes (Ch. 1) , 200 V/div, (Ch. 2) THD 9%, 20 A/div, (Ch. 3) . THD 43%, 5 A/div , 5 A/div. (c)

rectifier’s current pattern and the displacement correction due to the conversion of phase to line patterns as

Step 1) Elements of are compared with and , to obtain active states of an equivalent voltage source converter, as shown in Fig. 7. Step 2) , , and , are used to generate distributing pulses for zero states . Step 3) Check for a zero state using (26)

(25) Each angle is restricted to the dominium , as well as . Once the commutation angles and synchronization signals are computed, the resulting gating pattern is built using the logic described in [26] and [27]. The following steps summarize the process to build the gating pattern:

Step 4) If , use the signals the active gating signals source topology

to

to calculate for the current

(27)

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Fig. 12. MSHE 3) 5 A/div, (Ch. 2)

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operation with symmetrical modulating indexes (Ch. , 5 A/div, (Ch. 4) , 5 A/div.

Fig. 13. MSHE operation with asymmetrical modulating indexes (Ch. 1) , 200 V/div (Ch. 2) , 5 A/div THD 18%, 5 A/div. (Ch. 3) THD 79.5%, , 5 A/div. 5 A/div, (Ch. 4)

Otherwise, if check which of choose the right zero state of to

is true and according to

(28)

B. Implementation Using DSP6713 and Calculation Times The algorithm presented in Fig. 9 was implemented on a DSP320C6713 TI processor and programmed in C language using Code Composer Studio V® software. The program runs the synchronization and control blocks described in [17] and [29]. That approach uses a modified digital PLL providing both synchronization with the AC mains and operation at a unitary

Fig. 14. MSHE 1) , 5 A/div, (Ch. 2)

operation with asymmetrical modulating indexes (Ch. , 5 A/div, (Ch. 4) , 5 A/div.

Fig. 15. DSHE, operation with symmetrical modulating indexes, , (Ch. 1) , 200 V/div, (Ch. 2) THD 4%, 20 A/div. (Ch. 3) . THD 33%, , 5 A/div. 5 A/div, (Ch. 4)

displacement power factor. The voltage of phase is sampled using an ADS8345 ADC, which has a 16-bit solution, eight channels and a minimum sampling time of 10 s per channel. The DSP digital ports (24 digital channels) are used to send the gating signals to the rectifiers (six signals for each module). The system operates at giving a minimum pulse resolution of two degrees. Even if the DSP could run the algorithms faster, sensing voltages and currents for each module and running the control loops depicted in [17] takes slightly longer. Polynomial functions, were used for all the cases. Two different sets of approximations were used to perform MSHE, one for each module, in order to achieve the elimination of harmonics 5, 7, 11, and 13. To perform DSHE each displacement angle was set to perform the 11th harmonic cancellation in order to reduce the residual harmonics. Results of processing time are presented in Table I, which shows a 33% less time in MSHE with respect to DSHE for the same conditions .

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Fig. 16. DSHE, operation with asymmetrical modulating indexes, , (Ch. 1) 200 V/div, (Ch. 2) THD 4%, 5 A/div. (Ch. 3) . , 5 A/div. THD 33%, 5 A/div, (Ch. 4)

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Fig. 18. DSHE, , operation with asymmetrical modulating 200 V/div, (Ch. 2) THD 4%, 20 A/div. (Ch. 3) . THD indexes, (Ch. 1) , 5 A/div. 33%, 10 A/div, (Ch. 4)

TABLE III THD FOR SYMMETRIC LOADS

TABLE IV THD FOR ASYMMETRIC LOADS

Fig. 17. DSHE, , (Ch. 1) indexes. , THD 33%, 10 A/div, (Ch. 4)

, operation with symmetrical modulating V/div(Ch. 2) THD 4%, 20 A/div. (Ch. 3) , 5 A/div.

TABLE V HARMONIC AMPLITUDE (AS % OF FUNDAMENTAL) FOR SYMMETRIC LOADS

V. EXPERIMENTAL PERFORMANCE To validate the theoretical considerations SHE ( , elimination of 5th and 7th), MSHE ( , elimination of 5th, 7th, 11th, 13th), DSHE ( , elimination of 5th, 7th, 11th), and DSHE ( , elimination of 5th, 7th, 11th) were tested in an experimental setup (Fig. 9). The experiment considered three current source rectifiers feeding three isolated loads in order to evaluate the MCSCs at the rectifier stage under controlled symmetrical and asymmetrical conditions. The parameters of the experimental setup are given in Table II. To evaluate symmetrical conditions the loads are identical and each converter operates with modulating indexes close to 0.95. To evaluate asymmetrical conditions one load is changed to force the corresponding rectifier to reduce the modulation

TABLE VI HARMONIC AMPLITUDE (AS % OF FUNDAMENTAL) ASYMMETRIC LOADS

FOR

index value close to 0.4 in order to keep its DC current constant. Standard SHE is used as the reference for comparing other techniques. Relevant information for the experimental waveforms is given by the THD changes, summarized in Tables III and IV. They show that under symmetrical operation the THD in

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TABLE VII HARMONIC AMPLITUDE (AS % OF FUNDAMENTAL) FOR SYMMETRIC LOADS

TABLE VIII HARMONIC AMPLITUDE (AS % OF FUNDAMENTAL) ASYMMETRIC LOADS

FOR

both MSHE and DSHE techniques is lower than the THD in SHE but under asymmetrical operation the THD in MSHE is higher than the THD in standard SHE. On the other hand, and under asymmetrical operation, the THD in DSHE is still better than in SHE. This phenomenon is consistent with the theoretical analysis of Section III. Values relevant to unwanted harmonic amplitudes for input current appear in Tables V and VI, and values relevant to unwanted harmonic amplitudes for the total rectifier input current appear in Tables VII and VIII. Under symmetric conditions all unwanted harmonics are small and similar for all techniques. However, under asymmetrical operation MSHE presents an important increase of the unwanted harmonics as compared with SHE. On the other hand, and under asymmetrical operation, the DSHE techniques showed a moderated increase of the unwanted harmonics, achieving better performance than SHE. Patterns used to fill Table III to VIII are shown in Figs. 10 to 16. For each MSHE experiment two figures are presented. A primary figure shows the input voltage , input current , total rectifier current , and first cell rectifier current . An auxiliary figure shows total current and patterns for both cells. For each DSHE experiment, a standard figure shows input voltage , input current , total rectifier current and first cell rectifier current . VI. CONCLUSION This work shows the comparison of MSHE and DSHE on MCSCs. It is proved that both techniques can be implemented by modifying some inputs and parameters of standard SHE modulators. Experimental results show that MSHE requires shorter processing time than DSHE if the same number of rectifiers is used. Regarding harmonic elimination under symmetric conditions, similar remaining harmonics are obtained for all techniques. For asymmetrical operation of the rectifiers, MSHE presents important increases in the amplitude of the residual harmonics and THD, as opposed to DSHE, which maintains indexes better than standard SHE. REFERENCES [1] B. Wu, J. Pontt, J. Rodriguez, S. Bernet, and S. Kouro, “Current-source converter and cycloconverter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 2786–2797, Jul. 2008.

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GUZMAN et al.: DIGITAL IMPLEMENTATION OF SELECTIVE HARMONIC ELIMINATION TECHNIQUES

[24] W. Fei, X. Du, and B. Wu, “A generalized half-wave symmetry SHE-PWM formulation for multilevel voltage inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 9, pp. 3030–3038, Sep. 2010. [25] Y. Zhang, Z. Zhao, and J. Zhu, “A hybrid PWM applied to high-power three-level inverter-fed induction-motor drives,” IEEE Trans. Ind. Electron., vol. 58, no. 8, pp. 3409–3420, Aug. 2011. [26] J. Espinoza, G. Joós, J. Guzmán, L. Morán, and R. Burgos, “Selective harmonic elimination and current/voltage control in current/voltage source topologies: A unified approach,” IEEE Trans. Ind. Electron., vol. 48, no. 1, pp. 71–81, Feb. 2001. [27] J. Guzmán, J. Espinoza, L. Morán, and G. Joós, “Selective harmonic elimination in multi-module three-phase current-source converters,” IEEE Trans. Power Electron., vol. 25, no. 1, pp. 44–53, Jan. 2010. [28] G. Guíñez, J. Guzmán, J. Espinoza, C. Baier, and P. Mel´ın, “Improvements in harmonic mitigation for multilevel AC-drives for high power applications,” in Proc. IEEE Conf. Rec. ISIE 2010, Jul. 4–7, 2010, pp. 2921–2926. [29] M. A. Perez, J. R. Espinoza, L. A. Moran, M. A. Torres, and E. A. Araya, “A robust phase-locked loop algorithm to synchronize staticpower converters with polluted ac systems,” IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 2185–2192, May 2008. Johan I. Guzman (S’04–M’09) was born in Lota, Chile, in 1976. He received the Electronic Engineering Title, the M.Sc. and D.Sc. degrees from the University of Concepción, Concepción, Chile, in 2000, 2007, and 2009, respectively. Since 2006 to 2008 he combined research and academic activities with private consulting, giving classes at the University of Concepcion and the University of Desarrollo. Currently, he is an assistant professor at the University of Talca where he has been since 2008. He has consulting experience on energetic efficiency for little and medium business. His active research topics are on topologies, modulating patterns and magnetic coupled converters, publishing their results in IEEE transactions (4) and IEEE conference records (17).

Pedro E. Mel´ın (S’10) was born in Chillán, Chile, in 1982. He received the Eng. degree in electronic engineering and the M.Sc. degree in electrical engineering from the University of Concepción, Concepción, in 2006 and 2010, respectively, where he is currently pursuing the D.Sc. degree in electrical engineering in the area of multicell topologies based on current source converters, and working in the design and construction of an electrical vehicle for solar challenges.

Jose R. Espinoza (S’92–M’97) received the Eng. degree in electronic engineering and the M.Sc. degree in electrical engineering from the Universidad de Concepcion, in Concepcion, Chile, in 1989 and 1992, respectively, and the Ph.D. degree in electrical engineering from Concordia University, Montreal, QC, Canada, in 1997. Since January 2006, he has been a Professor in the Department of Electrical Engineering, at the Universidad de Concepcion, where he is engaged in teaching and research in the areas of automatic control and power electronics. He has authored and co-authored more than 100 refereed journal and conference papers and contributed to one chapter in the Power Electronics Handbook, third edition, published in 2011 by Academic Press. Prof. Espinoza is currently an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS.

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Luis A. Morán (S’79–M’81–SM’94–F’05) was born in Concepción, Chile. He received the Degree in electrical engineering from the University of Concepción, Concepción, Chile, in 1982, and the Ph.D. degree in electrical engineering from Concordia University, Montreal, PQ, Canada, in 1990. Since 1990, he has been with the Electrical Engineering Department, University of Concepción, where he is a Professor. He has written and published more than 50 papers in Active Power Filters and Static Var Compensators in IEEE Transactions. He is the principal author of the paper that got the IEEE Outstanding Paper Award from the Industrial Electronics Society for the best paper published in the IEEE TRANSACTION ON INDUSTRIAL ELECTRONICS during 1995, and the co-author of the paper that was awarded in 2002 by the IAS Static Power Converter Committee. From 1997 until 2001 he was Associate Editor of the IEEE Transaction on Power Electronics. In 1998, he received the City of Concepción Medal of Honor for achievement in applied research. He has extensive consulting experience in mining industry, especially in the application of medium voltage ac drives, large power cycloconverter drives for SAG mills, and power quality issues. His main areas of interests are in AC drives, power quality, active power filters, FACTS and power protection systems.

Carlos R. Baier (S’08–M’10) was born in Temuco, Chile, in 1979. He received the B.S., M.Sc. and D.Sc. degrees in electrical engineering from the University of Concepcion, Concepcion, Chile, in 2004, 2006, and 2010, respectively. Since 2009, he has been a Professor in the Department of Industrial Technologies, University of Talca, Talca, Chile, where he is teaching in the areas of automatic control and power electronics. His research interests include improved control techniques for multicell converters, new multilevel topologies and high energy efficient improvements for medium-voltage converter topologies.

Javier A. Muñoz (S’08–M’12) was born in Concepción, Chile, in 1983. He received the B.S. (with first class honors), M.Sc., and D.Sc. degrees in electrical engineering from the University of Concepcion, Concepcion, Chile, in 2007, 2009, and 2012, respectively. Since April 2011, he has been with the Department of Industrial Technologies, University of Talca, Curico, Chile, where he is currently teaching in the areas of dynamic systems and robotics. His research interests include digital control of modular multi-level converters to improve power quality.

Gonzalo A. Guiñez (M’10) was born in Chillán, Chile, in 1983. He received the engineer degree in electronic Engineering from the University of Concepción, Concepción, Chile, in 2008. He is currently working as Gearless Mill Drives Reliability Engineer at División El Teniente, CODELCO, Chile. His research interests include gearless motors for high power grinding mills, HVDC transmission systems and FACTS.