Digital Signal Generator for real-time FPGA Power Quality Alghoritm test A. Aprigliano, M. Caciotta, S. Giarnetti, F. Leccese Electronic Engineering Department, University of Roma “Roma Tre” Via della Vasca Navale n.84, 00146, Roma, Italy, tel. +390657337085, fax +390657337101
[email protected],
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[email protected] Abstract—This paper proposes an FPGA based device implementing a signal generator for power quality analysis. The device simulates the behavior of an ADC connected to the power grid. It’s main goal is to make it easy to have real-time tests on algorithms implemented on embedded hardware. Keywords: Spartan3, Signal Generator, hardware test-bench.
I.
Power Quality,
INTRODUCTION
The aim of many algorithms developed for the power quality is the detection of events of different nature and duration [1]. For the identification of the events in a monitoring network is necessary a real-time analysis of the network voltage and the implementation of the algorithms in embedded hardware like DSP processors and FPGA is strongly growing up. Today is mostly used the FPGA platform because it allows to implement complex algorithm with an elevated samplingrate. Moreover the FPGA market is getting closer to the digital signal elaboration offering devices equipped with integrated DSP modules. So it is possible to optimize the digital calculation in speed and parallelism. The HDL code, which describe the digital circuit, is being used for the FPGA planning. The functionality of the code can be checked with simulators. After the synthesizing of the HDL code and the generation of a bit stream file for the programming of the device, it is possible to use the hardware co-simulation through the “FPGA in the loop” system. In this way it is possible to generate the input signal and to read the computed output values of the device with a software using the JTAG protocol or Ethernet. This test is very slow because uses a software temporization which simulates the execution time. Moreover it’s impossible to verify if the circuit synthesized on the device is working correctly on the right frequencies. In this work will be proposed a new system for the testing of power quality algorithms implemented on FPGA in real time using another FPGA based system to generate signals. The new device will be able to be controlled by a PC and to change the features of the generated signal so to simulate typical situations of grid signals. It can also interpret external commands to change the characteristics of the signal without interrupting the generation. So many parametric models of the signal can be generated simply re-programming the FPGA so make easy the test phase. In this way also a cheap FPGA, like as a Spartan3 family of the Xilinx [2], can be used to perform many types of tests.
This structure overcomes the limit of a software-PC based system which, because of the operative system, doesn’t warranty a right timing. On the other the re-configurability typical of the FPGA system allows to obtain a cheap and versatile system for Power Quality test. II.
DEVICE DESCRIPTION
The classic model of a network signal is based on its fundamental and its harmonics. sin ω
sin ω
φ
where N is the number of harmonics, Ak is the amplitude and φk is the phase for each harmonic compared with the fundamental, and ω is the pulsation of the signal. The signal parameters are not stationary and they could be useful to evaluate the performances of the algorithm proposed in literature also in not-stationary conditions because each parameter of the model is function of the time. For example phenomena of fluctuations of the signal amplitude (flicker) are very common, which could be considered as a modulation of Ak Other types of disturbances, which can be included in the model, are the sub-harmonics and the inter-harmonics, which are sinusoidal components at frequencies non multiple of the fundamental. According to the test it could be useful to use a different model with modifiable parameters. The proposed system uses the reconfigurations of the FPGA to perform real time tests of algorithms implemented on embedded logic, acting like a digital functions generator . The system is based on a software interface which communicates by serial protocol with an UART interface implemented on the device. It has been defined a data frame to allow the communication of the single values of the model parameters which are going to be set during the test phase. A command interpretation system has been designed by a finite state machine which has to interface the chosen model modifying the numeric value of the parameter. The signal will be generated through a processing block which has to perform the mathematic operations useful to the definition of the samples. A general scheme of the purposed system is shown in the Fig. 1.
The output is composed by 17 pins, one represents the "data ready" and the others 2 byttes the sample signed integer formatted.
PC
The inside architecture is thought to offer the maximum modularity in terms of harmonics and non-harmonics sinusoidal components, this iss due to the fact that both the higher frequency harmonics and a the fundamental share the same time base. Hence the blocks b producing every single signal are identical (Fig. 2); to assign the order of the harmonic n to set a constant value to the single block it is simply necessary (2,3...,25).
SW Interface
RS232 FPGA
UART
Control logic parameters signal model
Signal bus DUT
Figure 1
Signal generator system block diagram.
The software offers an user interface to permit p the manual setting of some parameters or to launch thee required specific procedures of parameters variation (likee the sweep in frequency). It is possible to test the connectioon with the FPGA from the main form interface simply sending a known string. If the communication is established, the device will generate an u identifies acknowledgement containing a code which uniquely the programmed signal’s model. In this wayy the screen setting parameters will allow the modification of onnly the parameters included in the model loaded on the device. A. System Architecture The device simulates the behavior of an ADC A connected to the electric net (220 V 50 Hz), with a resoluttion of 16 bits and a frequency of sampling of 25 KHz. Its innput is an RS232 connection which allows to send all thee parameters that characterize the simulated signal from the PC C to the terminal. The parameters are: •
Magnitude and Frequency of the funddamental;
•
Magnitude and phase of the harmoniics of higher order up to the twenty-fourth;
•
Magnitude and frequency of possible inter-harmonics and sub-harmonics;
Figure 2
Modularity on o Simulink block scheme
The time reference is generrated by the TimeBase block and it’s based on a 25 kHz frequenncy 25,000 modulus counter, so to get reset every second; fuurther the signal is normalized between 0 and 2π. At the outpput we also have a trigger signal hooked to the counter to check the counter reset. At the TimeBase block outt the signal is multiplied by the parameters: "Fundamental Frequency" F (from which the frequencies of the superior harmonics are derived) and "SubFreq" for possible Sub-harrmonics. The further blocks are identical (Fig.2), both for the generation of the fundamental and the higher order harmonics and for the sub-harmonics. They just differ by the parameters at their inputs which are: •
"Arg" -Argument of thee sinusoidal function (2πft);
•
"Phase" - the initial phase;
•
HDL Coder [4];
•
"Amplitude" - the magnitude of the signal;
•
Stateflow Toolbox [5];
•
"Trigger"- High when the counter is reset;
•
System Generator (Xilinx ISE) [6];
•
"K"- it is a constant that determines the order of the harmonic.
•
Xilinx Blockset;
•
Modelsim (Mentor Graphics);
The communication protocol is pretty easy. To set the Fundamental parameters it is necessary to send the “A” character for the magnitude or “F” for the frequency followed by the value. To set the higher order harmonics parameters, send the “H” character followed by a number to identify which harmonic (1, 2, 3, …) then an “A” for the magnitude or “P” for the phase followed by the numeric value. The Sub-harmonics parameters are set by sending first an “S” followed by an “F,” if you want to set the frequency or an “A” for the magnitude, followed by the value.
The project has initially been developed in Simulink environment using the Matlab’s native numerical format (Double). Spartan 3E Starter Kit SIGNAL GENERATOR
RS 232
Signal samples
PC FPGA in the loop
Ethernet Figure 3
Simulink SinGen block diagram.
Inside the SinGen block firstly there is a system for the generation of the argument of the sine: 2Kπft +φ. Then, this signal is sent to a negative feedback system (Fig. 3) which limits the signal between 0 and 2π operating by subtractions. The trigger signal is used to warranty the signal continuity (without phase hopping) also when the time base is reset. At the end of this phase, the signal is sent to a trigonometric block that produces a sinusoid by Cordic approximation and multiplied by the magnitude. The generating blocks outputs are now added among them creating the 16 bits output signal. The device is provided with a bi-directional RS232 interface at a speed of 9,600 baud, no parity and 2 stop bits. It is possible to characterize the signal at every time while the system is running. The device’s architecture has been designed in the Matlab environment, using mostly the Simulink application and several special Libraries. Other segments of the software have been used to simulate, to synthesize HDL code and to program the FPGA as below listed: •
Fixed Point Toolbox [3];
DEVICE UNDER TEST
Xilinx ML 605 board (DSP FPGA) Figure 4 – Test bench configuration.
The control logic blocks have been realized with the Stateflow library, because it simply manages Finite State Machines. These blocks are in the communication section and are used to manages the decoding of the instructions received from terminal. In all the signal generation blocks is present another finite state machine which works as a resettable counter. After the simulations success, the Fixed Point Toolbox is used to convert the FPGA internal signals in fixed point format, this is due to the need to match the FPGA numerical formats which aren’t compatible with floating point numbers. Once defined the fixed point, the project has been converted in VHDL language with the HDL Coder tool which,
through the integration with "Modelsim", provided us a software “test bench” to check the compiled VHDL. Hence it has been possible to compare the Simulink model with the compiled one. After the code test, in order to program the FPGA device, it is possible to synthesize the VHDL code in the Bitstream. This has been accomplished in the Simulink environment too, thanks the high integration among Matlab and “System Generator” of Xilinx ISE. The realization of the Bitstream and a hardware test bench able to compare the Simulink’s model results with the ones coming from the FPGA development board has been realized in just one software environment. III.
HARDWARE TEST BENCH
The use of Simulink to design the hardware architecture of a particular algorithm allows to exploit the FPGA in the loop system to verify its correct functioning, but the management of the software timing used for the input signal generation doesn’t allow to perform a real-time test. In the Fig. 4 is shown a possible scheme for the performing of a real-time controlled test which use the signal generation purposed in this work. In this way the software has not to generate the clock and the signal samples, but it only has to control the device passing the parameters configuration of the chosen signal model. The signal samples are sent with the right timing to the board that mounts the FPGA where has been implemented the algorithm [7]. The FPGA in the loop system can be used to read the input and output signal so to verify the right
functioning of the hardware algorithm in real time, through Ethernet or JTAG connection. IV.
CONCLUSIONS
Exploiting the FPGA versatility a very cheap and particularly efficient system for Power Quality hardware test has been realized. The system is able to implement different signals for several analysis and allows to modify the signal characteristics during its generation. In this way it is possible to simulate steady and non steady conditions. The system has been designed in Matlab Simulink environment also using specific libraries and implemented on a Spartan3 board particularly cheap. REFERENCES [1] [2] [3] [4] [5] [6] [7]
M. Bollen, I. Gu, “Signal Processing of Power Quality Disturbances” Wiley-IEEE Press, pp. 277-315, 2006. P. P. Chu, “FPGA prototyping by VHDL examples. Xilinx Spartan 3 version”, Wiley-Interscience, 2008. “Fixed-Point Toolbox User’s Guide R2011b”, 2011. “Simulink HDL Coder User’s Guide R2011b”, 2011. “Stateflow user’s Guide R2011b”, 2011. Xilinx Inc., Xilinx System Generator for DSP v 12.3 User’s Guide, September, 2010. M. Caciotta, S. Giarnetti, F. Leccese, E. Pedruzzi, “Curve Fitting Algorithm FPGA implementation”, Environment and Electrical Engineering (EEEIC), Rome, 2011
