Direct extraction and numerical simulation of the base ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 6, JUNE 1999

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Direct Extraction and Numerical Simulation of the Base and Collector Delay Times in Double Heterojunction Bipolar Transistors Mohammad Sotoodeh, A. H. Khalid, Hong Sheng, Farid A. Amin, Tacar Gokdemir, Ali A. Rezazadeh, Andy P. Knights, and Christopher C. Button

Abstract—A new method is presented to evaluate the base and collector transit times, B and C ; in heterojunction bipolar transistors (HBT’s) from the phase and magnitude of the commonbase current gain, (!); which itself was directly extracted from measured S -parameter data. The method is applied to InGaP/GaAs single and double HBT’s. A smaller cutoff frequency in the latter device is attributed to B and C due to two effects: trapping of electrons in the conduction band triangular barrier existing at the base-collector (B-C) heterojunction and smaller saturation velocity of electrons in InGaP as compared to GaAs. Finally, a new B-C design of InGaP/GaAs DHBT’s is proposed to partially compensate the transit time effects. Numerical simulation of the cutoff frequency demonstrates the superiority of the proposed structure for high-frequency applications. Index Terms—Composite collector double heterojunction bipolar transistors, delay times, equivalent circuits, heterojunction bipolar transistors, semiconductor device modeling, semiconductor epitaxial layers.

I. INTRODUCTION

A

CCURATE extraction of the small-signal equivalent circuit of heterojunction bipolar transistors (HBT’s) is important for optimizing device performance. The most commonly used extraction technique is numerical optimization of the model-generated -parameters to fit the measured ones. It is well-known, however, that optimization techniques may result in nonphysical and/or nonunique values of the components. Alternative extraction methods exist which make use of either special test structures [1] or analytically derived expressions for a direct calculation of as many equivalent circuit elements as possible [2]. In this work, a combination of the schemes proposed in [1] and [2] are employed to extract the parameters of the -like equivalent circuit model of the and HBT’s shown in Fig. 1. However in [2], the values of in the formulation of are calculated using numerical

Manuscript received August 19, 1998; revised January 2, 1999. The review of this paper was arranged by Editor A. S. Brown. This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), U.K. M. Sotoodeh, A. H. Khalid, H. Sheng, F. A. Amin, T. Gokdemir, and A. A. Rezazadeh are with the Center for Optics and Electronics, Department of Electronic Engineering, King’s College, London, U.K. A. P. Knights is with the Department of Electronic and Electrical Engineering, University of Surrey, Surrey, U.K. C. C. Button is with the Department of Electronic and Electrical Engineering, University of Sheffield, Sheffield, U.K. Publisher Item Identifier S 0018-9383(99)04585-2.

Fig. 1.

T -like

equivalent circuit model for HBT’s.

optimization methods, while in the present work they are directly extracted from the frequency dependence of The method is applied to InGaP/GaAs single and double HBT’s to explain the reasons behind the rather lower cutoff of the latter device. Using the extracted delay frequency times, it has been confirmed that the trapping of electrons in the conduction band triangular quantum-well formed at the base-collector (B-C) heterojunction of DHBT’s and lower saturation velocity of InGaP as compared to GaAs are the degradation in DHBT’s. Furthermore, a new main causes of B-C design of InGaP/GaAs DHBT’s employing a quaternary InGaAsP material lattice-matched to GaAs is proposed to partly overcome the above limitations of DHBT’s. Numerical simulation of the cutoff frequency for various DHBT designs confirms the advantage of the proposed structure for highfrequency power applications. II. DEVICE STRUCTURE Both SHBT and DHBT devices have similar emitter and base structures. In both transistors, the base layer is p ˚ thick, collector layer is 5000 cm GaAs 1000 A ˚ A thick, and sub-collector is n cm GaAs ˚ thick. The collector of the SHBT is simply n 7000 A

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A plot of the left-hand side of (2) versus determines both and Finally, can be found from fitting the slope versus plot to that in Fig. 2. of model-generated The common-base current gain can be expressed as [6] (3) with and

for a uniform-base HBT. Assuming and one can write (4) (5)

Fig. 2. Total delay time versus inverse of collector current (VCE = 2:5 V).

cm GaAs, while that of the DHBT is composed of a ˚ undoped GaAs spacer and 4800 A ˚ n cm 200 A In Ga P. m B-E junction area HBT’s were fabricated The using conventional photolithography and wet chemical etching process. Device isolation was achieved using multiple energy He and O ion implantation [3]. DC characteristics of the HBT’s were measured using an HP4145B Semiconductor Parameter Analyzer. On-wafer -parameter measurements were then carried out using HP8510 Network Analyzer and cascade microwave probes. The SHBT and DHBT have dc current ) of gains of 20 and 15, B-C breakdown voltages (BV 21 and 32 V, and C-E offset voltages of 150 and 25 mV, respectively. III. EXTRACTION PROCEDURE From

-parameter measurements the current gain for m single and double HBT’s have been deduced. is calculated The total emitter-to-collector delay time values from and using the extracted in Fig. 2. For small to medium collector plotted against varies linearly (as expected) with a slope given currents [4], where is an effective by parasitic capacitance due to the interconnects/pads. Parameter extraction procedure starts from the measurement of an open test structure [1] for de-embedding the parasitic pad capacitances in Fig. 1. Then the direct extraction scheme suggested in [2] is applied to the resulting Z-parameters to find and Assuming the can be extracted from the real part emitter series resistance at low to medium frequencies. Since of (1) can also be found from the imaginary part of and the following relation is used [5]:

To find

(2)

are In Fig. 3, the phase and squared magnitude of respectively, for both the SHBT and plotted against and DHBT. The slopes of these graphs provide two equations for and This system of equations two unknowns, namely usually has two sets of positive results and the set with more physically meaningful values should be picked up. The extracted values of these two parameters together with other circuit element values are summarized in Table I. IV. DISCUSSION The values of the parameters listed in Table I are almost and identical for the cases of SHBT and DHBT, except which are significantly larger in the DHBT. The larger in DHBT’s can be attributed to the trapping of electrons in the quantum-well barrier formed between the GaAs spacer and InGaP collector. This may cause an additional delay time for electron transfer from emitter to collector. On the other hand, smaller saturation velocity of electrons in InGaP as in compared to GaAs may result in an enlargement of InGaP/GaAs DHBT’s. Reported values of saturation velocity (either measured or calculated by Monte Carlo methods) in – In Ga P and GaAs are in the ranges of cm/s and – cm/s, respectively (see for example in our DHBT [7], [8]). Therefore, an almost 50% higher can be explained by an approximately the same difference in the average saturation velocities reported for the above two materials. in DHBT’s needs to be sacrificed Although the larger for the price of larger breakdown voltage, lower offset voltage, can be and smaller leakage current, the large difference in avoided by an appropriate design of the B-C heterojunction in DHBT’s. The depth of the potential well in the B-C junction needs to be minimized in order to remove the carrier trapping effect at this junction. Based on our numerical modeling of DHBT’s [9], we suggest to employ a step-grading B-C heterojunction using InGaAsP quaternary material latticematched to GaAs as intermediate layers. Although the use of InGaAsP lattice-matched to InP in the design of InP/InGaAs DHBT’s has been studied by many authors [10], [11], to the best of our knowledge, no report exists in the literature on the application of this material lattice-matched to GaAs for GaAs-based HBT’s. Fig. 4 demonstrates the conduction band diagram of the BC heterojunction with various designs. This figure clarifies the significance of step-grading structure in minimizing the

SOTOODEH et al.: DIRECT EXTRACTION AND NUMERICAL SIMULATION

(a) Fig. 3. (a) Phase and (b) squared magnitude of common-base current gain,

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(b)

(!); versus (a) angular frequency, !; and (b) !2 :

TABLE I PARAMETERS OF THE EQUIVALENT CIRCUIT MODEL IN FIG. 1 FOR InGaP/GaAs SINGLE AND DOUBLE HBT’s

Fig. 4. Numerically simulated conduction band diagram of the B-C junction of InGaP/GaAs DHBT with various design approaches at thermal equilibrium.

energy barriers in the conduction band, and thus the base transit time. To further elucidate the advantage of the proposed DHBT structure over conventional designs of InGaP/GaAs DHBT’s, we have carried out a comparison of the numerically simulated intrinsic cutoff frequencies for various SHBT and DHBT structures. The layer structures of the devices are summarized in Table II. All devices have similar emitter, base, and sub-collector structures and similar collector thicknesses ˚ The difference is only in the material and doping of of 5000 A. the collector. Device DHBT-A is a simple DHBT without any treatment for the B-C heterojunction spike. In device DHBT-B a GaAs spacer layer is inserted between GaAs base and InGaP collector layers to lower the potential spike, similar to the experimental DHBT in the present work. Device DHBT-C

employs a doping spike in the collector which both lowers the conduction band spike and reduces the width of this barrier, thus improving the tunneling transmission across it. This structure is similar to the one reported in [12]. Finally, DHBT-D is our proposed step-graded structure which employs a combination of GaAs spacer, InGaP doping spike, and InGaAsP step-grading layers. Fig. 5 shows the simulated intrinsic cutoff frequencies versus collector current density. Details of our numerical modeling software for III–V HBT’s are published elsewhere [9]. It is clear from Fig. 5 that the cutoff frequency of the DHBT-A device is significantly degraded as compared to the SHBT. In fact, the current blocking effect of the potential spike in the B-C heterojunction is so serious that the modeled current gain of the device is less than unity. A major improvement in the high-frequency performance is obtained by employing a thin GaAs spacer in DHBT-B. The cutoff frequency of

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LAYER STRUCTURE

OF THE

SINGLE

AND

TABLE II DOUBLE HBT’s USED

IN THE

NUMERICAL SIMULATION

of the structures are underestimated. However, this work is more concerned with the trend of the maximum achievable cutoff frequency rather than its actual value. Further work in our laboratory is under way to investigate the suggested design approach experimentally. A final comment to make is with regards to the simulated dc current gains of the above single and double HBT’s. While significant difference can be observed in the high-frequency performance of the HBT’s specified in Table I, the difference in their respective dc current gains is just minimal (apart from DHBT-A, of course, which has a current gain less than unity). Simulated maximum current gains of the devices SHBT, DHBT-B, DHBT-C, and DHBT-D are 29, 26, 29, and 29, respectively. V. CONCLUSION Fig. 5. Numerically simulated cutoff frequency fT versus collector current density JC for the single HBT and various DHBT structures specified in Table II (VCE = 2:5 V).

DHBT-B is almost identical to that of SHBT at low to moderate current densities where the emitter-to-collector delay However, time is dominated by the emitter charging time at higher current levels, where microwave HBT’s are biased for most of the applications, the cutoff frequency of DHBTB is significantly less than that of SHBT. This is due to the larger collector depletion region and base transit times in the DHBT-B as explained earlier. By using the thin doping spike in the collector (DHBT-C) the high-frequency performance to that will be slightly improved, but the closest maximum of SHBT will be resulted by using our proposed structure of DHBT-D. One can observe that still there is a slight difference in the maximum cutoff frequencies of DHBT-D and SHBT. This is due to the smaller electron saturation velocity in InGaP comparing to GaAs as discussed earlier. It is worth mentioning that the velocity overshoot of electrons inside the base and collector layers of the devices are not considered in the present simulation work, and therefore, the intrinsic delay times in all

In summary, the base and collector transit times of InGaP/GaAs single and double HBT’s are extracted directly from the measured -parameter data. The significantly larger and in the DHBT is attributed to both the carrier trapping effect in the existing potential well of the B-C conduction band, and the smaller electron saturation velocity in InGaP comparing to GaAs. Therefore, a new design approach for minimizing the base transit time in InGaP/GaAs DHBT’s is suggested which employs a step-graded B-C heterojunction using the quaternary material InGaAsP lattice-matched to GaAs. Numerical simulation of the cutoff frequency in various single and double HBT structures is performed which confirms the significant improvement of the base transit time in the proposed DHBT layer structure. This work demonstrates that with some careful design of the of the DHBT’s B-C heterojunction, the current gain and may approach those of the SHBT, while the former has added advantages of smaller offset voltage, lower leakage current, and larger breakdown voltage. Alternatively, one may compromise the larger breakdown voltage in DHBT’s to push the high-frequency performance of the device beyond that of the SHBT’s. This may be achieved by either doping the collector to higher values or reducing the thickness of the

SOTOODEH et al.: DIRECT EXTRACTION AND NUMERICAL SIMULATION

collector to obtain lower collector delay times, while still having similar breakdown voltages to SHBT’s. ACKNOWLEDGMENT M. Sotoodeh would also like to acknowledge the scholarship provided by the Ministry of Culture and Higher Education (MCHE) of Iran. REFERENCES [1] D. Costa, W. Liu, and J. S. Harris, Jr., “Direct extraction of the AlGaAs/GaAs heterojunction bipolar transistor small-signal equivalent circuit,” IEEE Trans. Electron Devices, vol. 38, pp. 2018–2024, Sept. 1991. [2] D. R. Pehlke and D. Pavlidis, “Evaluation of the factors determining HBT high-frequency performance by direct analysis of S -parameter data,” IEEE Trans. Microwave Theory Tech., vol. 40, pp. 2367–2373, Dec. 1992. [3] A. H. Khalid, M. Sotoodeh, and A. A. Rezazadeh, “Planar self-aligned microwave InGaP/GaAs HBT’s using He+ /O+ implant isolation,” in Proc. 5th Int. Workshop High Performance Electron Devices for Microwave and Optoelectronic Applications (EDMO’97), pp. 279–284. [4] W. Liu, D. Costa, and J. S. Harris, Jr., “Derivation of the emittercollector transit time of heterojunction bipolar transistors,” Solid-State Electron., vol. 35, pp. 541–545, 1992. [5] A. Kameyama, A. Massengale, C. Dai, and J. S. Harris, Jr., “Analysis of device parameters for pnp-type AlGaAs/GaAs HBT’s including highinjection using new direct parameter extraction,” IEEE Trans. Electron Devices, vol. 44, pp. 1–10, Jan. 1997. [6] R. L. Pritchard, Electrical Characteristics of Transistors. New York: McGraw-Hill, 1967. [7] W. Liu, T. Henderson, E. Beam III, and S. K. Fan, “Electron saturation velocity in Ga0:5 In0:5 P measured in a GaInP/GaAs/GaInP double-heterojunction bipolar transistor,” Electron. Lett., vol. 29, pp. 1885–1887, 1993. [8] M. V. Fischetti, “Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures—Part I: Homogeneous transport,” IEEE Trans. Electron Devices, vol. 38, pp. 634–649, Mar. 1991. [9] M. Sotoodeh, A. H. Khalid, and A. A. Rezazadeh, “Numerical modeling of AlGaAs/GaAs and InGaP/GaAs single and double HBT’s,” in Proc. 5th Int. Workshop High Performance Electron Devices for Microwave and Optoelectronic Applications (EDMO’97), pp. 223–228. [10] K. Kurishima, H. Nakajima, T. Kobayashi, Y. Matsuoka, and T. Ishibashi, “Fabrication and characterization of high-performance InP/InGaAs double-heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 41, pp. 1319–1326, Aug. 1994. [11] E. F. Chor and C. J. Peng, “Composite step-graded collector of InP/InGaAs/InP DHBT for minimized carrier blocking,” Electron. Lett., vol. 32, pp. 1409–1410, 1996. [12] J-I. Song, C. Caneau, K-B. Chough, and W-P. Hong, “GaInP/GaAs double heterojunction bipolar transistor with high fT ; fmax ; and breakdown voltage,” IEEE Electron Device Lett., vol. 15, pp. 10–12, Jan. 1994.

Mohammad Sotoodeh was born in 1968. He received the B.Sc. degree in electronic engineering (highest honors) from Isfahan University of Technology, Tehran, Iran, in 1991, and the M.Sc. degree in electronic engineering (highest honors) from University of Tehran in 1994. He is currently pursuing the Ph.D. degree at King’s College, London, U.K. His research thesis is on design, optimization, and characterization of InGaP/GaAs double HBT’s for microwave power applications. His research interests include heterojunction bipolar transistors for high-frequency, high-power, and/or high-temperature applications, numerical simulation of semiconductor devices, dc and highfrequency characterization of HBT’s, III–V semiconductor compounds and their material parametrization. Mr. Sotoodeh is the winner of the 1st Award in the 3rd Nationwide Olympiad of Mathematics, held in Zahedan, Iran, in 1986.

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A. H. Khalid received the M.Sc. degree in physics from Government College Lahore, Pakistan, and the M.Phil degree in experimental semiconductor physics from Quaid-i-Azam University of Islamabad, Pakistan, in 1990. In 1992, he registered for the Ph.D. degree at King’s College London, London, U.K. His research work was on fabrication and design of transparent gate field effect transistors (TGFET’s). He joined the Department of Electronics, Quaidi-Azam University, as a Research Associate to characterize the conductive polymers. He then worked on EPSRC-funded projects on fabrication of multilayer MMIC’s on GaAs substrate. He also worked on fabrication of self-aligned double heterostructure bipolar transistors (DHBT’s). His research interests are in material properties of indium-tin oxide (ITO) and ITO-based contact technology and novel fabrication techniques for advanced semiconductor devices such as HEMT’s and HBT’s.

Hong Sheng was born in 1971. She received the B.Eng. (Hons.) degree in electrical and electronic engineering from University College, London, U.K., in 1993, where she is currently pursuing the Ph.D. research degree. Her research work is carried out in collaboration with BT Laboratories, U.K., on InP/InGaAs HBT’s for optoelectronic integrated circuit applications. She has developed a physics-based analytical model, as well as designed and fabricated small geometry devices. Temperature behavior, defect and bias stress analysis have also been investigated.

Farid A. Amin was born in 1970. He received the B.Sc. (Hons.) degree in applied physics and the M.Sc. degree in semiconductor science and technology from Kingston Polytechnic, U.K., in 1991 and 1992, respectively. He is currently pursuing the Ph.D. degree at King’s College, London, U.K. His research is carried out in collaboration with Epitaxial Products International of Cardiff, U.K., on ohmic contacts to AlGaAs/GaAs and InGaP/GaAs HBT’s with special considerations for small geometry devices. He also has studied the reliability of contacts for high field and temperature applications.

Tacar Gokdemir was born in Larnaca, Northern Cyprus, in 1968. He received the B.Eng degree in electronic engineering from Queen Mary and Westfield College, University of London, London, U.K., and the the M.Sc. degree in communication and radio engineering from King’s College, University of London, in 1993. He is currently pursuing the Ph.D. degree at King’s College London, London, U.K. Since 1994, he has been working as a Research Associate in the Monolithic Microwave Integrated Circuits (MMIC) Research Team. His research interests encompass all aspects of the design and application of MMIC and modeling of multilayer passive MMIC components.

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Ali A. Rezazadeh received the Ph.D. degree in applied solid state physics from The University of Sussex, Brighton, U.K., in 1983. In September 1983, he joined GEC-Marconi Hirst Research Centre as a Research Scientist and became the Group Leader responsible for research and development into advanced heterojunction bipolar transistor devices and circuits for high-speed and digital applications. In 1988, he became a Senior Research Associate-Group Leader responsible for research and development into advanced high electron mobility transistor devices and circuits for analog applications. In October 1990, he joined the Academic Staff of the Department of Electronic Engineering, King’s College, London, U.K. His current work involves the physics and technology of III–V heterojunction devices and circuits for microwave and optoelectronic applications. He is a Reader in Microwave Photonics and Consulting Engineer in the Department of Electronic Engineering, King’s College, and is also the Head of Microwave Circuits and Devices Research Group. He has contributed three book chapters and published 40 refereed journal papers and 50 conference papers. Dr. Rezazadeh is the Chairman of IEEE UKRI MTT/ED/AP/LEO Joint Chapter and the Chairman of IEE Professional Group E3 (Microelectronics and Semiconductor Devices). He also serves on the Technical Committees of several international conferences. In 1993, he founded the IEEE International Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications (EDMO).

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 6, JUNE 1999

Andy P. Knights gained the Ph.D. degree in experimental physics from The University of East Anglia, Norwich, U.K., in October 1994. After a period as a Post-Doctoral Research Fellow in the Department of Physics and Astronomy at the University of Western Ontario, London, Ont., Canada, he joined the EPSRC Central Facility for Ion Beam Applications, the University of Surrey, Surrey, U.K., in October 1996. In addition to ion implantation, he has research interests in the study of semiconductor point defects.

Christopher C. Button was born in Ipswich, Suffolk, U.K., in 1957. He was sponsored by British Telecom Research Laboratories (BTRL), Martlesham, and received the B.A. degree from the Open University, U.K., in 1988. In 1976, he joined the research laboratories of the Delta Metals Group, Ipswich, then moved on to join BTRL in 1981. Since 1988, he has been with the EPSRC Central Facility for III–V Semiconductors, The University of Sheffield, Sheffield, U.K., where he is now a Research Fellow, responsible for MOCVD growth of phosphorus-containing compounds, and is currently setting up a capability for the growth of GaN and related compounds.