IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
1897
Discontinuous PWM Modulation Strategy With Circuit-Level Decoupling Concept of Three-Level Neutral-Point-Clamped (NPC) Inverter Zhe Zhang, Member, IEEE, Ole C. Thomsen, Member, IEEE, and Michael A. E. Andersen, Member, IEEE
Abstract—A new pulse width modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is developed and presented in this paper. The proposed PWM scheme not only takes advantage of the special properties available in NPC inverters, but also reduces the switching loss of the inverter along with an inherent neutral point (NP) voltage control. Based on a circuit-level decoupling concept, the NPC inverter can be decoupled into two three-level Buck converters in every defined operating section, and thereby the controller design can be simplified. The salient features of the proposed scheme, as compared with the existing carrier-based DPWM strategies, are: 1) its reduced computational processing time, 2) its capability to balance the dc-link voltage without any additional control, and 3) its reduced complexity, e.g., only one carrier wave needed for pulse width modulating. Same as a space-vector modulation, the maximum modulation index, 1.1547, can be attainable by the proposed scheme. Moreover, compared to conventional continuous sinusoidal PWM, using this technique proposed here, the switching losses of the devices can be reduced by one third. In order to explain the operation of this topology properly, the decoupling principle including the driving signal synthesis and the NP potential variation are analyzed in detail in this paper. Finally, the viability and performance of the proposed modulation scheme are shown through simulation and experimental results in a laboratory prototype. Index Terms—Circuit-level decoupling, modulation strategy, multilevel converter, voltage-source inverter.
I. I NTRODUCTION
T
HE neutral-point-clamped (NPC) inverter [1] is the most extensively applied multilevel converter topology at present [2]–[6]. A three-level NPC inverter is illustrated as shown in Fig. 1, which is able to output five-level-step-shaped line to line voltage (three-level-step-shaped phase voltage) without transformers or reactors, so that it can reduce harmonics in both of the output voltage and current. The major benefit of this configuration is that, while there are twice as many switches as in the two-level inverter, each of the switches must block only one-half of the dc-link voltage (as is also the case for six center-tapped clamp diodes). However, the NPC inverter has some drawbacks, such as additional clamping diodes, compliManuscript received October 27, 2011; revised May 18, 2012 and September 27, 2012; accepted October 22, 2012. Date of publication November 15, 2012; date of current version January 30, 2013. The authors are with the Department of Electrical Engineering, Technical University of Denmark, 2800 Kgs. Lyngby, Denmark (e-mail:
[email protected]. dk;
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2227901
Fig. 1. Topology of a three-level NPC inverter.
cated pulse width modulation (PWM) switching pattern design, and possible deviation of neutral point (NP) voltage [7], [8]. In addition, since the NPC inverter is mostly used for mediumor high-power applications, the minimization of the switching loss is such a relevant issue. As to the modulation strategies, three popular modulation techniques for NPC inverters such as carrier-based PWM [9]–[11], space-vector modulation (SVM) [12]–[17], and selective harmonic elimination (SHE) [18]–[20] have been used widely in practice. The SHE method shows advantage for high-power applications due to having a small number of switching actions. The other two PWM techniques are commonly used in various applications because of their high PWM qualities. In order to realize the proper operation of the topology and overcome the problem of voltage unbalance on dc capacitors, a great deal of research has been done to balance the capacitor voltages using different strategies [7], [8], [12], [21]–[23]. Most of these techniques can resolve the NP voltage balancing problem, but at same time will increase the switching loss that is not favorable for medium/high-voltage applications. Typically, when a carrier-based PWM is utilized, the zero-sequence voltage is the only freedom degree which can be employed to maintain balancing. In [11], a zero sequence voltage is injected in the discontinuously sinusoidal reference signals to carry out the voltage balancing task. A fast-processing modulation strategy was investigated in [21], [22], which cannot only balance the averaged NP voltage but also completely eliminate the lowfrequency NP voltage oscillation, even though the switching frequencies of the devices are higher. A theoretical optimum algorithm employing interpolation method to calculate the
0278-0046/$31.00 © 2012 IEEE
1898
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
appropriate zero-sequence voltage was introduced in [23], and a comprehensive study of NP self-balancing effect for NPC inverters was given in [24]. For the purpose of reducing switching losses, for two-level inverters, the discontinuous PWM (DPWM) methods have been studied for years [9]. DPWM involves locking each phase leg to a fixed dc voltage level for 120◦ per fundamental cycle (using one or more subintervals) while the remaining two-phase legs are pulse width modulated. The DPWM modulation strategies for two-level inverters can be extended and utilized in threelevel or multilevel inverters. While, so far, only few research results on DPWM modulations for the multilevel inverters which have NPC, active NPC, or flying capacitor structures have been reported in the published literatures, because compared to the continuous ones, generally, discontinuous modulations not only have higher total harmonic distortion (THD) of output voltage that seems against to the purpose of utilizing the multilevel inverter, but also these modulations cannot directly be adopted into a three-phase four-wire system. Furthermore, some issues such as unbalanced switching load and dc-link voltage ripple must be studied even further when a multilevel inverter is implemented with a DPWM modulation scheme. As for the NPC inverters, in order to reduce the NP voltage fluctuations without increasing the switching loss, a DPWM method with three different switching patterns was proposed in [25]. In [26], a DPWM algorithm to minimize switching loss with the consideration on variable load currents for a five-level NPC inverter was introduced. In [27], [28] to simply the controller design, a circuit-level decoupling concept was proposed for a three-phase two-level voltage-source inverter, and the corresponding PWM strategy is basically similar to the Class II SVM reviewed in [29]. With the circuit-level decoupling concept [30], a new modulation strategy for the three-level NPC inverters is introduced in this paper. A theoretical basis for the proposed strategy is developed, and also the NP voltage oscillation is investigated in depth. The salient features of the proposed strategy are the following. • The NPC inverter can be decoupled as two three-level Buck converters (TLBCs) in every 60◦ operating section of the fundamental cycle, which leads to a simpler design of closed-loop controllers. • It provides inherent capability to maintain voltage balancing between the dc capacitors without any requirement of additional control effort. • As four of its 12 switches are not operated at switching frequency at any instant, the switching losses are reduced by one third. • Only one carrier wave is needed. This paper is organized as: following the introduction, the operation principle of the circuit-level decoupling method utilized in the three-level NPC inverter is introduced, and, based on that, a new modulation strategy is developed and implemented in Section II; with the proposed PWM scheme, the NP voltage variation of the NPC inverter is explained in Section III; the simulation and experimental results from a laboratory prototype are presented in Section IV; finally, in Section V, this paper is concluded by highlighting the advantages of the proposed PWM scheme.
Fig. 2.
Three-phase output voltage.
II. O PERATION P RINCIPLE OF THE P ROPOSED M ODULATION S TRATEGY In Fig. 1, a typical power stage of the three-level NPC inverter is presented. The inverter leg is composed of four active switches Ti1 ∼ Ti4 , where i = a, b, and c. Switches Ti1 and Ti3 on each leg are complementary, which means that when switch Ti1 is on, always Ti3 is off and vice versa. Switches Ti2 and Ti4 are the other complementary switching pair. Diodes Di1 and Di2 are to clamp the output terminal potential to the NP potential. The dc bus voltage is split into three levels by two dc bus capacitors C1 and C2 which produce a NP Z. Each capacitor has E volts, and each voltage stress will be limited to one capacitor level through clamping diodes. With a finite value of C1 and C2 , the neutral-point voltage deviation is caused by the neutral current iZ that will be discussed further in the later section. A. Circuit-Level Decoupling Scheme As illustrated in Fig. 2, a fundamental cycle can be divided into six regions equally. By inspecting the three-phase voltage waveforms in each region, one common fact is found that two-phase voltages are always positive and the other one is negative in regions I (0◦ –60◦ ), III (120◦ –180◦ ), and V (240◦ –300◦ ), whereas the opposite can be found in regions II (60◦ –120◦ ), IV (180◦ –240◦ ), and VI (300◦ –360◦ ). This fact leads to the thought of pulse width modulating the switches in the phases with the same signs and, on the other hand, keeping the switches in the other phase steady for the entire region or the partial region. Hence, in regions I, III, and V, where the same pattern exists, the following modulation scheme is applied. 1) The switches Ti3 and Ti4 (i = a, b, and c) in the phase with lowest voltage are always turned on, and the corresponding switches Ti1 and Ti2 in the same phase are always turned off; 2) The switches in the other two phases are controlled by SPWM scheme. With this treatment, Fig. 1 is equivalent to Fig. 3(a) in region I, which can be further simplified and reorganized as shown Fig. 3(b), where STLp and STLn surrounded by dotted lines are the equivalent single-pole-triple-throw switches for the half bridge of each phase. The same equivalent circuits are also applicable to regions III and V.
ZHANG et al.: DISCONTINUOUS PWM MODULATION STRATEGY FOR A THREE-LEVEL NPC INVERTER
Fig. 3.
Fig. 4. Equivalent circuit of the NPC inverter in region II (60◦ ∼ 120◦ ).
Equivalent circuit of the NPC inverter in region I (0◦ ∼ 60◦ ).
While in the regions II, IV, and VI, the voltage waveforms in Fig. 2 have another pattern, and accordingly the following modulation method is adopted: 1) The switches Ti1 and Ti2 (i = a, b, c) in the phase with highest voltage are always turned on, and the corresponding Ti3 and Ti4 in the same phase are always turned off; 2) The switches in the other two phases are controlled by SPWM scheme. With this treatment, in region II, the NPC inverter in Fig. 1 is equivalent to Fig. 4(a), and hereby the simplified circuit with the model of the single-pole-triple-throw switch is obtained and shown in Fig. 4(b). Similarly, the same equivalent circuits can be applicable to regions IV and VI as well.
where TonP,m(m=p,n) is the time of STLm(m=p,n) connected with the switch node P , and Ts is the switching period. In order to obtain the steady-state transfer functions from duty cycles to input/output voltages, the volt-second balance principle is applied on all the inductors in one switching cycle, and the following equations can be derived: (2E − vp ) · dp + (E − vp ) · (1 − dp ) = 0 (2E − vn ) · dn + (E − vn ) · (1 − dn ) = 0. Solving (2) and (3), the duty cycles are obtained as v −E dp = pE = VABE−E dn = vnE−E = VCBE−E .
(2) (3)
(4)
On the contrary, when vm(m=p,n) < E, the corresponding switch STLm(m=p,n) is switched between the switching nodes Z and N with a duty cycle defined as
B. Operation Principle of the Decoupled Converters For a further analysis on the operation principles, the following assumptions are made first: LA = LB = LC , CA = CB = CC and the switching frequency is much higher than the fundamental frequency. Usually, these assumptions are true in three-phase voltage generation applications. The detailed analysis is performed on regions I and II, with the equivalent circuits shown in Figs. 3 and 4, while similar derivation can be extended to all other regions. In region I, it can be seen in Fig. 3 that vp = VAB and vn = VCB . Hereby, when vm(m=p,n) ≥ E, the corresponding switch STLm(m=p,n) is switched between the switching nodes P and Z with a duty cycle defined as dm(m=p,n) = TonP,m(m=p,n) /Ts
1899
(1)
dm(m=p,n) = TonZ,m(m=p,n) /Ts
(5)
where TonZ,m(m=p,n) is the time of STLm(m=p,n) connected with the switch node Z. According to the inductor volt-second balancing in one switching period, the following equations can be derived: (E − vp ) · dp + (0 − vp ) · (1 − dp ) = 0 (E − vn ) · dn + (0 − vn ) · (1 − dn ) = 0.
(6) (7)
Correspondingly, the duty cycles in this case are calculated v dp = Ep = VAB E (8) dn = vEn = VCB E .
1900
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
Fig. 5. Equivalent circuit and corresponding waveforms for voltage VAB and VBA , respectively. (a) In region I and (b) in region II.
Apparently, (4) and (8) constitute the relationship of two TLBCs and to make this conclusion even clearer, the equivalent circuit and typical waveforms for the output voltage VAB are plotted in Fig. 5(a). In region II, as shown in Fig. 4, the active line voltages and phase voltage are VBA (−vp ) and VCA (−vn ), respectively. Accordingly, if −vm(m=p,n) ≤ −E, the equivalent switch STLm(m=p,n) will be switched between the terminals N and Z with the duty cycle defined dm(m=p,n) = TonN,m(m=p,n) /Ts
(9)
where TonN,m(m=p,n) is the time of STLm(m=p,n) connecting with the switch node N . Otherwise, if −Vm(m=p,n) > −E, STLm(m=p,n) will be switched between the terminals Z and P with the duty cycle dm(m=p,n) = TonZ,m(m=p,n) /Ts . In order to obtain the steady-
TABLE I S YNTHESIS OF THE R EFERENCE S IGNALS
state transfer functions from duty cycles to input/output voltages, the volt-second balance principle is adopted again, the same duty cycle descriptions as in region I can be obtained below v −E +E dp = VBA = VABE−E = pE −E (10) +E dn = VCA = VACE−E = vnE−E −E vp BA = VAB dp = V−E E = E (11) vn CA dn = V−E = VAC E = E .
ZHANG et al.: DISCONTINUOUS PWM MODULATION STRATEGY FOR A THREE-LEVEL NPC INVERTER
Fig. 6.
1901
Equivalent three-level Buck converters according to VAB . (a) A-TLBC in region I, (b) C-TLBC in region II, and (c) integrated converter.
It is clear that in region II the NPC inverter can also be decoupled into two TLBCs. As an example, the equivalent circuit of phase leg b and the typical waveforms for the output voltage VBA (−vp ) are plotted in Fig. 5(b) to present the decoupling effect. Applying the same analysis to one entire fundamental cycle, the reference signals vp and vn in every operating region are listed in Table I. By inspecting the reference signals, in Table I, it can be seen that in the adjacent two regions, the control signals are always same, for instance, in regions I and II, the line voltage VAB is used as the signal vp . Then, as for VAB , in region I and II, the equivalent circuits shown in Fig. 5 can be simplified even further. The so-called anode TLBC (A-TLBC) and cathode TLBC (C-TLBC) can be obtained in Fig. 6(a) and (b), respectively. These two TLBCs can be combined into one converter with common input dividing capacitors, as shown in Fig. 6(c). Thus, as the conclusions drawn in [31], by rotating the energy provision burden between both capacitors through the adjacent operating regions, the two dividing capacitors will provide, on average, an equal amount of energy to the load, which allows them to maintain a balance voltage over time, thereby the voltage of the dividing capacitors can be balanced naturally without any additional control. In summary, the completely decoupled TLBC representations of the NPC inverter can be derived in every 60◦ region. Also, in the adjacent regions, the integrated three-level converters can be obtained from the circuit-level point of view. The controller design and the selection of output filter parameters L and C can hence follow the same rules as those for three-level dc-dc converters. C. Implementation of the Proposed Modulation Strategy Fig. 7 shows the proposed modulator for the NPC inverter, which is responsible to determine the decouple logic and distribute the corresponding driving signals. It consists of a region selector, a carrier signal selector, a PWM generator, and a gate signal distributor. If a feedback controller is designed, the outputs of the controller (current and/or voltage signals) can be connected into the carrier signal selector. The region selector
Fig. 7. Block diagram of the proposed PWM modulator.
determines the active working region, as shown in Fig. 2, by detecting the zero-crossing point of the expected output AC voltages. The carrier signal selector selects the active control signals (modulation references), which are represented by CONp and CONn . Moreover, it also selects the switching position signal E + or E − , which indicates that half dc bus voltage E is larger or smaller than the corresponding output line voltage. The selected control and reference signals are processed by the PWM generator to generate the duty-ratio signals. The gate signal distributor sends these duty-ratio signals to the gate driver circuits in order to trigger the appropriate switches Ta1 ∼ Tc4 according to the outputs from the region selector and the carrier signal selector. In Table II, the selected line voltages that act as outputs of the equivalent decoupled circuits in every region are listed, which also depends on the switching-position signals; the assignment of duty cycles of the active switches, i.e., dp , dp , dn , dn is listed in Table II as well; dt , which equals 1, is allocated to the switch which is always ON in the inactive phase. According to the synthesis of PWM signal generation in Table II, the algorithm of modulator is simple, and the modulator proposed here can be even implemented by a simple logic with analog and gate circuits, so it can be processed quickly as compared to conventional 2-D or 3-D SVM [32]. Due to the decoupling effect, regarding closed-loop controller design, the methods for three-level dc-dc converters can be utilized easily to implement output voltage control of the NPC inverter,
1902
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
TABLE II S YNTHESIS OF THE D RIVING S IGNALS
Fig. 8.
Modulation signals of the switches Ta1 and Ta2 .
where 1 − vmax |vmax | ≥ |vmin | vz = 1 + vmin |vmax | < |v min | vmax = max(vAO , vBO , vCO ) and vmin = min(vAO , vBO , vCO ).
and thereby a high-speed digital signal processing (DSP) accompanied with a high sampling-rate A/D converter to achieve coordinate transformation is no more required essentially. From (4) and (8), it can be found that the modulation references are always line to line voltages. At the limit, we have dp = 1 or dn = 1, which means the maximal output line to line voltage is to be 2E. The maximum modulation index in a linearmodulation range is 2·E 2 vl−l mmax = √ =√ = √ = 1.1547. (12) 3·E 3·E 3 Equation (12) shows that the maximum achievable modulation index for the linear-modulation mode obtained here is same with those by SVM or other carrier-based PWM strategies with proper zero-sequence signal injection. In this paper, m, the modulation index, is expressed by normalizing with respect to this mmax . Considering the proposed PWM modulation of the NPC inverter shown in Fig. 1, a three-phase output voltage can be expressed vAO = m sin(ωt) + v0 2 vBO = m sin ωt − π + v0 3 2 vCO = m sin ωt + π + v0 3
(13)
where v0 is the zero sequence output voltage of the NPC inverter, and here the three phase voltages are normalized with respect to half dc bus voltage E. The reference signals of switches Ti1 and Ti2 (i = a, b, c) can be derived viO − vz , if viO ≥ vz (14) vref,T i1 = 0, if viO < vz 1, if viO ≥ vz vref,T i2 = (15) 1 + viO − vz , if viO < vz
In Fig. 8, the modulation signal of the switches Ta1 and Ta2 in phase leg a, can be illustrated under m = 0.8. It is clear that 1) line to line voltages are used as modulation reference; 2) there are no switching actions of Ta1 and Ta2 in regions II and V completely; 3) modulation signals are within the range [0, 1], so all the references can share one common carrier wave. Hereby, the modulation signals for the switches located in phase legs b and c can be obtained by ±120◦ phase-shifting, respectively. Fig. 9 shows variation of the modulation reference of Ta1 as the modulation index m changes. While complicated in shape, since the equations describing the functions are relatively simple sections of sinusoids, they can be readily implemented in real-time digital form. As shown in Fig. 10, there is linear relation of the output peak voltage value and modulation index. Furthermore, we can find that the peak value of the line voltage can reach to 1, which is normalized to 2E as aforementioned, and also the phase voltage is 1.732 times smaller than the line voltage. III. N EUTRAL P OTENTIAL VARIATION A NALYSIS The main technical challenge in any application of the NPC inverter is to maintain the voltages of the two dc-side capacitors equal and at a pre-specified level. The modulation strategy must have the function to achieve voltage balancing between the dc-side capacitors, if there is no external control utilized. The modulation algorithm proposed here can enable the locally averaged NP current to be zero, and hereby the NP voltage balancing and low-frequency NP voltage oscillation is investigated in the following. According to three-phase output voltage in (13) as well as assuming that the power factor angle is θ which can be positive, negative, or zero with respect to different load conditions, the uniform three-phase ac-side current can be given √ ia = 2I sin(ωt − θ) √ 2 ib = 2I sin ωt − θ − π 3 √ 2 ic = 2I sin ωt − θ + π (16) 3
ZHANG et al.: DISCONTINUOUS PWM MODULATION STRATEGY FOR A THREE-LEVEL NPC INVERTER
1903
The normalized neutral potential variation with respect to the center potential of dc-link is calculated be the following equation: IR (18) iz dt. vz = − 2CE The analysis can be performed in six sections shown in Fig. 2. In Section I, the switches in a phase are controlled by dp and dp , and the switches in c phase are controlled by dn and dn . While, the output of phase leg b cannot be connected into the NP in this region. By substituting (4) and (8) into (17), the average neutral current is derived iz = (1 − dp ) + dp · ia + 0 · ib + ((1 − dn ) + dn ) · ic = [1 − (vAO − vBO − 1) + vAO − vBO ] · ia + [1 − (vCO − vBO − 1) + vCO − vBO ] · ic = 2(ia + ic ) √ π
. (19) = 2 2I sin ϕ − θ + 3 Hence, in this region, the normalized NP potential vz is calculated by √ 2IR I cos ϕ − θ + π3 vz = − . (20) ωCE The average neutral current in Section II is obtained similarly as Fig. 9. Modulation reference signals according to modulation indices. (a) Modulation signal of Ta1 , and (b) modulation signal of Ta2 .
iz = 0 · ia + (1 − dp ) + dp · ib + ((1 − dn ) + dn ) · ic = 2(ib √ + ic ) (21) = − 2 2I sin(ϕ − θ). The equation shifts the angle of ϕ by π/3 ϕ = ϕ +
π . 3
(22)
Substituting the above equation into (21) derives as follows: √ π
. (23) iz = −2 2I sin ϕ − θ + 3 Fig. 10. Output voltage versus modulation index: VAB−peak and VAO−peak .
where three phase currents are expressed by normalizing with respect to the rated current IR . When any phase leg is clamped to the NP, the corresponding phase current will be injected into or drawn out from this point, so that the neutral potential drifts away from the center potential of the dc-link. Neglecting the switching frequency ripple, the mean value of the neutral current can be derived by product of the phase current and the clamped time ratio during a modulation period, as calculated by iz = da0 · ia + db0 · ib + dc0 · ic
(17)
where the di0 , (i = a, b, c) is the time ratio of the neutral-pointclamped phase output.
Equations (19) and (23) have the same form except for a different sign on the right-hand side. In operating regions III to VI, by using the same method as in regions I, II, the same descriptions on the neutral current in regions III, V and in regions IV, VI, can be derived, respectively. Finally, through synthesizing and comparing the results, it indicates as follows: 1) There is no dc component in NP current that means the zero sequence voltage does not move away the NP potential from the central potential of the dc-link; 2) The NP potential varies at three times as high as the output fundamental frequency, because the sign of the neutral current changes every 60◦ . The analysis and explanation of a mechanism to further reduce the calculated ac voltage ripple by control redundancies and/or modifying the duty cycle are out of range of this paper and will be discussed in the future.
1904
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
Fig. 11. Simulation waveforms with m = 0.8, Vdc = 400 V: (a) line-to-dc midpoint voltage of leg a, vaZ and output line to load-neutral voltage vAO , (b) line voltage, vab , switched waveform and output waveform vAB . TABLE III PARAMETERS OF THE E XPERIMENT
IV. S IMULATION AND E XPERIMENTAL R ESULTS The proposed modulation technique has been verified by simulation and experiment. Fig. 11 shows a simulation example, where the converter operates over an R wye-connected load and the modulation index is 0.8 and Vdc = 400 VDC by MATLAB/SIMULINK in which output three phase and line voltages are illustrated. In the experiment, the modulation technique was programmed into a TMS320F28335 DSP eZdsp board with the inverter parameters listed in Table III. Fig. 12 shows the experimental waveforms obtained by using proposed modulation strategy, when the prototype is tested with balanced resistive load and the modulation index is 0.8. The output phase voltage, the output line voltage, the threephase sinusoidal output voltages, and currents are shown in Fig. 12(a)–(d), respectively. It can be seen that there are no switching actions in phase leg a during the operating regions II and IV. The results match those reported in the theoretical analysis section which underlines the effectiveness of the proposed modulation strategy. Fig. 13 shows the dynamic balancing process by the simulation in which the initial voltages on the dc-link capacitors are unbalanced such as VC1 = 250 V and VC2 = 150 V, where the dashed lines are to illustrate the averaged voltages across the capacitors. Fig. 14 shows the experimental results of dclink voltages vC1 and vC2 as well as the voltage ripple in
Fig. 12. Experimental results with balanced resistive load (a) phase leg a voltage vaZ and vAO [100 V/div], (b) ouput line voltage vab and vAB [100 V/div], (c) output three-phase voltages vAO , vBO , and vCO [50 V/div]. (Time base: 5 ms/div) and (d) phase voltage vAO [50 V/div] and three-phase currents [2 A/div] (Time base: 10 ms/div).
Fig. 13.
Voltage across the dc-link capacitors.
the subwindow which has the frequency 150 Hz under AC coupling. Through the FFT analysis, the harmonics spectra of the switched phase- and line-voltage waveforms with m = 0.8 are shown in Fig. 15. Comparison of these figures indicates that with the proposed modulation, the phase-voltage has its triplen
ZHANG et al.: DISCONTINUOUS PWM MODULATION STRATEGY FOR A THREE-LEVEL NPC INVERTER
Fig. 14. Waveforms of voltage across the dc capacitors C1 and C2 and AC voltage ripple (5 ms/div).
1905
Fig. 16. Voltage WTHD factors for switched output voltages as a function of modulation index: (a) line voltage vab and (b) phase voltage vaZ .
V. C ONCLUSION This paper has proposed a modulation strategy based on circuit-level decoupling principle for a three-phase three-level NPC inverter. This method can be used in the NPC inverters for the industrial applications, such as voltage generation inverters in renewable energy systems and AC motor drive systems, where high control performance and low switching loss are required. Due to this proposed modulation strategy, the inverter can be decoupled into two TLBCs in every 60◦ region. The main features of this strategy, as compared with other strategies, are its simplicity for analog or digital implementation and the lower switching power losses. The capabilities of the proposed strategy which are concluded by simulation and experimental results can be summarized as:
Fig. 15. Harmonic spectra of the output switched waveforms: (a) line to dc midpoint voltage of the leg a, vaZ and (b) line switched voltage vab .
harmonics, whereas the line-voltage has no triplen harmonic components. This will apparently result in lower harmonic contents in the line voltage, as it can be observed. The weighted THD (WTHD) method [6] is widely used to indicate the quantity of harmonics contents in the output waveforms. The definition of voltage WTHD in an inverter circuit is given WTHD =
∞ n=2
V1
Vn 2 n
(24)
where Vn is peak value of nth-order harmonic voltage. The WTHD factors of the switched line voltage and phase voltage as a function of modulation index have been calculated and plotted (up to 49th-order harmonics included). Due to the triplen harmonics, the phase voltage has much higher WTHD than the line voltage as shown in Fig. 16.
1) Fast-processing ability: the structure of modulator is simple, and the algorithm can be implemented easily, and also only one carrier signal is needed; 2) Average NP voltage balancing ability: it can keep the NP voltage at half of the dc-link voltage without any feedback or feedforward control; 3) Low switching losses: The switching loss is reduced significantly by not switching the phases which have the highest or lowest voltages. 4) Higher compatibility: The proposed simple and fastprocessing PWM modulation strategy can be extended and utilized in three-phase four-leg NPC inverter for three-phase four-wire systems, as well as in other multilevel (five-level, seven-level) inverters or active PWM rectifiers. R EFERENCES [1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. 1A-17, no. 5, pp. 518–523, Sep.–Oct. 1981. [2] J. Rodríguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey on neutral-point-clamped inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2219–2230, Jul. 2010. [3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010. [4] A. Sanchez-Ruiz, M. Mazuela, S. Alvarez, G. Abad, and I. Baraia, “Medium voltage-high power converter topologies comparison procedure, for a 6.6 kV drive application using 4.5 kV IGBT modules,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1462–1476, Mar. 2012.
1906
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
[5] M. Liserre, R. Cárdenas-Dobson, M. Molinas, and J. Rodriguez, “Overview of multi-MW wind turbines and wind parks,” IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1081–1095, Apr. 2011. [6] J. D. Barros, J. F. A. Silva, and E. G. A. Jesus, “Fast-predictive optimal control of NPC multilevel converters,” IEEE Trans. Ind. Electron., vol. 60, no. 2, pp. 619–627, Feb. 2013. [7] R. Stala, “Application of balancing circuit for DC-link voltages balance in a single-phase diode-clamped inverter with two three-level legs,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4185–4195, Sep. 2011. [8] J. Shen, S. Schroeder, R. Roesner, and S. El-Barbari, “A comprehensive study of neutral point self-balancing effect in neutral-point-clamped threelevel inverters,” IEEE Trans. Power Electron., vol. 26, no. 11, pp. 3084– 3095, Nov. 2011. [9] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters. New York: Wiley, 2003. [10] J.-H. Kim, S.-K. Sul, and P. N. Enjeti, “A carrier-based PWM method with optimal switching sequence for a multilevel four-leg voltagesource inverter,” IEEE Trans. Ind. Appl., vol. 44, no. 4, pp. 1239–1248, Jul./Aug. 2008. [11] J. Pou, J. Zaragoza, S. Ceballos, M. Saeedifard, and D. Borojevic, “A carrier-based PWM strategy with zero-sequence voltage injection for a three-level neutral-point-clamped converter,” IEEE Trans. Power Electron., vol. 27, no. 2, pp. 642–651, Feb. 2012. [12] W. Song, X. Feng, and K. M. Smedley, “A carrier-based PWM strategy with the offset voltage injection for single-phase three-level neutralpoint-clamped converters,” IEEE Trans. Power Electron., vol. 28, no. 3, pp. 1083–1095, Mar. 2013. [13] A. Mehrizi-Sani and S. Filizadeh, “An optimized space vector modulation sequence for improved harmonic performance,” IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 2894–2903, Aug. 2009. [14] T. Ghennam, E. M. Berkouk, and B. Francois, “A novel space-vector current control based on circular hysteresis areas of a three-phase neutralpoint-clamped inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2669–2678, Aug. 2010. [15] M. C. Cavalcanti, M. A. Farias, K. C. Oliveira, F. A. S. Neves, and L. J. Afonso, “Eliminating leakage currents in neutral point clamped inverters for photovoltaic systems,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 435–443, Jan. 2012. [16] S. Das and G. Narayanan, “Novel switching sequences for a space-vectormodulated three-level inverter,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1477–1487, Mar. 2012. [17] A. R. Beig, “Synchronized SVPWM algorithm for the overmodulation region of a low switching frequency medium-voltage three-level VSI,” IEEE Trans. Ind. Electron., vol. 59, no. 12, pp. 4545–4554, Dec. 2012. [18] S. Sirisukprasert, J.-S. Lai, and T.-H. Liu, “Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 875–881, Aug. 2002. [19] J. Napoles, J. I. Leon, R. Portillo, L. G. Franquelo, and M. A. Aguirre, “Selective harmonic mitigation technique for high-power converters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2315–2323, Jul. 2010. [20] Y. Zhang, Z. Zhao, and J. Zhu, “A hybrid PWM applied to highpower three-level inverter-fed induction-motor drives,” IEEE Trans. Ind. Electron., vol. 58, no. 8, pp. 3409–3420, Aug. 2011. [21] J. Pou, J. Zaragoza, P. Rodriguez, S. Ceballos, V. Sala, R. Burgos, and D. Boroyevich, “Fast-processing modulation strategy for the neutralpoint-clamped converter with total elimination of the low-frequency voltage oscillations in the neutral point,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 2288–2294, Aug. 2007. [22] J. Zaragoza, J. Pou, S. Ceballos, E. Robles, C. Jaen, and M. Corbalan, “Voltage-balance compensator for a carrier-based modulation in the neutral-point-clamped converter,” IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 305–314, Feb. 2009. [23] C. Wang and Y. Li, “Analysis and calculation of zero-sequence voltage considering neutral-point potential balancing in three-level NPC converters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2262–2271, Jul. 2010. [24] N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters,” IEEE Trans. Power Electron., vol. 15, no. 2, pp. 242–249, Mar. 2000. [25] L. Ben-Brahim, “A discontinuous PWM method for balancing the neutral point voltage in three-level inverter-fed variable frequency drives,” IEEE Trans. Energy Convers., vol. 23, no. 4, pp. 1057–1063, Dec. 2008. [26] N.-V. Nguyen, B.-X. Nguyen, and H.-H. Lee, “An optimized discontinuous PWM method to minimize switching loss for multilevel inverters,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 3958–3966, Sep. 2011.
[27] L. Li, T. Jin, and K. M. Smedley, “A new analog controller for three-phase voltage generation inverter,” IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2894–2902, Aug. 2008. [28] L. Li and K. M. Smedley, “A new analog controller for three-phase fourwire voltage generation inverter,” IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1711–1721, Jul. 2009. [29] R. Zhang, “High performance power converter system for nonlinear and unbalanced load/source,” Ph.D. dissertation, Elect. Comput. Eng., Virginia Polytech. Inst. State Univ., Blacksburg, VA, Nov. 1998. [30] Z. Zhang, O. C. Thomsen, and M. A. E. Andersen, “The circuit-level decoupling modulation strategy for three-level neutral-point-clamped (TL-NPC) inverter,” in Proc. 14th EPE, Sep. 2011, pp. 1–10. [31] X. Ruan, B. Li, Q. Chen, S.-C. Tan, and C. K. Tse, “Fundamental considerations of three-level DC-DC converters: Topologies, analysis, and control,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3733– 3743, Dec. 2008. [32] J. I. Leon, S. Vazquez, R. Portillo, L. G. Franquelo, J. M. Carrasco, P. W. Wheeler, and A. J. Watson, “Three-dimensional feedforward space vector modulation applied to multilevel diode-clamped converters,” IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 101–109, Jan. 2008.
Zhe Zhang (S’07–M’11) received the B.S. and M.S. degrees in electrical engineering from Yanshan University, Qinhuangdao, China, in 2002 and 2005, respectively, and the Ph.D. degree from the Technical University of Denmark, Kgs. Lyngby, Denmark, in 2010. From 2005 to 2007, he was an Assistant Professor and Lecturer at Yanshan University. From June 2010 to August 2010, he was with the University of California, Irvine, as a Visiting Scholar. After receiving the Ph.D. degree, he became a Postdoctoral Researcher at the Technical University of Denmark from January 2011 to September 2011. Currently, he is an Assistant Professor of power electronics at the Technical University of Denmark. His current research interests include dc/dc converters, multilevel inverters for fuel-cell-powered uninterruptible power supplies, and hybrid electric vehicles.
Ole C. Thomsen (M’06) received the B.S.E.E. degree in electronics from the Engineering Academy of Denmark, Kgs. Lyngby, Denmark, in 1970. He was as an RF R&D Engineer at Skandinavisk Teleindustri A/S, Ballerup, Denmark, from 1970 to 1976. From 1976 to 1980, he was the Power Electronic Project Manager in the Space Department at Christian Rovsing A/S. In 1980, he founded Powerlab A/S, operating within R&D and manufacturing of professional power electronics and served as a General Manager until 2004. Since 2005, he has been with the Technical University of Denmark, Kgs. Lyngby, where he is currently an Associate Professor. His main research interests include switch-mode power supplies, power factor correction, and electromagnetic compatibility.
Michael A. E. Andersen (M’88) received the M.Sc.E.E. and Ph.D. degrees in power electronics from the Technical University of Denmark, Kgs. Lyngby, Denmark, in 1987 and 1990, respectively. Currently, he is a Professor of power electronics at the Technical University of Denmark. Since 2009, he has been a Deputy Director in the Department of Electrical Engineering. He is the author or coauthor of more than 100 papers. His research interests include switch-mode power supplies, piezoelectric transformers, power factor correction, and switchmode audio power amplifiers.
