Discrete-time control for DC–AC converters based on ...

www.ietdl.org Published in IET Power Electronics Received on 13th September 2011 Revised on 24th February 2012 doi: 10.1049/iet-pel.2011.0347

ISSN 1755-4535

Discrete-time control for DC – AC converters based on sliding mode design L. Schirone F. Celani M. Macellari DIAEE, Sapienza Universita` di Roma, Via Salaria 851-00138, Rome, Italy E-mail: [email protected]

Abstract: A discrete-time linear state-feedback controller with feedforward compensation is presented for the design of voltage source DC – AC converters. The proposed algorithm is based on duty-ratio control and is obtained by modifying an existing sliding mode design method. It does not introduce chattering in the output waveforms, and its robustness with respect to parameter variations is enhanced by introducing an integral action. An intuitive approach for the selection of the controller parameters is developed. The design criteria are illustrated with reference to a laboratory prototype by means of various experiments, intended to test both stationary and dynamic performance.

1

Introduction

Several applications require generation of an AC waveform from a DC source by means of static inverters, for example, motor drives, uninterruptible power supplies, grid-connected photovoltaic systems and stand-alone power buses. They should be designed to operate within stringent environment, compliant with rigorous specifications about low total harmonic distortion (THD) over a wide range of line voltages even in the presence of severe load unbalances and non-linearities. Stable output frequency, high efficiency, high power density and high reliability are expected too. The output voltage of a switching converter can be forced to track a sinusoidal reference by means of different pulse width modulation (PWM) methods [1, 2]. Analogue design was the main option for many years [3, 4], whereas digital techniques, derived from the control methodologies proposed for DC – DC switching converters ([5] and references therein), have been introduced later [1, 6]. Among the available control methods, sliding mode (SM) control, originally proposed for generic variable structure systems [7], has been applied successfully to DC – AC converters [8 – 10]. SM control is known to have advantages such as simple implementation, robustness against parameter uncertainties and external disturbances. However, classical continuous-time SM controllers are affected by some disadvantages such as the variable and theoretically unlimited switching frequency. Thus, several methods have been determined to limit the switching frequency; in [11] the limitation is obtained by introducing a second-order filter in the feedback loop. Alternatively, such limitation is intrinsically achieved by using a discrete-time SM controller (see [12]). However, setting bounds on the switching frequency leads to obtaining state trajectories as the Type I curve in Fig. 1 (see, e.g. [13 –15]) and consequently IET Power Electron., pp. 1– 8 doi: 10.1049/iet-pel.2011.0347

chattering is introduced in the controlled variable. Chattering removal is particularly beneficial for the discretetime controllers operating with low-resolution quantisers, because even a chatter corresponding to one least significant bit (LSB) would result in large spikes in the derivative/ current term of the state, and those spikes are capable to mask the signals generated according to the control law in use. On the other hand, in the case of inverters, the resolution of the quantiser is inherently limited as the input range should include the whole span of output sinewave; consequently approaches such as windowed A/D converters [16] cannot be used, and the precision must be traded off against the complexity of A/D converter. A mixed analogue – digital solution was proposed in [17], where the error with respect to the sliding surface was first obtained by analogue computation and then converted into digital. In this work a discrete-time controller that does not introduce chattering is proposed. The controller is obtained by applying a simple modification of the method for designing discrete-time variable structure controllers proposed in [14]; the modified method leads to designing a linear state-feedback controller with feedforward compensation, and the obtained controller makes the state not repeatedly cross the sliding surface, but just approach it asymptotically (see Fig. 1 – Type II curve). Thus, the undesired chattering associated to oscillations across the sliding surface is removed. In addition, in the proposed controller robustness is enhanced by inserting an integral action. An additional interesting feature of the proposed controller is the fact that it is based on an equivalent control approach [7, 18– 20] rather than hysteresis modulation [21, 22]. As a matter of fact, the controller’s output in most SM controllers is a binary signal directly applied to the state of a power switch, whereas in the proposed approach it is the duty ratio of the power switch. Since duty ratio is a smooth 1

& The Institution of Engineering and Technology 2012

www.ietdl.org robustness of a DC – AC converter designed according to the proposed method are analysed.

2

Mathematical analysis

The design of the discrete-time controller is obtained by a simple modification of the method in [14] where the control algorithm is determined by enforcing the following ‘reaching law’ S(k + 1) = (1 − Q) S(k) − 1 sign(S(k)) Fig. 1 State trajectories Type I: the state moves towards equilibrium while repeatedly crossing the sliding surface S ¼ 0. Type II: the state moves towards equilibrium while asymptotically tending to the surface S ¼ 0

function of the PWM pulses, the sampling frequency fS can be set independently of the switching frequency fPWM . Thus, in the applications where the switching frequency is limited by the speed of power switches, the equivalent control approach enables the proposed control law to be used as the linear part of a hybrid controller in a multisampling approach. Otherwise, when a high switching frequency is required in order to reduce the converter size, but millisecond transients are allowed and/or the speed of controller is a limiting factor, it is possible to sample the output voltage at a frequency lower than the switching frequency and to use the same duty-cycle for several consecutive PWM periods according to a sort of undersampling approach. Operation in this undersampling regime was tested and is discussed in the sequel. The paper is organised as follows. The proposed approach is presented in Section 2, and the related control law for a voltage source DC – AC converter is derived. A design procedure to select the parameters of the digital controller is reported in Section 3. Then, in Section 4, performance and

(1)

In (1) S(k) ¼ 0 is the sliding surface, Q . 0 is a convergence rate parameter such that (1 2 Q) . 0, and 1 is a positive parameter. Note that the presence of the ‘sign’ term in the previous equation induces chattering on the controlled variable (see Type I curve in Fig. 1). Then, it is convenient to modify (1) by setting 1 ¼ 0 which leads to the simpler reaching law S(k + 1) = (1 − Q) S(k)

(2)

The advantage of adopting (2) is that the resulting state trajectory converges to the sliding surface without crossing it (see Type II curve in Fig. 1) and consequently chattering is not present. For the sake of simplicity, the discussion will refer to a single-phase buck converter tracking a sinusoidal reference, as shown in Fig. 2. The switching action is provided by a bridge of switching transistors. Using the state-space averaging technique the equations of the plant to be controlled can be expressed as follows x1 (t) = Vref (t) − bVo (t) x˙ 1 (t) = x2 (t) = V˙ ref (t) + x˙ 2 (t) = −

   b Vo (t) u(t)Vcc − Vo (t) dt − C RL L

1 1 bV x (t) − x (t) − cc u(t) + g(t) CL CL 1 CRL 2 (3)

Fig. 2 DC –AC converter Experimental tests were carried out with a Resistive load b Triac-controlled load c Rectifier load 2

& The Institution of Engineering and Technology 2012

IET Power Electron., pp. 1–8 doi: 10.1049/iet-pel.2011.0347

www.ietdl.org where u(t) ¼ 2 d(t) 2 1 is the control signal and d(t) is the average duty cycle of transistors 1 and 3. C, L and RL are the capacitance, the inductance and the load resistance, respectively. VCC , VO(t) and bVO(t) are the supply, output and sensed voltage, respectively; g(t) is given by g(t) =

1 1 ˙ Vref (t) + V (t) + V¨ ref (t) CL CRL ref

method, that is x∗3 (k + 1) = x∗3 (k) + Ts x∗1 (k) It is convenient to rearrange (8) and (10) setting z1 = x∗3 z2 = x∗1

(4)

z3 = x∗2

and the sinusoidal reference signal is expressed as Vref (t) = A sin(2pf0 t + f)

(10)

(5)

and obtaining z(k + 1) = A z(k) + b u∗ (k) + p g∗ (k)

Since d(t) represents a duty cycle, the control signal must be such that

(11)

with −1 ≤ u(t) ≤ 1

(6)

Constraints on the reference signal that guarantee the fulfilment of the latter property can be easily obtained as follows. From (3) it can be verified that in order to have zero error in steady state, that is, x1(t) ¼ x2(t) ¼ 0 ∀t, it must be CL u(t) = g(t) bVcc

⎡

⎤ 0 p=⎣0⎦ Ts

(12)

S(k) = c1 z1 (k) + c2 z2 (k) + z3 (k) = cT z(k) = 0

(13)

1 A = ⎣0 0

1 2pf0 + + (2pf0 )2 g(t) ≤ A CL CRL



bVCC RL A≤ RL + 2p f0 L + (2p f0 )2 CLRL

cT = c1

+ 1) = + 1) =

c2

1



Since z(k) should be driven to the surface according to the chosen approach (2), then use (11) and (13) to express the incremental change of S(k) as S(k + 1) − S(k) = cT z(k + 1) − cT z(k) = cT A z(k) + cT b u∗ (k) (7)

Discretising (3) by using Euler’s forward method it is obtained that x∗1 (k) + Ts x∗2 (k) ax∗1 (k) + hx∗2 (k)

⎡

where

Thus, it is easy to see that a constraint on A and f0 that guarantees that in steady-state (6) holds is as follows

x∗1 (k x∗2 (k

⎡ ⎤ 0 b = ⎣0⎦ d

Consider the surface

Then using the expressions of g(t) (4) and Vref(t) (5), it follows 

⎤ 0 Ts ⎦ h

Ts 1 a

+ cT p g∗ (k) − cT z(k)

(14)

and enforce that S(k + 1) 2 S(k) ¼ 2QS(k) obtaining cT A z(k) + cT b u∗ (k) + cT p g ∗ (k) − cT z(k) = −Q cT z(k) (15)

+ du∗ (k) + Ts g ∗ (k)

(8)

Solving for the control u∗ (k) gives the control law u∗ (k) = −(cT b)−1 [cT A z(k) + cT p g∗ (k) − (1 − Q) cT z(k)]

where Ts ¼ 1/fs is the sampling period and

(16) T a=− s CL T h=1− s CRL

d=−

(9)

Ts bVcc CL

In order to obtain zero steady-state error it would be sufficient to design a linear state feedback control with feedforward compensation directly for system (8); however, to increase robustness with respect to parameter variations an integral action is introduced in the controller. Thus, let x∗3 be the discrete-time integral of x∗1 , computed using Euler’s forward IET Power Electron., pp. 1– 8 doi: 10.1049/iet-pel.2011.0347

which determines a linear state feedback control with feedforward compensation. The coefficients c1 and c2 can be determined as follows (see [14]). Note that on the surface S(k) ¼ 0 it holds that z3 (k) = −c1 z1 (k) − c2 z2 (k)

(17)

Then, from (11) the dynamics restricted to the surface S(k) ¼ 0 are given by 

z1 (k + 1) z2 (k + 1)



  z1 (k)  =A z2 (k)

(18)

3

& The Institution of Engineering and Technology 2012

www.ietdl.org with  = A

1 −Ts c1



Ts 1 − Ts c2

 are As a result, picking c1 and c2 so that the eigenvalues of A within the unit circle guarantees that the state of the system restricted to the surface S(k) ¼ 0 converges to the origin. For choosing c1 and c2 it was proposed in [22] to bind the values of those coefficients to the desired natural frequency and damping ratio of the dynamics on the sliding surface. The approach in [22] applies to second-order continuoustime systems but can be extended to discrete-time systems through the concept of equivalent continuous-time system. In fact, a second-order discrete-time dynamical system with complex conjugate eigenvalues given by

li = e−zvn Ts · e+j

√2

1−z vn Ts

,

i = 1, 2

(19)

with vn . 0 and 0 , z , 1, possesses a pseudoperiodic mode which is equal to the sampled mode of the corresponding continuous-time system  z˙c (t) =

0 −v2n

 1 z (t) −2zvn c

effects related to the small perturbations that in presence of a sinusoidal reference are continuously applied to the system. The nominal supply voltage is VCC0 ¼ 28 V and the amplitude of the output voltage is VOrms ¼ 12 V. Such a converter can be part of an inverter for aerospace applications, where the 28 V is a standard bus voltage and three-phase 115 Vac or 36 Vac can be obtained by combining three converters via a suitable star-delta transformer. The nominal load is RL0 ¼ 2 V and b ¼ 0.2. The power switches are IR3710 MOSFETs. Our discussion about the selection criteria of the design parameters starts with the characteristic frequencies of the converter fPWM and fLC , and then it proceeds with the parameters appearing in (16) either implicitly [i.e. Ts , vn and z, which are related to c1 and c2 through (19) and (21)] or explicitly (i.e. Q). 3.1

In order to obtain good filtering of the switching noise while avoiding that the filter may load the inverter output, √ the resonance frequency of the LC tank, fLC = 1/2p LC can be chosen according to the rule-of-thumb

(20)

Thus, since the z and vn parameters of system (20) can be chosen according to well-understood design rules [22], the eigenvalues (19) can be determined using those rules. Then, simple calculations show that c1 and c2 are related to the assigned eigenvalues l1 and l2 through the following equations

2 fLC = f0 fPWM

c1 =

3

−1 + Ts c2 + l1 l2 Ts2

(21)

Converter design

A systematic procedure for the design of a DC/AC converter based on the proposed controller will be outlined in this section. The study is carried out both in simulation by means of a MATLAB model and experimentally by probing the response of a DC/AC converter prototype for several types of inputs. In order to focus on the control issues, the prototype is single-phase. The controller (16) is implemented in a digital signal processor (DSP), in order to obtain both design flexibility and a computing speed sufficient to numerically calculate the x∗2 state variable from voltage measurements according to x∗2 (k) =

x∗1 (k) − x∗1 (k − 1) TS

(22)

with sampling frequencies fS ≥ 100 kHz. The output voltage was monitored via an 8-bit A/D converter. Different reference waveforms can be selected: a sinusoid at f0 ¼ 50 Hz or a sinusoid at f0 ¼ 400 Hz or a pulsed voltage. Indeed, an analysis on the controller sensitivity to parameter variations is carried out with a step reference in order to avoid the 4

& The Institution of Engineering and Technology 2012

(23)

In the case of an inverter with f0 ¼ 400 Hz and fPWM ¼ 100 kHz, (23) provides fLC ¼ 6 kHz. The reactive components are accordingly chosen as L0 ¼ 60 mH, C0 ¼ 50 mF. 3.2

2 − l1 − l2 c2 = Ts

LC tank resonance frequency fLC

Sampling frequency fS

The natural choice for the sampling frequency is fS ¼ fPWM , providing an updated duty cycle at the beginning of every PWM period. On the other hand, the approach of duty ratio control, adopted for the controller, allows different options. For example, the capability to operate with fPWM . fS can be exploited in those applications where it is desired to reduce the size of reactive components without resorting to a faster controller. Some tests carried on in this configuration are reported in Section 4. In the sequel, unless it is stated differently, the sampling frequency is set to fS ¼ fPWM ¼ 100 kHz. 3.3

Natural frequency fn

The control bandwidth is largely determined by the natural frequency of the controlled system fn ¼ vn/2p, and it is chosen on the basis of application-specific requirements about transient response. In order to emphasise the effects of natural frequency variations, experimental investigations on the system sensitivity to this parameter were carried on by observing the response to a step reference voltage. A good trade-off between transient duration and overshoot amplitude (Fig. 3) is obtained for fn ≃ fLC /2

(24)

According to (24), corresponding to the previously selected fLC the natural frequency for the prototype is set to fn ¼ 3 kHz. IET Power Electron., pp. 1–8 doi: 10.1049/iet-pel.2011.0347

www.ietdl.org

Fig. 3 Response to step reference voltage (timebase: 500 ms/div, voltage: 2 V/div) obtained for fn ¼ 0.5fLC ¼ 3 kHz, Q ¼ 0.5 and z¼1

Fig. 5 Duration of the transient DT and peak deviation DV experimentally observed in the output voltage VO in response to a step on the supply voltage VCC from 26 to 30 V for different choices of z Q parameter is set as Q ¼ 0.5

3.4

Damping ratio z

Smooth variations of the supply voltage in the VCC0 + 25% range have minor effects on the converter output. Nevertheless, fast transients can lead to appreciable pulses in output, with amplitude and duration dependent on the damping ratio coefficient z. The observed behaviour was analysed by a model of the system, developed in MATLAB environment, simulating the closed-loop response to small-signal perturbations. Fig. 4 shows the amplitude of the closed-loop transfer function between output and harmonic perturbations on the supply voltage obtained by simulations. It can be observed that the closed-loop response exceeds unity in a frequency range that decreases with z and vanishes for z . 0.7. This can be related to the reduction of transients; in fact Fig. 5 reports the experimentally observed peak deviation (DV) and duration of the transient (DT) induced by a step variation in the supply voltage, and it can be seen that both DT and DV decrease by increasing z; the latter condition corresponds to having the closed-loop response in Fig. 4 lower than unity. As a result, z ¼ 1 was chosen for the prototype design.

Fig. 4 Amplitude of the closed-loop transfer function between harmonic perturbations on the supply voltage VCC and the output voltage, obtained by simulation for different values of the z parameter a z ¼ 0.5 b z ¼ 0.7 cz¼1 Q parameter is set as Q ¼ 0.5 IET Power Electron., pp. 1– 8 doi: 10.1049/iet-pel.2011.0347

Fig. 6 THD as a function of Q and RL for different output frequencies

3.5

Convergence rate Q

The last parameter to be selected is Q that regulates the speed of convergence towards the surface S(k) ¼ 0. In Fig. 6 it is possible to observe that when f0 ¼ 50 Hz ( fS/f0 ¼ 2000) the minimum THD in the output voltage is obtained for Q ¼ 0.5. In this condition the THD is barely affected by RL . For larger values of f0 (i.e. for smaller values of fS/f0) both the THD and its sensitivity to RL increase, especially for low Q (Fig. 6). In Fig. 7 the experimental waveforms recorded in presence of the triac-controlled load of Fig. 2b for f0 ¼ 400 Hz ( fS/f0 ¼ 250) show that the recovery time after load steps is also reduced as Q grows. Nervertheless, when Q . 0.5 appreciable overshoots are displayed in the output waveforms (see Fig. 7c). In the applications where those overshoots represent a problem, and a slight increase of the overall THD can be accepted, the value Q ¼ 0.5 can be maintained even for f0 ¼ 400 Hz. As a result, this is what is done for the laboratory prototype.

4

Performance analysis

The typical output voltage and current waveforms obtained for the settings derived in the previous section, namely f0 ¼ 50 Hz, fS ¼ fPWM ¼ 100 kHz, fLC ¼ 6 kHz, fn ¼ 3 kHz, z ¼ 1, Q ¼ 0.5 and for nominal circuit parameters, that is, RL ¼ RL0 , L ¼ L0 and C ¼ C0 , are reported in Fig. 8. 5

& The Institution of Engineering and Technology 2012

www.ietdl.org

Fig. 8 Output of the prototype DC –AC converter in the nominal conditions Timebase: 5 ms/div; voltage: 5 V/div; current: 6 A/div

Fig. 7 Record of experimental waveforms corresponding to triaccontrolled load for different Q and fS/f0 ¼ 250 a Q ¼ 0.2 b Q ¼ 0.5 c Q ¼ 0.8 Time base: 250 ms/div; voltage: 5 V/div; current: 6 A/div. The load was RL ¼ RL0

Deviations from a sinusoidal trend are merely appreciable: Fig. 9a reports the voltage error x1 registered by the DSP along one sinusoid period, and shows that it rarely reaches +2 LSB of the A/D converter. When f0 ¼ 400 Hz, with the controller lagging with respect to the faster variations of the reference sinusoid, the peak of the observed voltage error increases to +4 LSB (see Fig. 9b). In order to make sure that the lower accuracy is related to the ratio between the sampling and the output frequencies which is decreased from fS/f0 ¼ 2000 to fS/f0 ¼ 250, the converter is also operated at f0 ¼ 50 Hz

6

& The Institution of Engineering and Technology 2012

with a sampling frequency decreased to fS ¼ 12.5 kHz; in fact that corresponds to the ratio fS/f0 ¼ 250 which is the same as for the tests at f0 ¼ 400 Hz, fS ¼ 100 kHz. Owing to the adopted approach of duty ratio control, it was possible to maintain the switching frequency unchanged at fPWM ¼ 100 kHz, simply by repeating the same duty cycle for eight consecutive PWM periods. The resulting voltage error (Fig. 9c) shows a maximum amplitude similar to that reported in Fig. 9b, although the trend is slightly modified. The capability to set the sampling rate independent of the switching frequency could be useful to reduce the converter size while saving cost and power dissipation of the controller. The converter robustness with respect to parametric variations was investigated on the basis of the THD dependence on the circuit parameters C, L and of the load RL . The THD modifications observed when a linear load in the range RL ¼ 0.05 – 20 RL0 is applied, and the internal capacity C is varied in the range C ¼ C0 + 50% with L ¼ L0 ¼ constant, are reported in Fig. 10. Similarly, the results obtained when L ¼ L0 + 50% while C ¼ C0 ¼ constant are reported in Fig. 11. It is possible to observe that when f0 ¼ 50 Hz for any RL . 0.1RL0 the THD remains almost constant between 0.5 and 0.7%. When f0 ¼ 400 Hz, both THD and its parametric variations tend to increase, especially with large loads. In the presence of a rectifier load (see Fig. 2c) with CL ¼ 5 mF, when the controller is designed according to the previously derived criteria, minor deviations from a sinusoidal trend appear in the output waveforms (see Fig. 12). For f0 ¼ 50 Hz the output waveforms are barely affected by variations of RL and L (see Fig. 13) and THD remains in the 0.6– 1.8% interval for any value of the circuit parameters in the ranges RL ¼ 0.05RL0/20– 20RL0 , L ¼ L0 + 50%. When f0 ¼ 400 Hz, the reduced ratio fS/f0 leads to an increase of THD and of its sensitivity to parameter variations. Moreover, it was also verified that THD is barely affected by variations of the internal capacitance C. When the waveforms reported in the Figs. 7, 8 and 12 are compared with the results obtained in similar conditions with other SM techniques (see, e.g. the results presented in [4, 12, 17, 23– 25]), an appreciable improvement is observed in terms of transient response and/or steady-state accuracy.

IET Power Electron., pp. 1–8 doi: 10.1049/iet-pel.2011.0347

www.ietdl.org

Fig. 11 THD in the output waveforms in the presence of a resistive load as a function of RL and L for C ¼ C0 , both for f0 ¼ 50 Hz and for f0 ¼ 400 Hz

Fig. 12 Output of the prototype inverter in the presence of a rectifier load for f0 ¼ 50 Hz Timebase: 5 ms/div; voltage: 5 V/div; Current: 6 A/div

Fig. 9 Voltage error along a sinusoid period, as recorded by the DSP [horizontal axis: sample index; vertical axis: voltage error (% of full scale)] for fPWM ¼ 100 kHz a f0 ¼ 50 Hz, fS ¼ 100 kHz b f0 ¼ 400 Hz, fS ¼ 100 kHz c f0 ¼ 50 Hz, fS ¼ 12.5 kHz

Fig. 13 THD in the output waveforms in the presence of a rectifier load as a function of RL and L for C ¼ C0 , both for f0 ¼ 50 Hz and for f0 ¼ 400 Hz

5

Fig. 10 THD in the output waveforms in the presence of a resistive load as a function of RL and C for L ¼ L0 , both for f0 ¼ 50 Hz and for f0 ¼ 400 Hz IET Power Electron., pp. 1– 8 doi: 10.1049/iet-pel.2011.0347

Conclusions

A discrete-time linear state feedback controller with feedforward compensation was presented for the design of voltage source DC – AC converters. The proposed algorithm is based on duty-ratio control and is obtained by modifying an existing SM design method. It does not introduce chattering in the output waveforms, and its robustness with respect to parameter variations is enhanced by introducing an integral action. 7

& The Institution of Engineering and Technology 2012

www.ietdl.org The design criteria for selecting the controller parameters were thoroughly discussed. The design technique was demonstrated by means of a prototype DC – AC converter, obtaining low THD, good dynamic response and good converter robustness with respect to parametric variations both in the presence of linear and non-linear loads.

12 13 14

6

Acknowledgment

The authors are grateful to Alfiero Schiaratura for his assistance in setting up the prototype and performing the experiments.

7

15 16

References 17

1 Venkataramanan, G., Divan, D.M., Jahns, T.M.: ‘Discrete pulse modulation strategies for high frequency inverter systems’, IEEE Trans. Power Electron., 1993, 8, (3), pp. 279– 287 2 Holtz, J.: ‘Pulsewidth modulation for electronic power conversion’, Proc. IEEE, 1994, 82, (8), pp. 1194– 1214 3 Buja, G.S.: ‘Optimum output waveform in PWM inverters’, IEEE Trans. Ind. Appl., 1980, IA-16, (6), pp. 830 –836 4 Carpita, M., Marchesoni, M., Oberti, M., Puglisi, L.: ‘Power conditioning system using sliding mode control’. Proc. 19th Power Electronics Specialists Conf. (PESC), Kyoto, Japan, 11– 14 April 1988, pp. 623– 633 5 Liu, Y.F., Meyer, E., Liu, X.: ‘Recent developments in digital control strategies for DC/DC switching power converters’, IEEE Trans. Power Electron., 2009, 24, (11), pp. 2567–2577 6 Gokhale, K.P., Kawamura, A., Hoft, R.G.: ‘Dead-beat microprocessor control of PWM inverter for sinusoidal output waveform synthesis’, IEEE Trans. Ind. Appl., 1985, IA-23, (5), pp. 901– 910 7 Utkin, V.I., Guldner, J., Shi, J.X.: ‘Sliding mode control in electromechanical systems’ (CRC Press, 1999, 1st edn.) 8 Jezernik, K., Zadravec, D.: ‘Sliding mode controller for a single phase inverter’. Proc. Fifth Applied Power Electronics Conf. and Exposition (APEC), Los Angeles, CA, USA, 11–16 March 1990, pp. 185– 190 9 Tai, T.L., Chen, J.S.: ‘UPS inverter design using discrete-time slidingmode control scheme’, IEEE Trans. Ind. Electron., 2002, 49, (1), pp. 67–75 10 Biel, D., Guinjoan, F., Fossas, E., Chavarria, J.: ‘Sliding-mode control design of a boost-buck switching converter for AC signal generation’, IEEE Trans. Circuits Syst. I, 2004, 51, (8), pp. 1539– 1551 11 Olivier, J.C., Le Claire, J.C., Loron, L.: ‘An efficient switching frequency limitation process applied to a high dynamic

8

& The Institution of Engineering and Technology 2012

18 19

20

21 22 23 24 25

voltage supply’, IEEE Trans. Power Electron., 2008, 23, (1), pp. 153–162 Jung, S., Tzou, Y.: ‘Discrete sliding-mode control of a PWM inverter for sinusoidal output waveform synthesis with optimal sliding curve’, IEEE Trans. Power Electron., 1996, 11, (4), pp. 567 –577 Young, K.D., Utkin, V.I., Ozguner, U.: ‘A control engineer’s guide to sliding mode control’, IEEE Trans. Control Syst. Technol., 1999, 7, (3), pp. 328– 342 Gao, W., Wang, Y., Homaifa, A.: ‘Discrete-time variable structure control systems’, IEEE Trans. Ind. Electron., 1995, 42, (2), pp. 117–122 Tan, S.-C., Lai, Y.M.: ‘Constant-frequency reduced-state sliding mode current controller for Cuk converters’, IET Power Electron., 2008, 1, (4), pp. 466– 477 Yousefzadeh, V., Babazadeh, A., Ramachandran, B., Alarco´n, E., Pao L., Maksimovic, D.: ‘Proximate time-optimal digital control for synchronous buck DC– DC converters’, IEEE Trans. Power Electron., 2008, 23, (7), pp. 2018– 2026 Ramos, R.R., Biel, D., Fossas, E., Guinjoan, F.: ‘A fixed frequency quasi-sliding control algorithm: application to power inverter design by means of FPGA implementation’, IEEE Trans. Power Electron., 2003, 18, (1), pp. 344–355 Sira-Ramirez, H.: ‘A geometric approach to pulse-width modulated control in nonlinear dynamical systems’, IEEE Trans. Autom. Control, 1989, 34, (2), pp. 184–187 Valderrama-Blavi, H., Bosque, J.M., Barrado, J.A., Munoz, M., Calvente, J.: ‘Design of a sinusoidal current source using a slidingmode-controlled asymmetrical full-bridge multilevel converter’, IET Power Electron., 2008, 1, (2), pp. 203 –213 Vidal-Idiarte, E., Carrejo, C.E., Calvente, J., Martinez-Salamero, L.: ‘Two-loop digital sliding-mode control of DC-DC power converters based on predictive interpolation’, IEEE Trans. Ind. Electron., 2011, 58, (6), pp. 2491–2501 Ramos, R., Biel, D., Fossas, E., Guinjoan, F.: ‘Interleaving quasisliding-mode control of parallel-connected buck-based inverters’, IEEE Trans. Ind. Electron., 2008, 55, (11), pp. 3865– 3873 Tan, S.C., Lai, Y.M., Tse, C.K.: ‘General design issues of sliding-mode controllers in DC-DC converters’, IEEE Trans. Ind. Electron., 2008, 55, (3), pp. 1160– 1174 Chang, E.C., Liang, T.J., Chen, J.F., Chang, F.J.: ‘Real-time implementation of grey fuzzy terminal sliding mode control for PWM DC– AC converters’, IET Power Electron., 2008, 1, (2), pp. 235–244 He, Y., Luo, F.L.: ‘Design and analysis of adaptive sliding-mode-like controller for DC– DC converters’, IEE Proc. Electr. Power Appl., 2006, 153, (3), pp. 401– 410 Muthu, S., Kim, J.M.S.: ‘Discrete-time robust sliding mode control for switching power converters’. Proc. 28th Power Electronics Specialists Conf. (PESC), Orlando, FL, USA, 17–21 June 1997, pp. 210–216

IET Power Electron., pp. 1–8 doi: 10.1049/iet-pel.2011.0347