A Class of High-Input Low-Output Voltage Single-Step ... - CORPE

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A Class of High-Input Low-Output Voltage Single-Step Converters with Low Voltage Stress on the Primary-Side Switches and High Output Current Capacity Huai Wang Henry Shu-Hung Chung Adrian Ioinovici Suggested Citation H. Wang, H. S. H. Chung, and A. Ioinovici, "A class of high-input low-output voltage single-step converters with low voltage stress on the primary-side switches and high output current capacity," IEEE Trans. on Power Electron., vol. 26, no. 6, pp. 1659-1672, Jun. 2011.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

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A Class of High-Input Low-Output Voltage Single-Step Converters with Low Voltage Stress on the Primary-Side Switches and High Output Current Capacity Huai Wang, Student Member, IEEE, Henry Shu-Hung Chung, Senior Member, IEEE, and Adrian Ioinovici, Fellow, IEEE

Abstract—Power conversion from an input voltage of several kilovolts to a low load voltage is of great significance in various applications, but poses serious challenges. In this paper, a new converter, which is able to realize such a large step-down conversion in a single step, is proposed by introducing a novel concept of dc–dc multiphase conversion and n-phase interleaving rectification. The proposed structure is formed by n switch pairs in the primary side, an n-phase isolation transformer with the primary windings connected to dc blocking capacitors, and an n-phase current multiplier in the output side. The switching patterns applied to the switch pairs have a phase difference of 360◦ /n, and the output inductor currents are interleaved correspondingly, making necessary a smaller output filter. For a Vi input voltage and Io load current, the converter features Vi /n voltage stress on the primary-side switches, and Io /n current stress on the secondaryside inductors and diodes. Thus, the magnetic size of the inductors is considerable reduced. The primary-side switches are commutated with zero-voltage-switching (ZVS). Therefore, rather than using insulated-gate bipolar transistors (IGBTs) or MOSFETs with higher voltage ratings, the most available, notable performing 500/600 V MOSFETs can be used in the proposed converter with several kilovolts supply voltage, allowing for a higher operation frequency and lower conduction losses. Compared with an input-series–output-parallel (ISOP) connection of full-bridge (FB) isolated converters, for the same voltage stress on the switches, the proposed converter requires half of the number of transistors and inherently balances the input voltage among the switch pairs. The switching mechanism of a typical switch pair in the kth interval Ts /n of a switching cycle is analyzed. A dc analysis was carried out to determine the dc conversion ratio and the ZVS conditions in an analytical form. It allows for a tradeoff design of the converter, such that to minimize the duty-cycle loss and maximize the ZVS load range. A 1500/48-V, 2-kW prototype with four switch pairs was designed, implemented, and evaluated. The experimental results prove the soft switching of the switches, the low voltage stress across the primary-side switches, and the low current flowing through the rectifier’s diodes and inductors. The efficiency measured at nominal power rating was 90.75%. Manuscript received March 24, 2010; revised August 2, 2010; accepted October 12, 2010. Date of current version July 22, 2011. This work was supported by the Research Grants Council of the Hong Kong Special Administrative Region, China, under Project CityU 112406. This paper is presented in part at the IEEE Energy Conversion Congress and Exposition 2009, San Jose, CA, and in part at the IEEE Applied Power Electronics Conference and Exposition 2010, Palm Springs, CA. Recommended for publication by Associate Editor J. A. Cobos. H. Wang and H. S.-H. Chung are with the Center for Power Electronics and School of Energy and Environment, City University of Hong Kong, Kowloon, Hong Kong. A. Ioinovici is with the Department of Electrical and Electronics Engineering, Holon Institute of Technology (HIT), 58102 Holon, Israel. Digital Object Identifier 10.1109/TPEL.2010.2089536

Index Terms—Current-multiplier rectifier, dc–dc conversion, high-voltage converter, multiphase converter, zero-voltageswitching.

I. INTRODUCTION OWER converters with input voltage up to several kilovolts have a large range of applications in power distributed generation, energy storage, and auxiliary power supplies for traction systems [1]–[3]. For example, typical railway systems are powered by dc transmission lines with voltage levels of 600, 750, 1500, or 3000 V. This voltage is then inverted into a three-phase ac voltage of 440 V, 60 Hz, and further rectified into a dc voltage of 110 V for charging up the backup batteries. The 110 V voltage is further converted to lower voltages for supplying the low-voltage equipment (which requires 24, 32, 48, or 64 V [3]). Fig. 1 shows the power distribution for the electrical system on trains in Hong Kong mass-transit-railway (MTR). As illustrated, the energy supplied to the low-voltage equipment goes through multiple power conversion stages for converting the medium voltage (MV) of several kilovolts into a low voltage (LV), implying a low overall conversion efficiency. An alternative energy-efficient approach would be to perform the MV-LV dc–dc conversion in one step and at high switching frequency. Investigations into the suitability of devices and corresponding topologies are essential to make this objective achievable. Insulated-gate bipolar transistors (IGBTs) and metal-oxidesemiconductor FETs (MOSFETs) are the predominant used devices for power conversion, especially for medium or low input voltage applications. If the input voltage level is the only concern, discrete IGBT or IGBT modules are preferred, as they have higher voltage blocking capability. However, the limitation of IGBTs is their low switching frequency. This will be an obstacle in achieving high power density, what is the general trend and requirement of future power supplies, especially for mobile applications like traction and auxiliary converters in trains [4], [5]. From this perspective, the use of MOSFETs is preferable if operation at high frequency is needed. Although discrete highvoltage MOSFETs rated up to 4000 V have emerged in the market, they usually present very low current ratings, for example 1 A, and high ON-resistance, with the value proportional k , k ∈ [1.6, 2.6], where VDS is the drain–source voltage to VDS of the MOSFET, thus, inducing a substantial conduction loss. Another detrimental aspect is the cost consideration. The cost

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Fig. 1. Typical block diagram of the electrical network on trains (e.g. Hong Kong MTR).

of high-voltage MOSFETs is significantly higher than the lowvoltage MOSFETs, due to their low demand. Concluding with the aforementioned analysis, 500 or 600 V MOSFETs of relatively low ON-resistance are the best candidates for the specified MV-LV conversion. It is thus necessary to find new suitable topologies to reduce the voltage stresses of the switching devices to a fraction of the input voltage, allowing for switches with lower ON-resistance to be used. Galvanic isolation is usually required for safety and preventing corrosion in MV-LV conversion. Mainly, there are two types of topologies being proposed to meet these requirements: three-level (TL) converters [6] and isolated input-series– output-parallel (ISOP) modular converters [7], [8]. TL converters incorporate two dc-link capacitors to split the input voltage, operating the outer two and inner two switches in antiphase. Additional diodes and/or flying capacitors are used to clamp the voltage on the transistors in the OFF-state. As a consequence, the voltage stress on each switch is only half of the input voltage. An alternative structure of TL converter [9] changes the parallel legs into series ones to share the input voltage. In MV applications where the input voltage is higher than 1000 V, the voltage stresses in TL converters are still too high to allow the use of the common 500/600 V MOSFETs with a reliable safety margin. Isolated ISOP modular structures converters, consisting of a number of isolated dc–dc converter modules, make it possible to meet the condition of high input voltage level. For instance, in [7], [10] and [11], a full-bridge (FB) converter was selected as the basic module to sustain a voltage stress of onenth of the input voltage, where n is the number of modules. The ISOP modular converters enable the use of low-voltage MOSFETs with low ON-resistance. By properly interleaving of the converter modules, the filter requirement can be reduced [12]. Despite its advantages, the challenge of the ISOP converter is to ensure the balance of input voltage and identical sharing of output current among different modules. Efforts have been made to tackle this concern with additional control schemes [13]–[17] or by impedance design method [18]. High-frequency operation is a crucial contributor toward high power density. Various kinds of soft-switching techniques have been proposed to allow high frequency operation of the switched mode power supplies without increasing their switching loss, such as ZVS [19], [20], zero-voltage– zero-current-switching (ZVZCS) [21]–[24] and zero-currentswitching (ZCS) [25]–[27]. Among them, ZVS is especially recommended for the converters employing MOSFETs as the switching devices. Different solutions were proposed to extend the ZVS conditions to light load [28]–[34].

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In the low-output-voltage applications, a high demanding current poses a significant challenge to the secondary-side rectifier circuit. Current-doubler [35] and current-tripler [36]–[38] rectifiers were proposed to increase the load current capacity two times and three times, respectively, as well as for maintaining high efficiency. These two rectification techniques have been applied in the voltage regulator modules (VRMs) area with relatively low input voltage and low output voltage conversion. In [39], a novel primary-side structure matching the currenttripler rectifier topology was proposed. Each primary-side switch was submitted to only one-third of the input voltage. The reduced voltage stress allows for the use of low-voltage MOSFETs having low ON-resistance. The converter was evaluated on a prototype with an input voltage of 1000 V. The structure proposed in this paper extends the primary-side structure in [39] and proposes a multiphase dc-ac conversion and n-phase interleaving rectification technique. It realizes the MVLV conversion in one step, avoiding multiple energy processing and the multiple losses associated with it. A special switching pattern, with a phase difference of 360◦ /n, is applied to each pair of two adjacent switches. A new class of soft-switched dc–dc converters is proposed, featuring the following properties. 1) With n switch pairs in the converter, the voltage stress on the switches on the primary side of the converter is only one-nth of the input voltage and the current stress on the inductors and diodes on the secondary side of the converter is only one-nth of the output current. 2) 2n MOSFETs rated 500 or 600 V are utilized as the primary-side switching devices, with proper safety margins, implying higher reliability, lower conduction loss and cost. 3) The MOSFETs are switched with ZVS, thus reducing switching losses. 4) The n-phase current multiplier gives high output current capacity. 5) The voltages among the switch pairs are inherently selfbalanced. 6) Due to the interleaving rectification, the input and output filters can be minimized. The generalized structure and operation principles of the proposed converter are given in Section II. Section III gives the dc analysis, including the dc voltage conversion ratio, effective duty cycle, ZVS range, and switch-pair-voltage self-balancing mechanism. Based on minimizing the duty-cycle loss and maximizing the ZVS range, Section IV gives a tradeoff design procedure for determining the values of the components used in the converter. A 2-kW, 1500/48-V prototype suitable for direct MVLV conversion on the trains of Hong Kong MTR has been built. The experimental results are given and favorably compared with theoretical predictions in Section V. II. GENERALIZED STRUCTURE AND OPERATION PRINCIPLE A. Circuit Structure The generalized structure of the proposed converter is shown in Fig. 2. It is formed by n switch pairs on the primary side and an n-phase isolation transformer with turns-ratio m. The

WANG et al.: CLASS OF HIGH-INPUT LOW-OUTPUT VOLTAGE SINGLE-STEP CONVERTERS WITH LOW VOLTAGE STRESS

Fig. 2.

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General structure of the proposed dc–dc converter.

Fig. 3. Circuit structure of the (k–1)th and kth switch pairs and associated rectifier branches.

primary windings are connected to the switch pairs with each winding having a series-connected dc blocking capacitor, while the secondary windings are connected to an n-phase rectifier. The dc blocking capacitors have the same value. There are n dclink capacitors C1 , C2 , . . . , Cn of the same capacitance to split equally the input voltage Vi . Each switch pair SPk is connected across a dc-link capacitor Ck (k = 1, 2, . . . , n). The structure of the (k–1)th and kth switch pairs and associated rectifier branches is shown in Fig. 3. The dc blocking capacitors connected to the primary windings are CW 1 , CW 2 , . . . , CW n . Each switch pair contains two switching devices, Sk U and Sk D (with the built-in diode–capacitor pairs Dk U –Ck U and Dk D –Ck D ) operated in antiphase. The switching patterns applied to the two adjacent switch pairs have a phase difference of 360◦ /n. The output current is shared by n identical parallel diode–inductor branches D1 –Lf 1 , D2 –Lf 2 , . . . , and Dn –Lf n to reduce the current stress of the inductors to one-nth of the load current. B. Operation Principle The output voltage is regulated by varying the duty cycle, the same in each switch pair. Fig. 4(a) gives the timing diagram of the proposed converter in one switch cycle and Fig. 4(b) presents the detailed operation timing diagram of the kth switch pair in the kth interval Ts /n. The duty cycle D was defined by the on-time of upper switch Sk U over the total duration of the kth interval, Ts /n. A dead time was added for soft-switching transitions. The operation modes for the switch pair SPk are theoretically analyzed based on the following assumptions: 1) the equivalent parasitic capacitors paralleled with each MOS-

Fig. 4. Operation timing diagram of the proposed converter. (a) Timing diagram in one steady-state cycle. (b) Detailed timing diagram of the kth switch pair in the kth interval of Ts .

FET are of the same value Cs , 2) the input voltage is shared evenly by the n input capacitors (this will be proved in Section III), and 3) the leakage inductances of each transformer winding have an identical value, Llk . The status of the other switch pairs keeps unchanged during the discussed time interval. vW x denotes the voltage on the primary-side winding Wx , vw x denotes the voltage across the secondary-side winding wx , iW x denotes the primary-side current flowing through Wx , ipx denotes the primary side current circulating through the switches, or their parasitic capacitances, of switch pair SPx , and iD x is the current flowing through diode Dx . During the considered kth interval: [tk 0 , tk 0 +Ts /n], with the exception of the switches in the pair SPk , all the other switches do not change their state: all the upper switches are in the OFF-state and all the lower switches are in the ON-state. Similarly, all the rectifier diodes, except Dk , are conducting in a freewheeling mode.

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Fig. 5. Operation modes of the kth switch pair in the kth interval of a switching cycle. (a) Mode k 0 [Before tk 0 ], (b) Mode k 1 [tk 0 , tk 1 ], (c) Mode k 2 [tk 1 , tk 2 ], (d) Mode k 3 [tk 2 , tk 3 ], (e) Mode k 4 [tk 3 , tk 4 ], and (f) Mode k 5 [tk 4 , tk 5 ].

Generally, the converter transfers energy when the upper switch of the kth switch pair SPk is on and then enters into freewheeling stage until another energy transfer stage begins after the upper switch of the (k+1)th switch pair SPk +1 is ON. Therefore, the energy transferred from primary side to secondary side is in a sequential manner in one steady-state cycle, allowing for an interleaved operation of the output inductors. During the transition intervals, the freewheeling currents in the primary-side or output inductor currents are used for providing the ZVS conditions for turning on MOSFETs. The detailed analysis allowing for steady-stage analysis and designing of the prototype in Sections III and IV are given as follows. Mode k1 [tk 0 , tk 1 ]: Before tk 0 , as shown in Fig. 5(a), the upper switches S(k −1)U and Sk U are OFF, while the lower switches S(k −1)D and Sk D are ON. Capacitor Ck U was charged at Vi /n. The circuit is in a freewheeling mode. The values of the currents before tk 0 will be proven later. They are iW (k −1) (tk 0 ) = (n − 1) io /(mn2 ), iW k (tk 0 ) = −io /(mn2 ), iW x (x = 1, 2, . . . ,

n, x = k − 1, k) = −io /(mn2 ), iD (k −1) (tk 0 ) = 0, iD k (tk 0 ) = 2io /n, iD (k +1) (tk 0 ) = io /n, iD x (x = 1, 2, . . . , n, x = k − 1, k, k + 1) = io /n. The primary-side winding voltages at tk 0 are zero. At tk 0 , Sk D is switched off with ZVS due to the presence of Ck D . Ck U is discharged and Ck D is charged, in a resonant manner, providing the ZVS condition for Sk U turn on at tk 1 . In this mode, the voltage across Ck D , vC k D increases from 0 to Vi /n, and the voltage on Ck U , vC k U , decreases from Vi /n to 0. It can be assumed that the voltage across the dc-blocking capacitor CW (k 1) keeps constant within one steady state with value of Vi /n (this will be proved in Section III). According to Fig. 5(b), from a KVL equation written in the loop formed by S(k −1)D in ON-state, CW (k −1) , Ck U and primary winding Wk −1 , it results that vW (k −1) goes from a zero value to a negative one (-Vi /n). Similarly, by writing a KVL equation in the following loop, formed by Ck D , Ck +1 , CW k , and primary winding Wk , it results that vW k increases from zero to a positive value Vi /n.

WANG et al.: CLASS OF HIGH-INPUT LOW-OUTPUT VOLTAGE SINGLE-STEP CONVERTERS WITH LOW VOLTAGE STRESS

Therefore, i0 ipk (t) = ipk (tk 0 ) cos(ωt) = − cos(ωt) (1) mn  io Llk Vi vC k U (t) = − sin (ωt) (2) n 2mn Cs  Llk io vC k D (t) = sin (ωt) (3) 2mn Cs  Llk io vW k = VC (k +1) + vC k D − VC W k = sin (ωt) 2mn Cs

vW (k −1) = vC k U (t) − VC W (k −1) = −

iW k (t) = iW k (tk 0 ) +

1 Llk

io 2mn



(4) Llk sin (ωt) Cs

io io [1 − cos (ωt)] + mn2 2mn  1 iW (k −1) (t) = iW (k −1) (tk 0 ) + vW (k −1) (t)dt Llk

vW (k −1) = −VC W (k −1) = −Vi /n  1 iW k (t) = iW k (tk 1 ) + vW k (t)dt Llk ≈−

io (n − 1) io [1 − cos (ωt)] − 2 mn 2mn

(6)

iW (k −1) (t) = iW (k −1) (t1 ) +

(7)

io [1 + cos (ωt)] (8) n iD (k −1) (t) = iL f (k −1) (t) − m[iW (k −1) (t) − iW (k −2) ]

io io [1 − cos(ωt)] + . 2n n

vW (k −1) (t)dt

Vi (n − 1) io − t 2 mn nLlk

(15) 2Vi io + t mn nLlk

ip(k −1) (t) = iW (k −1) (t) − iW (k −2) (t) =

iD k (t) = iL f k (t) − mipk = =

(9)

(10)

Diode Dk −1 , which was OFF in the previous Ts /n period, starts conducting because the primary-side current ip (k −1) becomes smaller than the corresponding reflected branch output current iL f (k −1) , indicating a change from energy transfer to a freewheeling mode for this rectifier branch. During the first mode, all the diodes are ON. The converter’s secondary side is still in the freewheeling mode. This mode ends when vC k D reaches Vi /n and vC k U decreases to zero. From (2), the duration of this mode results as   2mVi 1 −1  (11) tk 01 = tk 1 − tk 0 = sin ω io Llk /Cs Mode k2 [tk 1 , tk 2 ]: As vC k U (tk 1 ) = 0, Dk U conducts naturally. After a while, Sk U turns on with ZVS. The primary current

(13)



(16)

Vi io − t (17) mn nLlk

Vi t nLlk

(18)

io [1 + cos (ωt)] n

2mVi 2io − t n nLlk

(19)

iD (k −1) (t) = iL f (k −1) (t) − mip(k −1) = iD (k +1) (t) = iL f (k +1) (t) − mip(k +1) =

=

io io [1 + cos(ωt)] + 2n n iD (k +1) (t) = iL f (k +1) (t) − m[iW (k +1) (t) − iW k ]

1 Llk

(12)

(14)

ip(k +1) = iW (k +1) − iW k = −

iD k (t) = iL f k (t) − m[iW k (t) − iW (k −1) ]

=−

io Vi + t mn2 nLlk

ipk (t) = iW k (t) − iW (k −1) (t) = −

 where ω = 1/(Llk Cs ). Taking into account that iD x (t) = iL f x (t) − isecx (t) (x = 1, 2, . . . , n) and that the inductor currents keep their values at the transition instant, it results

=

vW k = vC k D + VC (k +1) − VC W k = Vi /n

≈

vW k (t)dt

=−

=

ipk (t) increases linearly, remaining less than the reflected branch output current. The converter is still in a freewheeling stage. According to Fig. 5(c)

(5)



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mVi t nLlk

(20)

mVi io + t. (21) n nLlk

During this mode, the leakage inductance of winding Wk is charged. The mode ends when ipk (t) reaches the reflected secondary-side current io /(mn), indicating the end of the freewheeling stage. During this mode, the primary-side winding Wk was supplied with voltage Vi /n, while the voltage across the corresponding secondary-side winding wk was zero (the secondary side was still freewheeling, even if the primary-side switch was turned on with the purpose of starting the transfer of energy. This process is typical for ZVS solutions in FB converters), resulting in a duty-cycle loss. According to (16), the duration of this interval is given by tk 12 = tk 2 − tk 1 =

io Llk . mVi

(22)

At the end of the second stage, Dk turns off with ZCS according to (19) and (22). At the instant tk 2 , according to (14)–(21), the values of the currents are: iW k (tk 2 ) = (n − 1)io /(mn2 ), iW (k −1) (tk 2 ) = −io /(mn2 ), ipk (tk 2 ) = io /(mn), ip(k −1) (tk 2 ) = 0, ip (k +1) (tk 2 ) = −io /(mn), iD k (tk 2 ) = 0, iD (k −1) (tk 2 ) = io /n, and iD (k +1) (tk 2 ) = 2io /n. Mode k3 [tk 2 , tk 3 ]: The converter enters the energytransfer stage. The primary-side windings’ voltages vW k (t) and vW (k −1) (t) are Vi /n and −Vi /n, the secondary-side windings voltages vw k (t) and vw (k −1) (t) become the reflected

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values of the voltages across the associated primary-side windings: Vi /(mn) and −Vi /(mn), respectively. The currents in both primary-side and secondary side are almost constant, by assuming that the current variations in the output inductors are negligible. Mode k4 [tk 3 , tk 4 ]: According to the controlled pulsewidthmodulated (PWM) signal, Sk U is turned-off at tk 3 with ZVS due to the parallel capacitance across the switch. The converter is commutated from the energy-transfer stage to the freewheeling stage. Ck U and Ck D are charged and discharged respectively by ipk (t)/2  1 io t (23) ipk (t)dt = vC k U = 2Cs 2mnCs  1 io Vi Vi − − vC k D = t (24) ipk (t)dt = n 2Cs n 2mnCs

III. DC ANALYSIS A. DC-Voltage-Conversion Ratio and Duty-Cycle Loss During the analyzed kth interval, the transfer of power from input to load occurs during Mode k3 by neglecting the energy transferred during the switch transition interval tk 34 for ZVS. An input-output energy balance written for a Ts /n interval gives    tk 3 DTs Vi Ts Vi io ipk (t) dt = − tk 01 − tk 12 = Vo io n n mn n n tk 2 (33) tk 01 is very short and negligible compared to tk 12 , therefore, according to (22) and (33), the conversion ratio M and dutycycle loss Dloss are given by   1 Vo nio Llk = M= D− (34) Vi mn2 mVi Ts

vW k = VC (k +1) + vC k D − VC W k = vC k D io Vi − = t n 2mnCs vW (k −1) = vC k U (t) − VC W (k −1)

Dloss = B. ZVS Load Range

io Vi =− + t. n 2mnCs

tk 34 = tk 4 − tk 3 =

(26)

2mVi Cs . io

(27)

Mode k5 [tk 4 , tk 5 ]: At tk 4 , the body diode of Sk D conducts naturally. Therefore, Sk D can be turned on with ZVS subsequently. From KVL written in the same loops as in the first Mode, it results that the voltages across primary-side and secondary-side windings are zero and no energy is transferred from the primary side to secondary side. The converter operates in a new freewheeling stage. The values of the currents in the third, fourth and fifth modes remain as calculated at the instant tk 2 (n − 1) io , mn2

iw k (t) =

(n − 1) io , n2

io , ipk (t) = mn

iseck (t) =

io , n

iD k (t) = 0,

(35)

(25)

This mode ends when Ck D is fully discharged, giving, according to (24), the stage duration

iW k (t) =

nio Llk . mVi Ts

io , mn2 x = 1, 2, . . . , n,

x = k

(28)

io , n2 x = 1, 2, . . . , n,

x = k

(29)

iW x (t) = −

iw x (t) = −

For the lower switch Sk D , the energy stored in both output inductor and leakage inductor provides the ZVS turn-on condition. However, for turning on the upper switch Sk U , as illustrated in Mode k1 , only the energy stored in the leakage inductor is used to discharge the parallel capacitor Ck U . Therefore, the ZVS load range is determined from (2) by the condition that vC k U reaches zero  2  2 1 Vi Llk 1 io > 2Cs (36) 2 mn 2 2 n Moreover, the durations of the left and right dead time between the two PWM signals of each switch pair should be long enough to fully discharge the parasitic capacitor voltage  1 tdl > tk 01 = sin−1 [2mVi /(io Llk /Cs )] (37) ω (38) tdr > tk 34 = 2mVi Cs /io where tdl and tdr are the dead time of left and right sides, respectively. C. Switch-Pair-Voltage Self-Balancing Mechanism

io ip(k +1) (t) = − , ipx (t) = 0, mn x = 1, 2, . . . , n, x =  k, k + 1 (30) io , isecx (t) = 0, n x = 1, 2, · · · , n, x =  k, k + 1 (31)

isec(k +1) (t) = −

2io io , iD x (t) = , n n x = 1, 2, . . . , n, x = k, k + 1.

Fig. 6 represents a voltage loop during the freewheeling stage shown in Fig. 5(f). Let Vi ( k −1) and Vik denote the voltages across the input capacitors Ck −1 and Ck , respectively. During the freewheeling stage, the voltage across the transformer winding Wk −1 is zero, implying an equality between the voltages on capacitors Ck and CW ( k −1) . In case that a perturbation occurs, the current through the loop will equalize the two capacitor voltages. VC W (k −1) = Vik

iD (k +1) (t) =

(32)

For the other (n − 1) Ts /n intervals in Fig. 4(a), the converter operates in a similar manner.

(39)

In practice, the voltage across the dc blocking capacitor CW (k −1) is designed to be relatively constant over one switching cycle. From KVL written in a loop formed by

WANG et al.: CLASS OF HIGH-INPUT LOW-OUTPUT VOLTAGE SINGLE-STEP CONVERTERS WITH LOW VOLTAGE STRESS

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A simple control scheme with only one voltage loop was configured for the proposed converter. A pair of PWM signals was generated and then shifted by times of 360◦ /n to drive other switch pairs. Therefore, by neglecting tiny differences that could appear in the shifting process, the duty cycles of the generated PWM driving signals are the same. Duty-cycle imbalances caused by the mismatched driver dead time and MOSFET switching characteristics can be removed by system calibration [40], implying a negligible difference between Dk and Dk −1 . As a result, regardless of the capacitors values, the voltage distribution on each input capacitor will always reach parity after a few switching cycles from start-up or other dynamic perturbations. According to (39), it implies that the voltage across the dc-blocking capacitor CW ( k −1) is equal to Vi /n. D. Steady-State Current Distribution in the Windings

Fig. 6.

Voltage loop during the freewheeling stage of kth switch pair.

C(k −1)D , Ck U , CW (k −1) and Wk −1 (Fig. 3), as the winding average voltage is zero in a steady-state cycle, it results that VC W (k −1) = v¯C W (k −1) = v¯C k U + v¯C (k −1)D , where v¯C k U and v¯C (k −1)D represent the average value over a cycle. Referring to Fig. 4(b), the average voltage vC k U in one cycle is given by, (40), as shown at the bottom of this page, where Dk is the duty cycle of switch pair SPk . In Mode k1 , as the duration tk 01 is very short, sin (ωt) ≈ ωt, (2), (11), (23), (27), (40) give   Dk (41) v¯C k U = 1 − Vik . n Similarly, the average voltage vC (k −1)D in one cycle is given by v¯C (k −1)D =

Dk −1 Vi(k −1) , n

k = 1

(42)

where Dk −1 (k = 1) is the duty cycle of switch pair SPk −1 . According to (41) and (42), VC W (k −1) = v¯C k U + v¯C (k −1)D = Vik +

1 (Dk −1 Vi(k −1) − Dk Vik ), n

k = 1. (43)

Substituting (43) into (39), one gets D(k −1) Vik = , Vi(k −1) Dk

T s +t k 0 v¯C k U =

tk 0

tk 1 =

tk 0

vC k U (t)dt Ts

tk 1 =

tk 0

vC k U (t)dt + 0 + 0 +

k = 1.

vC k U (t)dt +

tk 4 tk 3

where iw j,k denotes the current through the secondary-side winding wj in the kth energy transfer stage. It can be observed from Fig. 4(b) that a winding current changes its value only two times in a steady cycle Ts . Such a change can take place only in the first two operation modes after the transition from a Ts /n interval to the next Ts /n interval. For example, iw k , which was −io /n2 before the beginning of the kth interval, will change to (n − 1)io /n2 during the first two modes of the kth interval and will change again to −io /n2 after the transition to the (k + 1)th interval. Therefore, during the transition from the kth energy-transfer stage to (k + 1)th energytransfer stage, the currents in the corresponding two adjacent windings wk and wk +1 decrease and increase respectively by the same amount of current defined as Δi, and those in other secondary-side windings keep constant. It can be shown that, (46), as shown at the bottom of the next page. Considering that the initial current of the transformer is

(44)

tk 2 tk 1

iw 1,k + iw 2,k + · · · + iw n ,k = 0.

vC k U (t)dt + 

vC k U (t)dt + Ts − Ts

It is essential to study the steady-state current distributions in the transformer windings, therefore, to verify the initial values used for analysis of the first mode in Section II. As shown in Fig. 4(a), there are n energy-transfer stages in one cycle. The current in each output inductor is considered to have a constant value io /n. As diode Dx was blocked in the xth energy-transfer stage (x = 1, 2, . . . , n), ⎧ stage 1: iw 1,1 − iw n ,1 = iL f 1 = io /n ⎪ ⎪ ⎪ ⎪ ⎨ stage 2: iw 2,2 − iw 1,2 = iL f 2 = io /n (45) .. ⎪ . ⎪ ⎪ ⎪ ⎩ stage n: iw n ,n − iw (n −1),n = iL f n = io /n

Dk Tns

tk 3 tk 2

vC k U (t)dt + 

tk 4 tk 3

vC k U (t)dt +

T s +t k 0 tk 4

(47) vC k U (t)dt

Ts

− tk 34 Vik

(40)

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TABLE I DESIGN SPECIFICATIONS OF THE PROPOSED DC–DC CONVERTER WITH FOUR SERIES-CONNECTED SWITCH PAIRS

By solving (45)–(47), one gets Δi = io /n, iw k ,k = iw x = −

(n − 1) io , n2

io (x = 1, 2, · · · , n, and x = k) n2

(48)

Therefore, the current distribution in the primary-side windings in steady state is given by iW k ,k =

(n − 1) io , mn2

io mn2 x = 1, 2, . . . , n, and x = k. (49)

iW x = −

According to (48), the currents in the secondary-side windings of the isolation transformer at the beginning of the kth stage are given by iw (k −1) (t0 ) = iw x (t0 ) = −

io , n2

(n − 1) io n2

x = 1, 2, . . . , n, and x = k − 1.

(50) (51)

Based on (50) and (51), the initial currents flowing through the primary-side windings and rectification diodes of the analyzed kth interval in Section II are given by the following equations (52) and (53), respectively ⎧ (n − 1) io ⎪ ⎪ ⎨ iW (k −1) (t0 ) = mn2 (52) ⎪ ⎪ ⎩ iW x (t0 ) = − io , x = 1, 2, . . . , n, and x = k − 1 mn2 ⎧ iD (k −1) (t) = iL f (k −1) − [iw (k −1) − iw (k −2) ] = 0 ⎪ ⎪ ⎪ ⎪ ⎪ 2io ⎪ ⎪ ⎨ iD k (t) = iL f k − [iw k − iw (k −1) ] = n (53) ⎪ ⎪ i o ⎪ ⎪ iD x (t) = iL f x − [iw x − iw (x−1) ] = , ⎪ ⎪ n ⎪ ⎩ x = 1, 2, · · · n, x = k − 1, k. IV. DESIGN CONSIDERATIONS A. Design Specifications Design considerations are presented here based on the prototype specified in Table I. The variation of the input voltage is within ±10% of the nominal value 1500 V. A converter with four switch pairs are considered here as a demonstration example, i.e. n = 4.

B. Turns Ratio of the Isolation Transformer (m) According to (34), m=

Vi Deff n2 Vo

(54)

where Deff = D − nio Llk /(mVi Ts ). By substituting n = 4, Vi = 1500 V, Vo = 48 V, Deff ,m in = 0.5 into (54), it results in m = 0.977. Thus, the value of m is practically chosen to be close to such theoretical value. C. Design of the Value of the Leakage Inductance of the Transformer (Llk ) The leakage inductance is a very crucial parameter to determine the duty-cycle loss and soft-switching range as shown in (35) and (36), which are represented in Fig. 7 and Fig. 8. It can be observed that a lower inductance value is beneficial to reducing the duty-cycle loss while narrowing the soft-switching range. Therefore, a tradeoff design between duty-cycle loss and ZVS load range was considered. Consequently, Llk was selected with the value of 20 μH to achieve soft switching from a 60% load and above. The duty-cycle loss at nominal load will be 0.11 accordingly. It should be noted that the leakage inductance of isolation transformer depends on the design and fabrication process conducted by the manufacturer. On the one hand, it is unnecessary to design transformers with the required leakage inductance because an external inductor can be placed in series

⎧ ⎪ ⎪ iw 1,1 = iw 1,n + Δi, iw 2,1 = iw 2,n , . . . , iw (n −1),1 = iw (n −1),n , iw n ,1 = iw n ,n − Δi ⎪ ⎪ ⎨ iw 1,2 = iw 1,1 − Δi, iw 2,2 = iw 2,1 + Δi, iw 3,2 = iw 3,1 , . . . , iw n ,2 = iw n ,1 .. ⎪ . ⎪ ⎪ ⎪ ⎩ iw 1,n = iw 1,(n −1) , . . . , iw (n −2),n = iw (n −2),n −1 , iw (n −1),n = iw (n −1),n −1 − Δi, iw n ,n = iw n ,n −1 + Δi.

(46)

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Fig. 7. Duty-cycle loss versus leakage inductance under different load conditions (V i = 1500 V, Io , ra te d = 41.7 A, m = 1, n = 4, fs = 50 kHz). Fig. 9.

Rectifier inductor currents and output current (n = 4).

Therefore, the output current ripple is reduced to n (1 − Deff )/(n − Deff ) times of the phase current ripple. For n = 4, Deff = 0.5, the output current ripple will be 57% of the phase current ripple. The output inductor was designed according to the specified Δio in Table I as Lf m in ≥ (1 − Deff , m in )

Vo Ts . Δio

(57)

For each phase, an inductor with a value of 124 μH was chosen. E. Design of Output Capacitor (Co )

Fig. 8. Minimal load for soft-switching versus leakage inductance (V i = 1500 V, Io , ra te d = 41.7 A, m = 1, n = 4, fs = 50 kHz).

with the primary-side windings of the transformer. On the other hand, the leakage inductance is usually predetermined, provided by the manufacturer. The components used in the converter are thus designed with the leakage inductance. D. Design of Output Inductors (Lf ) Fig. 9 shows the relationships between the theoretical inductor current of each rectifier branch (phase) and the output current with n = 4. Assuming that the inductors are identical (i.e. Lf 1 = Lf 2 = · · · = Lf n) one can obtain the phase current ripple   Deff Vo Ts . (55) ΔiL f k = 1 − n Lf The output current ripple is given by Δio = (1 − Deff )

Vo Ts . Lf

(56)

The output voltage ripple Δvo and RMS current of the capacitor IC o ,RM S are given by ΔiL o (Ts /n) ΔiL o RESR C o (58) + 8Co 2 √ 3 ΔiL o . (59) IC o ,RM S = 6 The capacitance Co , equivalent series resistance (ESR) RESR C o , and ripple current rating IA C of the capacitor are selected to ensure that the output voltage ripple is less than 1% of the nominal value, and IC o ,RM S is lower than IA C . Accordingly, two capacitors with Co = 220 μF, RESR = 212 mΩ and IA C = 1.49 A were used in parallel for the testing prototype. The power dissipation of the output capacitor is approximately equal to Δi2L o RESR /12. Δvo =

F. Design of Input Capacitors (C1 , C2 , C3 , C4 ) and DC-Blocking Capacitors (CW 1 , CW 2 , CW 3 and CW 4 ) The input capacitor voltage ripple and hold-up time are used to choose the values of the input capacitors. By neglecting the transition period tk 01 and tk 34 , the current flow through capacitor Ck , iC k = iin − ipk = Deff io /mn2 − io /mn = − (n − Deff ) io /mn2 when the upper switch Sk U is on, and iC k = iin = Deff io /mn2 when Sk U is off. Therefore,

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TABLE II NUMBER OF SWITCH PAIRS, TURNS RATIO OF TRANSFORMER AND VOLTAGE RATING OF MOSFET FOR DIFFERENT INPUT VOLTAGES

the voltage ripple on the capacitor Ck is given by ΔVC k =

(n − Deff ) io Deff Ts (n − Deff ) io RESR + mn2 Ck mn2

Ck

(60) where RESR C k is the ESR of the selected capacitors and ΔVC k is designed within 1% of Vi /n. Based on [41], the input capacitors are designed by considering the 20 ms hold-up time from 1500 V to 1200 V. It results in Cin ≥

2Po Th



η Vin2

norm

− Vin2



(61)

drop

where Th is the designed hold-up time, Vin norm is the nominal input voltage, Vin drop is the designed voltage drop within the hold-up time period, and η is the designed efficiency (η = 90% for calculation). The minimum calculated value Cin is 109.7 μF. Accordingly, four 400 V (450 V surge) 680 μF electrolytic capacitors with measured ESR of 150 mΩ at 100 Hz are selected for C1 –C4 . Film capacitors are selected for the dc blockings due to their high current capability and low ESR properties. In dc–dc converter applications, the selection of film capacitors applied for dc blocking mainly depends on the required capacitances limited by voltage ripple. By neglecting the transition intervals, according to Fig. 4, the voltage ripples of the dc-blocking capacitors are given by ΔVC W k =

1 CW k

(n − 1)io Ts . mn2 n

Fig. 10. Experimental prototype of the proposed converter. (a) Top-side view and (b) bottom-side view.

(62)

The value of the capacitance is designed to ensure the voltage ripple of each capacitor is less than 2.5%. In the prototype, the voltages across CW 1 , CW 2 , and CW 3 are Vi /4 and the voltage stress of CW 4 is 3Vi /4. Accordingly, 400 V/4.7 μF metallized polyester film capacitors with measured ESR of 14.3 mΩ at 50 kHz are selected for CW 1 , CW 2 , and CW 3 and 1200 V/1.5 μF metallized polypropylene film capacitor with measured ESR of 9.9 mΩ at 50 kHz is chosen for CW 4 . G. Selection of MOSFETs and Diodes The voltages stresses of the MOSFETs are Vi /n and the current stresses are io /mn. The voltage stresses of the secondaryside diodes are Vi /(mn) while their average currents are

Fig. 11. Measured PWM driving signals for switch pairs SP1 and SP2 (v G S 1 U , v G S 1 D , v G S 2 U , and v G S 2 D : 10 V/division, time base: 2 μs/division).

WANG et al.: CLASS OF HIGH-INPUT LOW-OUTPUT VOLTAGE SINGLE-STEP CONVERTERS WITH LOW VOLTAGE STRESS

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Fig. 12. ZVS turns on/off of one switch pair under different load conditions (v G S 1 U and v G S 1 D :10 V/division, v S 1 U and v S 1 D : 200 V/division, time base: 200 ns/division).

io /n. For the specified prototype, 600 V/35 A MOSFETs (SPW35N60CFD) and 600 V/15 A Diodes (FFH15S60 S) were used. Example of designs for other practically required input voltages are given in Table II. Here, there are tabulated the designed number of switch pairs, associated turns ratios of the transformer and voltage ratings of MOSFETs for an output voltage of 48 V. One can note that in all these cases, the widely used 500 or 600 V MOSFETs can serve for implementing the proposed converters.

V. EXPERIMENTAL VERIFICATIONS Based on the specifications given in Table I, a 2-kW 1500/ 48-V prototype with four switch pairs has been built and tested as shown in Fig. 10. It should be noted that the four-phase transformer are carried out with four separate cores (i.e., four single phase transformers) in the prototype. The experimental results are shown in Figs. 11–16. The PWM driving signals for switch pairs SP1 and SP2 were measured, as shown in Fig. 11. All of the values were measured

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

Fig. 15.

Measured efficiency under various load conditions.

Fig. 13. Waveforms of output inductor currents (iL f 1 , iL f 2 , iL f 3 , and iL f 4 : 5 A/division, time base: 4.0 μs/division).

Fig. 16. Measured losses in the components under full load (input power P i n = 2266.8 W and the ratios between the power loss in specific component and input power are indicated in percentage).

Fig. 14. Waveforms of driving signals and currents in one rectification branch (v G S 1 U and v G S 1 D : 10 V/division, iL f 1 : 10 A/division, iD 1 : 20 A/division, time base: 4.0 μs/division).

at the point when the PWM signals increase to 50% of their high level. The duty cycles for SP1 and SP2 are 0.608 and 0.606, respectively, indicating a negligible difference. The left and right dead times between driving signals for upper and lower switch in one switch pair were 360 ns. The phase shift angle between the observed two switch pairs is 90.4◦ , which is very close to the theoretical value 90◦ . Fig. 12 gives the switching waveforms of switch pair SP1 under various load conditions (i.e. 100%, 80%, and 60% of the nominal load). It can be observed that both switching transistors are turned on/off with zero-voltage, implying a negligible switching loss. With load variations, the reflected load current in

the primary-side changed; therefore, the slopes of the MOSFET voltages have a small difference during the ZVS commutation intervals. The voltage stresses on the two switches are only one-fourth of the total input voltage. Fig. 13 presents the waveforms of the four output inductor currents. Due to the self-balance mechanism of the input capacitor voltages and well-balanced power stage design, the prototype shows a good performance of output phase current sharing among different rectification branches, with Ts /4 phase shift between two adjacent inductor currents. It can be observed from the waveforms that the discrepancy between the largest inductor current and smallest inductor current is 0.96 A, which is acceptable when considering the design margin of the output inductors. Fig. 14 gives the inductor and diode currents in one rectifier branch. It can be noted that both the current stress of the inductor and average current of the diode are 1/n of the output current. Therefore, the magnetic size of the inductors and the conduction

WANG et al.: CLASS OF HIGH-INPUT LOW-OUTPUT VOLTAGE SINGLE-STEP CONVERTERS WITH LOW VOLTAGE STRESS

TABLE III COMPARISON OF NUMBER OF SWITCHES AND THEIR VOLTAGE STRESSES OF FOUR TYPES OF TOPOLOGIES

loss of the diodes were reduced, giving an improved efficiency and well thermal distribution. The waveforms are in a good agreement with the theoretical analysis. The efficiency was measured at different load conditions, starting at light load where ZVS is lost, and up to nominal load. The results are plotted in Fig. 15. The efficiency measured at around nominal power rating (Po = 2023 W) is 90.75%. The power losses in different components were measured under full load as shown in Fig. 16. The input power is 2229.2 W and the ratios between the power loss in specific component and input power are also indicated in the figure. It can be noted that the major losses are in the passive components, i.e. isolation transformers, output inductors and rectifiers, while the total loss in the MOSFETs is only 2.51% of the input power. It implies that the power loss of the MOSFETs is dominantly induced by the conduction loss and their switching loss is negligible with the aid of ZVS switching. VI. CONCLUSION A class of dc–dc converters suitable for high input voltage applications was proposed. It performs a conversion from several kilovolts to an LV of 48 V in a single step. Both the voltage stress on the primary-side switches and current stress in the secondary-side inductors/diodes were reduced by n times, allowing the use of MOSFETs and diodes with lower voltage and current ratings. ZVS of the switching devices determines a minimum switching loss. The voltages across the input capacitors and the currents through the output inductors are well-balanced due to the intrinsic self-balance mechanism. The current multiplier with interleaved rectification in the secondary-side reveals high current capacity and reduced size of magnetic components. The experimental evaluations on a 1500/48-V 2-kW prototype with four switch pairs verify the theoretical analysis. An efficiency of 90.75% was obtained at nominal load. Compared with other available topologies, as shown in Table III, the proposed structure represents the optimum one with respect to the voltage stress on the switches and number of switches. Especially, compared with FB based ISOP converters, the proposed converters withstand the same voltage stress, however, halve the number of switches. REFERENCES [1] F. Blaabjerg, Z. Chen, and S. B. Kjaer, “Power electronicsas efficient interface in dispersed power generation systems,” IEEE Trans. Power Electron., vol. 19, no. 5, pp. 1184–1194, Sep. 2004.

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[2] L. M. Tolbert and F. Z. Peng, “Multilevel converters as a utility interface for renewable energy systems,” in Proc. Power Eng. Soc. Summer Meeting, 2000, vol. 2, pp. 1271–1274. [3] IEEE Standard for Passenger Train Auxiliary Power Systems Interfaces, IEEE Std. 1476-2000, 2000. [4] J. Biela, U. Badstuebner, and J. W. Kolar, “Design of a 5-kW, 1-U, 10-kW/dm3 resonant dc–dc converter for telecom applications,” IEEE Trans. Power Electron, vol. 24, no. 7, pp. 1701–1710, Jul. 2009. [5] M. Pavlovsky, de Haan, and J. A. S. Ferreira, “Reaching high power density in multikilowatt dc–dc converters with galvanic isolation,” IEEE Trans. Power Electron., vol. 24, no. 3, pp. 603–612, Mar. 2009. [6] J. Pinheiro and I. Barbi, “The three-level ZVS-PWM dc-to-dc converter,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 486–492, Oct. 1993. [7] J. W. Kim, J. S. You, and B. H. Cho, “Modeling, control, and design of input-series-output-parallel-connected converter for high-speed-train power system,” IEEE Trans. Ind. Electron., vol. 48, no. 3, pp. 536–544, Jun. 2001. [8] V. Vorp´erian, “Synthesis of medium voltage dc-to-dc converters from low voltage, high-frequency PWM switching converters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1619–1635, Sep. 2007. [9] I. Barbi, R. Gules, R. Redl, and N. Sokal, “DC–DC converter: Four switches Vp k = Vin /2, capacitive turn-off snubbing, ZV turn-on,” IEEE Trans. Power Electron., vol. 19, no. 4, pp. 918–927, Jul. 2004. [10] X. Ruan, W. Chen, L. Cheng, C. K, H. Yan, and T Zhang, “Control strategy for input-series-output-parallel converters,” IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 1174–1185, Apr. 2009. [11] J. P. Lee, B. D. Min, T. J. Kim, D. W. Yoo, and J. Y. Yoo, “High efficient interleaved input-series-output-parallel-connected dc/dc converter for photovoltaic power conditioning system,” IEEE Energy Convers. Congr. and Expo., pp. 327–329, 2009. [12] C. Chang and M. A. Knights, “Interleaving technique in distributed power conversion systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 42, no. 5, pp. 245–251, May 1995. [13] R. Ayyanar, R. Giri, and N. Mohan, “Active input-voltage and load-current sharing in input-series and output-parallel connected modular dc–dc converters using dynamic input-voltage reference scheme,” IEEE Trans. Power Electron., vol. 19, no. 6, pp. 1462–1473, Nov. 2004. [14] R. Giri, V. Choudhary, R. Ayyanar, and N. Mohan, “Common-duty-ratio control of input-series connected modular dc–dc converters with active input voltage and load-current sharing,” IEEE Trans. Ind. Appl., vol. 42, no. 4, pp. 1101–1111, 2006. [15] H. Mao, L. Yao, C. Wang, and I. Batarseh, “Analysis of inductor current sharing in non-isolated and isolated multiphase dc–dc converters,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 3379–3388, Dec. 2007. [16] J. W. Kimball, J. T. Mossoba, and P. T. Krein, “A stabilizing, highperformance controller for input series-output parallel converters,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1416–1427, May 2008. [17] P. J. Grbovic, “Master/slave control of input-series-and output-parallelconnected converters: concept for low-cost high-voltage auxiliary power supplies,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 316–328, Feb. 2009. [18] E. de Jodar, J. A. Villarejo, F. Soto, and J. S. Muro, “Effect of the output impedance in multiphase active clamp buck converters,” IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3231–3238, Sep. 2008. [19] R. Fisher, K. Ngo, and M. Kuo, “A 500 kHz, 250 W dc–dc converter with multiple outputs controlled by phase-shifted PWM and magnetic amplifiers,” in Proc. High Freq. Power Conf., May 1988, pp. 100–110. [20] X. Ruan, L. Zhou, and Y. Yan, “Soft-switching PWM three-level converters,” IEEE Trans. Power Electron., vol. 16, no. 5, pp. 612–622, Sep. 2001. [21] J. Cho, J. Sabate, G. Hua, and F. Lee, “Zero-voltage and zero-currentswitching full bridge PWM converter for high-power applications,” IEEE Trans. Power Electron., vol. 11, no. 4, pp. 622–628, Jul. 1996. [22] F. Canales, P. Barbosa, and F. C. Lee, “A zero-voltage and zero-current switching three-level dc/dc converter,” IEEE Trans. Power Electron, vol. 17, no. 6, pp. 898–904, Nov. 2002. [23] T. T Song, N. Huang, and A. Ioinovici, “A zero-voltage and zero-current switching three-level dc–dc converter with reduced rectifier voltage stress and soft-switching-oriented optimized design,” IEEE Trans. Power Electron, vol. 21, no. 5, pp. 1204–1212, Sep. 2006. [24] I. Aksoy, H. Bodur, and A. Faruk Bakan, “A new ZVT-ZCT-PWM dc–dc converter,” IEEE Trans. Power Electron., vol. 25, no. 8, pp. 2093–2105, Aug. 2010. [25] J. Zhang, X. Xie, X. Wu, G. Wu, and Z. Qian, “A novel zero-currenttransition full bridge DC/DC converter,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 354–360, Mar. 2006.

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[26] A. Leung, H. Chung, and K. Chan, “A ZCS isolated full-bridge boost converter with multiple inputs,” in Proc. IEEE Power Electron. Spec. Conf., 2007, pp. 2542–2548. [27] H. Wang, Q. Sun, H. S. H Chung, S. Tapuchi, and A. Ioinovici, “A ZCS current-fed full-bridge PWM converter with self-adaptable soft-switching snubber energy,” IEEE Trans. Power Electron., vol. 24, no. 8, pp. 1977– 1991, Aug. 2009. [28] G. Hua, F. Lee, and M. Jovanovic, “An improved full-bridge zero-voltageswitched PWM converter using a saturable inductor,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530–534, Oct. 1993. [29] R. Ayyanar and N. Mohan, “Novel soft-switching dc–dc converter with full ZVS-range and reduced filter requirement—Part I: Regulated output applications,” IEEE Trans. Power Electron., vol. 16, no. 2, pp. 184–192, Mar. 2001. [30] F. Liu and X. Ruan, “ZVS combined three-level converter-A topology suitable for high input voltage with wide range applications,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 1061–1072, Apr. 2007. [31] Y. Jang and M. M. Jovanovic, “A new PWM ZVS full-bridge converter,” IEEE Trans. Power Electron, vol. 22, no. 3, pp. 987–994, May 2007. [32] A. J. Mason, D. J. Tschirhart, and P. K. Jain, “New ZVS phase shift modulated full-bridge converter topologies with adaptive energy storage for SOFC application,” IEEE Trans. Power Electron, vol. 23, no. 1, pp. 332–342, Jan. 2008. [33] Z. Ye, “Dual-bridge dc–dc converter with wide-range ZVS and zero circulating current,” IEEE Energy Convers. Congr. Expo., pp. 1353–1361, 2009. [34] W. Yu, J. Lai, and S. Park, “An improved zero-voltage switching inverter using two coupled magnetics in one resonant pole,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 952–961, Apr. 2010. [35] L. Balogh, “The current-doubler rectifier: an alternative rectification technique for push-pull and bridge converters,” Unitode Design Note DN-63, pp. 1–3, 1994. [36] M. Xu, J. Zhou, and F. Lee, “A current-tripler dc/dc converter,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 693–700, May 2004. [37] L. Yao, H. Mao, and I. Batarseh, “A rectification topology for high-current isolated dc–dc converters,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1522–1530, Jul. 2007. [38] Z. Zhang, E. Meyer, Y. Liu, and P. C. Sen, “A non-isolated ZVS self-driven current trippler topology for low voltage and high current applications,” IEEE Energy Convers. Congr. Expo., pp. 1983–1990, 2009. [39] T. T. Song, H. S. H. Chung, and A. Ioinovici, “A high-voltage dc–dc converter with Vi n /3 voltage stress on the primary switches,” IEEE Trans. Power Electron, vol. 22, no. 6, pp. 2124–2137, Nov. 2007. [40] A. Kelly, “Current share in multiphase dc–dc converters using digital filtering techniques,” IEEE Trans. Power Electron., vol. 24, no. 1, pp. 212– 220, Jan. 2009. [41] “Increasing hold-up time in switch mode power supplies,” Aimtech Application Note A018e, Feb. 2008.

Huai Wang (S’ 07) was born in China in 1985. He received the B.Eng. degree in electrical and electronic engineering from Huazhong University of Science and Technology, Wuhan, China, in 2007. He is currently working toward the Ph.D. degree in Department of Electronic Engineering, City University of Hong Kong, Kowloon, Hong Kong. He was a Research Assistant in the City University of Hong Kong in 2007–2008. During April to September 2009, he was an Intern at ABB Corporate Research Center, D¨attwil, Switzerland. His current research interests include high-voltage medium-power dc–dc conversions, softswitching technology, and fast dynamic control for converters. He is the recipient from the Power Sources Manufactures Association to present papers at Applied Power Electronics Conference and Exhibition 2009, WA. He is also the recipient of the Outstanding Paper Award for Yong Engineers/Researchers from Hong Kong Institute of Engineers and the Outstanding Academic Performance Award from the City University of Hong Kong, both in 2010.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

Henry Shu-Hung Chung (M’95–SM’03) received the B.Eng. degree in electrical engineering in 1991 and the Ph.D. degree in 1994, both from the Hong Kong Polytechnic University, Kowloon, Hong Kong. Since 1995, he has been with the City University of Hong Kong (CityU), Kowloon, where he is currently a Professor with the Department of Electronic Engineering. He is also the Chief Technical Officer of e.Energy Technology Limited—an associated company of CityU. His current research interests include time- and frequency-domain analysis of power electronic circuits, switched-capacitor-based converters, random-switching techniques, control methods, digital audio amplifiers, soft-switching converters, and electronic ballast design. He has authored or coauthored six research book chapters, and more than 260 technical papers including 120 refereed journal papers in his research areas. He holds 12 patents. Dr. Chung is the recipient of the Grand Applied Research Excellence Award in 2001 from the CityU. He was the IEEE Student Branch Counselor and was the Track Chair of the technical committee on power electronics circuits and power systems of the IEEE Circuits and Systems Society in 1997–1998. He was an Associate Editor and a Guest Editor of the IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications in 1999–2003. He is currently an Associate Editor of the IEEE Transactions on Power Electronics and the IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications.

Adrian Ioinovici (M’84–SM’85–F’04) received the Electrical Engineering degree in 1974 and the Dr.Eng. degree in 1981, both from Polytechnical Institute of Iasi, Iasi, Romania. In 1982, he joined the Holon Institute of Technology, Holon, Israel, where he is currently a Professor in the Electrical and Electronics Engineering Department. During 1990–1995, he was a Reader and then a Professor in the Electrical Engineering Department, Hong Kong Polytechnic University. He is the author of the book Computer-Aided Analysis of Active Circuits (Marcel Dekker, 1990) and of the chapter “Power electronics” in the Encyclopedia of Physical Science and Technology (Academic, 2001). He has authored or coauthored more than 100 papers in circuit theory and power electronics. He was an Associate Editor of the Journal of Circuits, Systems, and Computers. His current research interests include simulation of power electronics circuits, switched-capacitor-based converters and inverters, soft-switching dc power supplies, and three-level converters. Prof. Ioinovici has been the Chairman of the Technical Committee on Power Systems and Power Electronics of the IEEE Circuits and Systems Society. He was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS. He has been an Overseas Advisor of the IEICE Transactions, Japan. He was the Chairman of the Israeli chapter of the IEEE CAS Society between 1985 and 1990, and served as the General Chairman of several conferences, e.g., ISCSC’86, ISCSC’88 (Herzlya, Israel), and SPEC’94 (Hong Kong), organized and chaired special sessions in power electronics at International Symposium on Circuits and Systems (ISCAS) 1991, ISCAS’92, ISCAS’95, ISCAS’2000, and was a member of the Technical Program Committee at the Conferences ISCAS’91, ISCAS’95, ISCAS’06, Power Electronics Specialists Conference (PESC) 1992-PESC’95, Track Chairman at ISCAS’96, ISCAS’99, ISCAS’2005, Co-Chairman of the Special Session’s Committee at ISCAS’97, Co-chairman of the Tutorial Committee at ISCAS’06, and Co-Chair, Special Session Committee at ISCAS’10, Paris. He was a Guest Editor of special issues of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (August 1997 and August 2003) and a special issue on Power Electronics of Journal of Circuits, System, and Computers (August 2003).