A Hamming Distance Based Test Pattern Generator with ... - CiteSeerX

A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage Dhiraj K. Pradhan(1) , Dimitri Kagaris(2) , Rohit Gambhir(2) (1) Department of Computer Science, University of Bristol, Bristol BS8 1UB, UK (2) ECE Department, Southern Illinois University, Carbondale, IL 62901, USA email : [email protected], [email protected], [email protected]

Abstract

deterministic patterns or mapped patterns [3]. Though efficient methods have been developed to generate exhaus-

This paper proposes a new test pattern generator (TPG)

tive and pseudo-exhaustive patterns [1], many large cir-

which is an enhancement of GLFSR (Galois LFSR). This de-

cuits require unacceptably large numbers of vectors to at-

sign is based on certain non–binary error detecting codes,

tain acceptable test coverage. Consequently, a number of

formulated over an extension field of GF (2δ ), δ > 1. The

methods have been proposed in the literature to reduce the

resulting generator provides a guaranteed Hamming dis-

number of required patterns with additional hardware (see

tance between successive test patterns, resulting in shorter

[2, 5, 6, 7, 8, 12, 13, 14] as a small sample of the numerous

test lengths. As an additional advantage, the proposed TPG

techniques available).

has the intrinsic ability to detect 1–bit errors in the TPG itself. Detailed design methodology and experimental results

Pattern Generator

are presented. The results presented here also have impli-

GLFSR (Pseudo Random Pattern Generator)

cations in algebraic coding theory in that they may lead to new coding techniques for test pattern generation. CIRCUIT UNDER TEST (a)

Keywords: Test Pattern Generation (TPG), Built–in GLFSR

Self–Test (BIST), LFSRs, GLFSRs, Hamming Distance.

1 Introduction

CIRCUIT UNDER TEST (b)

Built-In-Self-Test (BIST) has been widely adopted in the industry at the board level and is gaining increasing acceptance at the IC level, in particular, in SOC designs. Hav-

SCAN CHAIN

Fig. 1 Proposed Test Pattern Generator (a) Parallel input BIST (b) Scan Chain based design.

ing a small number of test patterns in a BIST environment results in a reduced test time. This is particularly impor-

In this paper, we propose a new pseudorandom test pat-

tant when BIST techniques are used for fast on-line diag-

tern generator which aims to achieve higher efficiency by

nosis and reconfiguration. Also reduced BIST test appli-

using an enhanceed GLFSR [11]. Essentially the GLFSR is

cation time can reduce over all test cost in a hybrid envi-

designed in such a way that the test patterns are separated

ronment where easy-to-detect faults are handled by pseudo-

by a minimum distance which, in turn, guarantees more ran-

random patterns, and hard-to-detect faults are handled by

domness and faster traversal through a large fraction of the

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS’05) 1530-1591/05 $20.00 © 2005 IEEE

input space. As an dditional advantage, the mechanism can

δ

detect 1–bit errors in the mechanism itself. The design pro-

Φ

is directly connected to the circuit inputs, as shown in Fig.

Φ

I

1(a), or through a scan chain, as shown in Fig. 1(b). For

Φ

1

0

posed is equally applicable when the test pattern generator

D0

δ

Φm-1

2

D1

D

the purpose of illustration we use the organization shown δ

in Fig. 1(a) throughout the paper. However, when tests are

δ

δ

GF(2 δ ) Adder

applied as shown in Fig. 1(b), the scan chain may have to

δ

δ

GF(2 δ ) Multiplier

D

δ

GF(2 δ ) Storage Element

be segmented to equal lengths. Fig. 2: The Galois LFSR (Generalized LFSR)

This paper is organized as follows. The next section reviews GLFSRs and their implementation as test pattern gen-

α2

α

erator. Section 3 describes the mathematical framework of the proposed scheme, highlighting certain key observations.

D0

1

D1

Section 4 describes experimental results comparing the per-

D2

(a)

formance of our pattern generator with other dominant designs.

2 GLFSR - Review

a1

a3

a5

a0

a2

a4

(b)

GLFSR (Galois LFSR) was first proposed for test response compaction [10], also termed Generalized LFSR.

a1

This has been later shown to be also effective as a test pat-

a0

a3

a5

a2

a4

(c)

tern generator [11], providing better fault coverage than the standard LFSR. Fig. 2 illustrates the basic structure of a GLFSR(δ, m). The circuit under test is assumed to have

a0

a1

a2

a3

a4

a5

a3

a4

a5

(d)

n = (δ × m) inputs driven by the outputs of the GLFSR. A GLFSR(δ, m) has m stages, D0 ,D1 .. Dm−1 , where each a0

stage has δ binary storage cells. Each shift shifts δ bits from

a1

a2 (e)

one stage to the next. The feedback polynomial is represented as Φ(x) = xm + Φm−1 xm−1 + ... + Φ1 x + Φ0 The coefficients of the polynomial Φ(x) are elements GF(2δ ). Coefficient Φi multiplies the δ–bit feedback in-

Fig. 3: Structure of the GLFSR: (a) representation, (b) initial structure to be implemented, (c) optimized implementation, (d) 6-bit pattern generator (single register array implementation) and (e) Standard 6-bit LFSR (GLFSR(1,6)).

put over GF(2δ ) and this can be realized using only XOR gates. As described in [10], the GLFSR represents a general structure [10] and all known structures like the LFSR, MISR, multiple MISR, etc., constitute special cases.

As an example, Fig.

3 illustrates [11] the structure

of a GLFSR(2,3) defined over GF(22 ). The field GF(22 ) used in this example is defined by using the primitive polynomial p(x) = x2 + x + 1. The feedback polynomial is Φ(x) = (x3 + x2 + α2 x + α), where α is the primitive polynomial of p(x). The transition matrix of this GLFSR

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS’05) 1530-1591/05 $20.00 © 2005 IEEE

nately, as it turns out, a small value of δ suffices to provide

can be expressed as        

0 0 0 0 0 1

0 0 0 0 1 1

1 0 0 0 1 1

0 1 0 0 1 0

0 0 1 0 1 0

0 0 0 1 0 1

       

Table 1 shows the first 15 states of the GLFSR(2,3) and the GLFSR(1,6) (which is the standard LFSR) as a comparison. It can be seen below that any two consecutive states of GLFSR have greater distance than the corresponding pair of consecutive states in LFSR. Also proven in [11], the GLFSR demonstrates a significantly greater degree of randomness, resulting in improved fault coverage when compared to standard (binary) LFSR. GLFSR(2,3) 111111 101000 101010 010100 000101 111000 001111 100100 001001 111011 101001 110011 101011 101101 110010

GLFSR(1, 6) = Standard LFSR 111111 101111 100111 100011 100001 100000 010000 001000 000100 000010 000001 110000 011000 001100 000110

Table 1. States of GLFSR(2,3) and 6-bit LFSR(GLFSR(1, 6)) To generate patterns for a circuit of n inputs, we have a variety of GLFSRs(δ, m) available, where (m × δ) ≥ n. Different values of δ and m, where δm ≥ n, create differ-

maximal coverage.

3 EGLFSR In this section, we propose a technique for realizing a GLFSR, referred to as Enhanced GLFSR (EGLFSR), whose states in any cycle constitute the codewords from either linear or nonlinear non–binary codes of a minimum specified Hamming distance. Furthermore, these codes can be either binary or non-binary depending on the field used. If q = 2δ then the codewords can be expressed in δ-bit bytes over GF (2). Because the proposed design guarantees a certain minimum distance between two consecutive states, it provides for better randomness. Consequently, as the experimental results demonstrate, this new GLFSR actually has the potential to achieve shorter test lengths for improved fault coverage. The following develops the mathematical framework.

3.1 Mathematical Framework Definition:

An EGLFSR(δ, k, t), k, t >

0, is a

GLFSR(δ, k + t) with feedback polynomial φ(x)

=

t

p(x)(x − 1) where p(x) is a primitive polynomial of degree k over GF (2δ ). Definition: The Hamming distance between two states Si and Sj , is the Hamming distance between the two n-vectors (Si0 , Si1 , · · · , Sin−1 ) and (Sj0 , Sj1 , · · · , Sjn−1 ) which represent the contents of the delay elements for Si and Sj , respectively. It is straight-forward to observe that the Hamming distance between Si and Sj can also be defined as the number of nonzero terms in the polynomial, Si (x) − Sj (x).

ent types of GLFSRs, capable of generating different types

Theorem 3.1 The states of the EGLFSR are separated by a

of patterns for the same n-input circuit. For example, for

symbol distance of at least 2.

n = 36, we can choose the values of (δ,m) to be one of the following combinations: (2,18), (3,12), (4,9), (6,6), (9,4),

Proof: Let Si (x) and Sj (x) be two distinct states

etc. As the value of δ increases, the number of XOR gates

reached by the EGLFSR. Assuming j > i, we have that

needed to realize the generator increases, as well. Fortu-

Sj (x) = xj−i Si (x) mod φ(x), where φ(x) = p(x)(xt −1).

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS’05) 1530-1591/05 $20.00 © 2005 IEEE

= α + αx + α6 x2 + α2 x4 + α5 x5 + x6 .

The Hamming distance between Si (x) and Sj (x) is equal to the number of nonzero terms in Sj (x) − Si (x). j−i

But Sj (x) − Si (x) = (x

− 1)Si (x) mod φ(x) ⇒ j−i

Sj (x) − Si (x) = q(x)φ(x) + (x

The implementation of this EGLSFR is shown in Fig. 4. A partial list of test pattern generated by this EGLFSR, with

− 1)Si (x), for some

the initial seed being 100100000000000000, is given in Ta-

quotient q(x). By substituting the value x = 1, we have that

ble 2. As can be verified, the Hamming Distance between

Sj (1) − Si (1) = 0. This is only possible if Sj (x) − Si (x)

any two successive patterns is at least 2. It can also be noted

has an even number of nonzero terms, and since this num-

that these test patterns do not come from the standard single

ber is not 0, as the two states are distinct, it has to be at least

parity (distance 2) (n, k) code, where n = k + 1.

2.

000 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018

The above Theorem also provides a technique for generating the nonzero-nonbinary codewords of a large class of distance-2 codes (both linear and nonlinear) in a cyclic chain. Depending on the initial contents, the resulting codewords during a cycle may be from a linear or a non-linear code. However, the parity of the contents of the n storage elements in each of the δ rows remains constant during the cycle. If the initial contents are such that the parities of all the δ rows are even, then the set of codewords produced will

100100000000000000 000100100000000000 000000100100000000 000000000100100000 000000000000100100 010010011000001010 001011110011101010 001000111110110110 011010111111010011 100111100111101101 111011110100001111 110001110110111000 000110001100110111 110110011001101111 110000011011010100 010100011011010100 010000111011010100 010000011111010100 010000011011110100

019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 035 036 037

010000011011010000 000010000011011010 001001110000110000 000001001110000110 011011110001010101 111100010110111000 000111100010110111 110110010100001111 110000011010111000 000110000011010111 110110011000000011 100010000011010111 110010111000000011 100010100111010111 110010111100100011 100010100111110011 100000100100101001 101001010100011001 101000011010011111

be from a linear code. On the other hand, if at least one of Table 2. A partial list of test patterns

the δ rows has an odd parity, the resulting codewords will be from a nonlinear code. However, these nonlinear codes are also capable of detecting single δ-adjacent errors, that is their Hamming distance is at least 2.

3.2 Example +

1

+

4

+

7

10

+

13

+

16

2

+

5

+

8

11

+

14

+

17

3

+

6

+

9

12

+

15

+

18

Consider the design of a pattern generator with bit width 18. One can design this using an LFSR with a primitive polynomial of degree 18 over GF (2), or a GLFSR(3,6)

C

with a primitive polynomial of degree 6 over GF (23 ), or,

U

T

as proposed here, with an EGLFSR(3,5,1) using a primitive polynomial p(x) of degree 5 over GF (23 ), multiplied by (x − 1).

Fig. 4: EGLSFR for generating 18–bit test pattern with Hamming Distance 2.

Assume we use p(x) = α + α6 x2 + α6 x3 + αx4 + x5 , as the primitive polynomial of degree 5 over GF (23 ).

4 Experimental Results

Element α is taken to be the primitive element of GF (23 ) using primitive polynomial 1 + x2 + x3 . Then the overall polynomial is

The mathematical results established in Section 3 guarantee a distance-2 between two distinct patterns, if the feed-

6 2

6 3

4

5

φ(x) = (α + α x + α x + αx + x )(x + 1)

back polynomial used corresponds to φ(x) = (x − 1)p(x).

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS’05) 1530-1591/05 $20.00 © 2005 IEEE

As shown before [11], if the feedback polynomial φ(x)

Benchmarks

of a simple GLFSR corresponds to p(x), where p(x) is a

C499 C880 C1355 C1908 C2670 C3540 C7552

primitive polynomial over GF (2δ ), then the resulting TPG has significantly greater randomness. What the following results demonstrate is that if we further ensure that a nonbinary minimum distance of 2 (distance over GF (2δ )) between test patterns, then we achieve even further random-

EGLFSR (x − 1) 34 148 102 340 642 286 2624

EGLFSR (x2 − 1) 26 98 96 264 562 256 2248

ness, which provides for shorter test lengths. We have experimented on both stuck–at and transition faults. Test

Table 5. Best test length comparisons for EGLSFR versions for 95% Stuck-at-fault Coverage

length comparisons among LFSR, GLFSR, and EGLFSR for 95% fault coverage are shown in Table 3 for stuck–at faults and in Table 4 for transition faults. We have obtained also results on the use of an EGLFSR(δ, k, 2), that is, with φ(x) = p(x)(x2 − 1). As seen in Table 5, the test length

EGLFSR and GLFSR include of course more hardware

achieved is even shorter than that of EGLFSR(δ, k, 1).

logic than LFSR, but there is no significant difference be-

Benchmarks C499 C880 C1355 C1908 C2670 C3540 C7552

LFSR 160 3776 704 1664 3264 704 10016

GLFSR 50 210 260 540 928 400 3008

EGLFSR 34 148 102 340 642 286 2624

tween the overhead of EGLFSR and GLFSR. Finally, in addition to the improved fault coverage, the proposed mechanism has the intrinsic ability to detect 1– bit faults within TPG itself, as was demonstrated for binary LFSR in [9]. This is very useful as the effect of a single bit error in the TPG itself reduces the fault coverage drastically. For example, the fault coverage drop due to a faulty

Table 3. Best test length comparisons for 95% Stuck-at-fault Coverage

LFSR (with a single stuck–at fault) drops from 97.52% to 50.50% for C7552. The proposed mechanism has the ability to detect such a problem and alert the test engineer to it.

Benchmarks C499 C880 C1355 C1908 C3540

LFSR 576 7328 1280 7008 2700

GLFSR 256 704 672 1728 1150

EGLFSR 192 586 394 952 842

5 Conclusions

This paper proposes a test pattern generator which proTable 4. Best test length comparisons for 95% Transition-fault Coverage

vides for greater randomness than the GLFSR proposed earlier [11] through guaranteeing a minimum distance between test vectors. The mechanism can also detect 1–bit

We have also conducted a variety of experiments with

errors in itself. The results presented here can be gener-

different seeds, lengths, and characteristic polynomials.

alized to guarantee greater minimum distance between test

The trend is similar to the that in the tables above,

vectors by using Reed-Solomon codes [4]. It is expected

i.e., EGLFSR shows better performance than GLFSR

that with greater the minimum distance, the greater the de-

and GLFSR shows better performance than LFSR. The

gree of randomness. This is currently being investigated.

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS’05) 1530-1591/05 $20.00 © 2005 IEEE

References

[11] D. K. Pradhan, M. Chatterjee, “GLFSR - A New Test Pattern Generator for Built-in-Self-Test,” IEEE Trans.

[1] M. Abramovici, M. A. Breuer, A. D. Friedman, Digital

on CAD/ICAS, vol. 18, n. 2, pp. 238–247, 1999.

Systems Testing and Testable Design, Computer Science Press, New York, 1990.

[12] B. Reeb, H.-J. Wunderlich, “Deterministic Pattern Generation for Weighted Random Pattern Testing,”

[2] P. H. Bardell, W. H. McAnney, J. Savir, Built–in Test

Proc. European Design & Test Conf., 1996, pp. 30–36.

for VLSI, Wiley, New York, 1987. [13] A. P. Stroele, “Synthesis for Arithmetic Built–in Self– [3] M. Chatterjee and D. K. Pradhan, “A Novel Pat-

Test,” Proc. IEEE VLSI Test Symposium, 2000, pp. 165–

tern Generator for Near-Perfect Fault-Coverage”, IEEE

170.

Transactions on Computers, vol. 52, no. 12, pp. 1543– 1558, 2003.

[14] J. A. Waicukauski, E. Lindbloom, E. B. Eichelberger, O. P. Forlenza, “A Method for Generating Weighted

[4] D. J. Costello, S. Lin: Error Control Coding: Fundamentals and Applications, Englewood Cliffs, NJ: Prentice-Hall, 1982. [5] S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, “Generation of Vector Patterns Through Reseeding of Multiple–Polynomial Linear Feedback Shift Registers,” Proc. of the Inter. Test Conf., 1992, pp. 120–129. [6] D. Kagaris, “Built–In TPG with Designed Phaseshifts,” IEEE VLSI Test Symposium, Apr. 2003, pp. 365–370. [7] G. Mrugalski, J. Rajski, J. Tyszer, “Cellular Automata– Based Test Pattern Generators with Phase Shifters,” IEEE Transactions on CAD/ICAS, vol. 19, no. 8, pp. 878–893, 2000. [8] G. Mrugalski, J. Rajski, J. Tyszer, “Ring Generators – New Devices for Embedded Test Applications,” IEEE Transactions on CAD/ICAS, vol. 23, Issue 9, pp. 13061320, Sept. 2004. [9] D. K. Pradhan, C. Liu, K. Chakrabarty, “EBIST: A Novel Test Pattern Generator with On–Line Fault– Detection Capability” Proc. DATE Conf., 2003, pp. 224–229. [10] D. K. Pradhan, S. Gupta, “A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression,” IEEE Transactions on Computers, vol. 40, n. 6, pp. 743–763, 1991.

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS’05) 1530-1591/05 $20.00 © 2005 IEEE

Random Patterns,” IBM. J. Res. Develop., pp. 149–161, 1989.