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A HILBERT FRACTAL CODEC FOR REGION ORIENTED COMPRESSION OF COLOR IMAGES Jan Bormans 1 2

Serge Vernalde 2

;

1

Jan Cornelis 1

Ivo Bolsens 2

Hugo De Man 2  ;

ETRO/BIIP, VUB, Pleinlaan 2, B-1050 Brussels, Belgium IMEC/VSDM, Kapeldreef 75, B-3001 Leuven, Belgium

2

ABSTRACT

Region-Oriented Compression (ROC) is a computation intensive emerging technique for very low bitrate image and video coding. The design of a Hilbert fractal codec, a key-component for ROC of color images, is discussed. The implementation ef ciency of the codec is critical since it determines the feasibility of the global compression scheme. We discuss the role of the Hilbert fractal codec in the global codec scheme and the high-level design methodology that leads to a successful implementation of the codec design.

1. INTRODUCTION

Region-Oriented Compression (ROC) techniques have been shown to perform better than BlockOriented Compression (BOC) at high image compression ratios [1][2]. ROC is especially appropriate for previewing image databases, for progressive transmission, for preprocessing images in object recognition applications, and for remote vision applications. The main advantage of ROC is the combination of a high compression ratio, which decreases both the transmission cost and the (receiver) postprocessing, with the preservation of recognizability. It is therefore likely that ROC techniques will be included in the future MPEG-4 standard [3], not only as compression method, but possibly also as a method to obtain Video Object Planes (VOPs). A VOP is an arbitrarily shaped 2D video object component, typically an image region whose pixels are to be encoded with the same compression method (e.g. the background in a videoconferencing scene). Traditionally, the high computation and implementation complexity of ROC techniques are the main drawbacks when designing ROC based systems, especially for on-line and portable applications. We will focus on a ROC scheme for color images with low computation and implementation complexity. This scheme avoids the threefold complexity increase, that one would obtain by combining three greyscale ROC coders. This is achieved by introducing "RGB $ Hilbert fractal" transforms.  Professor at the Katholieke Universiteit Leuven

The overall eciency of the scheme strongly depends on the eciency of the computation of the forward transform in the encoder and the computation of the inverse transform in the decoder, especially since the speed of computation of the transforms determines the maximum pixel rate of the global ROC scheme (since every pixel has to be transformed).

2. COLOR IMAGE ROC

The Human Visual System (HVS) has a high sensitivity to sudden transitions and edges in the eld of vision (as discussed in [4]). In practice these discontinuities will correspond to the shapes or contours of the observed objects. The basic philosophy of ROC is to maximally guarantee the preservation of these contours by proposing a partitioning of the image that corresponds as much as possible to the contours in the image. A ROC encoder basically consists of an image dependent segmentation phase, which is followed by the actual coding of the segments (Figure 1 shows a one-component or greyscale ROC encoder). Segment Coding

Input Image

Coded Segments

8

Communication Channel

8 Segmentation

Segmented Image

Figure 1. Greyscale ROC encoder When dealing with color images, the traditional approach is to compress the dierent color components separately (e.g. RGB or Y UV ), possibly subsampling one or more components, yielding a poor subjective impression (poor coincidence of the segmentation of each individual color component) and a threefold implementation complexity. A color ROC scheme with a computation and implementation complexity comparable to that of a greyscale ROC coder has been proposed in [5]. The reduction in complexity is achieved by transforming the three RGB color components of each image pixel to a one-dimensional length L (pseudo greyscale containing color information).

Segment Coding

Coded Segments

24

Input Image

8 8

RGB

L

24

Communication Channel

L Image

8 24

Segmented Image

Segmentation

Figure 2. Hilbert fractal-based ROC enoder This length is found by following the Hilbert fractal (also referred to as the Peano curve), a space lling curve with attractive clustering properties for segmenting color images [6], in the RGB space from the origin to the RGB components of the given pixel. The resulting scheme is shown in Figure 2.

3. THE HILBERT FRACTAL

We will now focus on the rst stage (RGB ! L transform) of Figure 2, since its implementation is critical: every input pixel has to be transformed to the L space in the encoder (the inverse transform takes place in the decoder). The papers further discusses the design of the Hilbert fractal codec which includes both the forward (RGB ! L) and the inverse (L ! RGB ) transform. The Hilbert fractal can be generated starting from seed curves (Figure 3).

The length L, obtained by following the Hilbert fractal from the origin to a given pixel, is obtained by concatenating Y bitvectors which can be computed as follows [7]: k

Y = G[T  X ] k

T =T k

with:

k

new

k

(Y ?1 ):T ?1 k

k

X : bits at position k of the input components T : transform matrix G : bit mapping transform Y : output vector for iteration k k

k

Y and X are n bit vectors: n is the number of input components (we will further consider n = 3). z 2 T  X is then de ned as follows: k

k

i

z = i

Xt x 2

ij

j

j

=0

t =1!t x =x t = 0 ! t x =0 t = ?1 ! t x = 1 ? x ij

ij

ij

ij

Figure 3. 2D and 3D seed curves These seed curves are replaced by a set of similar seed curves, some of which are rotated with respect to the original. This process is iterated until the required resolution is achieved (e.g. 8 iterations for 8 bit color components). Figure 4 shows the result (in 2D) after 3 iterations.

j

ij

ij

j

j

j

j

Analogous formulae can be found for the inverse transform. The Hilbert fractal codec is intended to be a versatile component, for usage in dierent applications: some are demanding a full color resolution (e.g. image compression), some are not (e.g. preprocessing for object recognition). The iteration produces the most signi cant bits of L (coarsest resolution level) rst. We have paid special attention to maintain this property through the design trajectory: the codec then has a color resolution dependent pixel rate.

4. DESIGN METHODOLOGY 4.1. Modular Approach

Figure 4. 2D curve after 3 iterations

A modular approach has been chosen for several reasons: i) the dierent modules can be separately speci ed, simulated and implemented, ii) the reuse of the implemented components is simpli ed, iii) dierent modules can have dierent architectures, and iv) the interfacing between the algorithm designer(s) and the VLSI designer(s) is simpli ed (indeed, the algorithm designer(s) can be "shielded"

from all non-algorithm related modules). Additionally, late speci cation changes for one module do not imply "recompilation" of all modules.

Synopsys is used to further optimize the global design at gate level. The layout generation is done using the Cadence Opus environment.

clock0 clock

RGB in[0..7]

it is possible to directly write them in VHDL. These VHDL descriptions are then further considered in the same way as the cathedral-2/3 generated descriptions.

L

in0[0..23]

out0[0..23]

out[0..7]

clock1 in[8..15]

global controller

out[8..15]

instruction register

L in[16..23]

in1[0..23]

RGB out1[0..23]

IO

ir0 ir1 ir2 ASU instruction bits

out[16..23]

Figure 5. Dierent modules of the design

read & write addresses

local controller

flags

Figure 5 shows the three modules involved in this design: RGB ! L is the Hilbert fractal transform, and L ! RGB is the inverse Hilbert fractal transform. The IO module provides the multiplexing, the buering, the external interfacing, and, with power aspecs in mind, it switches o the RGB ! L module when the L ! RGB module is in use and vice-versa.

reg_file_5

reg_file_4

reg_file_3

reg_file_2

reg_file_1

4.2. High-Level Description

The modules have been described as C processes in a UNIX environment. Since the use of both C and UNIX is widespread, the participation threshold for the algorithm designer(s) is kept as low as possible. Each separate C process constitutes the stand alone functional reference for the VLSI designer(s).

UNIX allows to consider the concurrent execution of the dierent processes by redirecting the appropriate inputs and outputs. These concurrent C processes are the functional reference for the global design. The C descriptions have manually been converted to Silage [8], a C-like data ow oriented language.

4.3. Implementation Strategy

The cathedral-2/3 silicon compiler [9] was used to implement the dierent processes. Cathedral2/3 allows the designer to generate Application Speci c accelerator Units (ASUs) from a high-level description in Silage. An ASU is a datapath that is targeted towards a speci c application both in instruction set and architecture (Figure 6). The designer can explore dierent implementation alternatives by using compiler directives without having to change the high-level description. Merging of dierent ASUs can be considered, but it does not result in an optimal solution for this design. The ASU generation methodology consists of code generation yielding a signal ow graph, operator allocation, assignment to hardware, redundancy removal, adder structure speed-up and pipelining. The ASUs are generated in VHDL. If processes exist which can not adequately be described in Silage,

modes

it_5

internal state

buf_3

ot_3

buf_2

ot_2

buf_1

ot_1

it_4

it_3

arithmetic core

it_2

it_1

Figure 6. ASU datapath 4.4. Simulations

Simulations have taken place after each design step to verify functional consistency with the previous abstraction level, both for stand alone processes (Silage vs. C, VHDL vs. Silage) and for the global design (Global VHDL vs. global C). Initial simulations have taken place with typical input data. When the VHDL description was generated, Synopsys has been used to generate testvectors which have been used as additional input stimuli (in the appropriate formats) for all abstraction levels. Timing information is available at dierent abstraction levels: cathedral-2/3 allows for static timing analysis of the dierent ASUs, extended analysis tools are available at the VHDL level, both before and after the layout generation (backannotation of capacitance and resistor values). Pixel Rate (MHz) 50

45

40

35

30

Resolution (#bits) 25 10

12

14

16

18

20

22

24

Figure 7. Resolution dependent pixel rate

Figure 8. Hilbert fractal codec microphotograph 5. RESULTS

A Hilbert fractal codec has been realized in 0:7m double metal CMOS technology. The total design consists of 1942 equivalent NAND gates, resulting in a Silicon area of 1:7mm2 . The circuit has been processed by EUROCHIP (MIETEC/ALCATEL). For true color (24 bit) applications, pixel rates up to 27 MHz can be obtained. Figure 7 shows the applicable pixel rates for other resolutions. Figure 8 shows a microphotograph of the chip.

6. CONCLUSIONS

We have discussed an ecient implementation of the Hilbert fractal codec. This implementation not only demonstrates the feasibility of ROC for color images, but, since a modular design methodology was used, it also means that the codec can be reused with minor eort in other future designs. The proposed design methodology has the advantage that the designer can use a high-level environment, without losing the possibility of advanced ne-tuning of the solution.

ACKNOWLEDGEMENTS

This research was supported by a grant of the Flemisch institute for the promotion of scienti ctechnological research in the industry (IWT). We would also like to acknowledge Luc Marent (IMEC) for his valuable help during the physical realization stage.

REFERENCES

[1] M. Kunt, M. Benard, R. Leonardi, "Recent Results in High-Compression Image Coding," IEEE Transactions on Circuits and Systems, vol. CAS-34, No. 11, November 1987, pp. 13061336.

[2] M. Biggar, O. Morris, A. Constantinides, "Segmented-image coding: performance comparison with the discrete cosine transform," IEE Proceedings, vol.135, Pt. F, No. 2, April 1988, pp. 121-132. [3] L. Teixeira, M. Martins, "Video Compression: The MPEG Standards," Proceedings ECMAST 96, pp. 615-634, May 1996. [4] M. Kunt, A. Ikonomopoulos, M. Kocher, "Second-Generation Image-Coding Techniques," Proceedings of the IEEE, vol. 73, No. 4, April 1985. [5] J. Bormans, I. Bolsens, G. Lafruit, J. Cornelis, H. De Man, "A Fractal-Based RegionOriented Color Image Compression Scheme for VLSI Implementation," VLSI Signal Processing VII, Eds. J. Rabaey, P.M. Chau, J. Eldon, 1994. [6] R. J. Stevens, A. F. Lehar, F. H. Preston, "Manipulation and Presentation of Multidimensional Image Data Using the Peano Scan," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. PAMI-5, No. 5, September 1983. [7] B. Theodore, "Space- lling Curves: Their Generation and Their Application to Bandwidth Reduction," IEEE Transactions on Information Theory, vol. IT-15, pp. 658-644, November 1969. [8] P.N. Hil nger, "A high-level language and silicon compiler for digital signal processing," Proceedings IEEE Custom Integrated Circuits Conference, Portland OR, pp.213-216, May 1985. [9] S. Vernalde, P. Schaumont, I. Bolsens, H. De Man, J. Frehel, "Synthesis of high throughput DSP ASICs using Application Speci c Datapaths," DSP & Multimedia Technology, June 1994.

A HILBERT FRACTAL CODEC FOR REGION ORIENTED COMPRESSION OF COLOR IMAGES Jan Bormans 1 2, Serge Vernalde 2 , Jan Cornelis 1 , Ivo Bolsens 2 and Hugo De Man 2 1 ;

;

ETRO/BIIP, VUB, Pleinlaan 2, B1050 Brussels, Belgium 2 IMEC/VSDM, Kapeldreef 75, B-3001 Leuven, Belgium

1

Region-Oriented Compression (ROC) is a computation intensive emerging technique for very low bitrate image and video coding. The design of a Hilbert fractal codec, a key-component for ROC of color images, is discussed. The implementation eciency of the codec is critical since it determines the feasibility of the global compression scheme. We discuss the role of the Hilbert fractal codec in the global codec scheme and the high-level design methodology that leads to a successful implementation of the codec design.