A Low-Noise Interface for MEMS Vibration Gyroscope Based on a Novel Power-Efficient C/V Conversion Structure Hai Chu, Wengao Lu, M.X. Liu, Meng Zhao, X.L. Li, Dahe Liu, L.Y. Zhang, Zhongjian Chen and Yacong Zhang National Key Laboratory of Science and Technology on Micro/Nano Fabrication Peking University, Beijing 100871, CHINA
[email protected] circuits. Fig. 1(a) shows a widely used charge sensitive amplifier (CSA) structure. It needs a common mode feedback (CMFB) at amplifier’s input nodes [2]. Fig. 1(b) shows another C/V conversion stage using the fully capacitor bridge structure [3] [4]. This structure can simplify the implementation of the input CMFB. The calibration module is necessary, but not depicted in Fig. 1(a) and (b).
Abstract—A low-noise MEMS vibration gyroscope interface is presented in this paper. A novel capacitance to voltage (C/V) conversion structure is introduced, which consists of a fully differential capacitor bridge and an active filtering net. An autocalibration method is proposed, which can compensate the gyroscope mismatch to less than 2fF. We use a multistage noise shaping (mash) sigma-delta modulator to convert the analog signal to bit stream. The input referred noise of C/V conversion stage is 0.63 aF/√Hz at 8 kHz in simulation. The chip converts sensor output into bit stream with 106dB dynamic range.
In this paper we propose a novel C/V conversion circuit, which is detailed in part II. The C/V conversion circuit neither needs CMFB at amplifier’s input nodes, nor adds to the sensor element’s complexity. Furthermore, it is commonly more power-efficient compared to circuits shown in Fig. 1(b). Based on this C/V conversion structure, we designed an interface ASIC applied in high-resolution close loop MEMS vibration gyroscope. The system design consideration is detailed in part III. The major modules of the system except C/V conversion stage are detailed in part III, including the sigma-delta modulator and the auto-calibration module.
Keywords—low noise; capacitor bridge; gyroscope interface; sigma-delta modulation;
I.
INTRODUCTION
MEMS gyroscope constitutes one of the fastest growing segments in the sensor market relative to the fiber optic and ring laser gyroscopes [1]. The research on gyroscope is mainly towards improving resolution or reducing power consumption. This paper is focused on the high resolution switch capacitor (SC) interface circuits applied in close loop MEMS vibration gyroscopes.
II.
The schematic of the C/V conversion stage is depicted in Fig. 2. The circuits utilize gyroscope capacitors and on-chip compensation capacitors to form a capacitor bridge, realizing capacitance to current conversion. The voltage of node X and Y are fixed at Vcm. Every clock period, there will be a current pulse flowing into or out of X and Y. The rest of circuits in Fig. 2 form an active SC filtering net. The current pulses flow into the active SC filtering net, being amplified and filtered.
In low noise interface circuits’ design, the C/V conversion stage is very important because it decides the noise level of the whole system. The C/V conversion stage needs to reduce circuit noise to the minimum level and amplitude the signal to a proper amplitude such that the further signal process doesn’t bring too much SNR loss in the band of interest. Fig. 1 depicts 2 simplified schematics of conventional SC C/V conversion
In Fig. 2, Cs1 and Cs2 represent gyroscope capacitors. We assume Cs1 = C10 + ΔCs/2 and Cs2 = C20 - ΔCs/2, where C10 and C20 represent the DC values of the gyroscope capacitance at positive and negative end respectively, and ΔCs represents the variance of capacitance proportional to the modulated angular velocity signal. Ca1 and Ca2 are compensation capacitors whose values are set by an auto-calibration module. The autocalibration module will set Ca1 = C10 and Ca2 = C20 when the chip starts working. VRN and VRP are two low noise reference voltages, and (VRN+VRP)/2=Vcm. CP represents the parasitic capacitor of the sensor’s output and the amplifier’s input. Vcm and Vcmh represent input and output common mode voltages, respectively. The common mode voltages of the amplifier’s input and output nodes are different, so a power-efficient single
Fig. 1 simplified schematic of two common C/V conversion stages This work is supported by National Natural Science Foundation of China (No. 61473007 & No. 61475009).
978-1-4799-8391-9/15/$31.00 ©2015 IEEE
C/V CONVERSION STAGE
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H (s) =
Vout (s) (VRP − VRN ) CR = ΔCs (s) 1 + s / 2π f bw
(2)
fbw is the 3dB bandwidth, fbw= fsCR /2πCF. If s/2πfs ≪1, (2) can represents the frequency characters of (1). From (2) or the frequency response drawn in Fig. 3, we can tell this frontend circuit acts as a low-pass filter, whose bandwidth is determined by the ratio of CR/CF. The DC gain is (VRP−VRN)/CR. We could adopt a small CR to provide a relative high gain, and a large CF (CF≫ CP+Cs+Ca) to reduce kT/C noise. A small CR/CF ratio implies a high over sampling ratio (OSR), which reduces sampling noise. A large CF also eases the GBW demand for op-amp, which may further decrease the power consumption of op-amp. Compared to the circuits drawn in Fig. 1(b), with the same sampling frequency and gain, the circuits proposed in this paper can work with an op-amp with much smaller GBW. It generally reduces the power dissipation.
Fig. 2 the readout frontend circuits
Through this circuits we realize a high-gain power-efficient low-noise C/V conversion frontend with low-pass filtering function. With this structure, the further amplification can be abridged and the filtering task can be alleviated. It would improve circuit performance and simplify the circuit design. III.
Fig. 3. The frequency response of (1).
stage telescope op-amp can be adequate to provide a proper output swing. CF, CR and the 4 switches connecting to them form a damping integrator. CF functions as an integration capacitor. CR and the 4 switches function as a resistor providing damping. When S2=1, node X and Y reset to Vcm while the op-amp holds the last output. When S1=1, node X and Y is virtual ground (Vcm). If Cs1≠Ca1 (Cs2≠Ca2), there will be a current pulse flowing into or out of the damping integrator when S3 and S3B changes states. The output is insensitive to CP as long as the op-amp’s gain is high enough, for the voltage of node X and Y remain the same between S2=1 and S1=1. With some calculation we can get the transfer function (TF) of this circuit in Z-domain, which is shown by (1). With calculation, we can get the frequency response of (1), which is drawn in Fig. 3. Here we adopt CR/CF=0.03, and assume (VRP−VRN)/CR=1.
H ( z) =
Vout ( z ) (VRP − VRN ) CR = ΔCs ( z ) (1 + CF / C R ) − z −1CF / CR
SYSTEM DESIGN
In order to design a low noise interface circuit, we need both system level and circuit level consideration. In system level, a relative high sampling frequency is needed to reduce the high frequency noise folding. The signal must be amplified to an enough amplitude in C/V conversion before further signal process introduces extra noise. A high performance filter is necessary to decrease the noise out of signal band. We also need a high resolution analog to digital convertor (ADC) which brings reduction to signal to noise ratio (SNR) as small as possible. In circuit level, the amplifier must be carefully designed to reduce noise floor. A large capacitor may be needed at chargesensitive node to reduce kT/C noise generated by switches. And chopper or correlated double sampling technique may be needed to reduce flicker noise according to the frequency of the band of interest. In this paper, a novel low-noise and power-efficient C/V conversion circuit is proposed, which also provides high gain
(1)
Since the band of interest is 100Hz around 8 kHz, while the system clock frequency (sampling frequency) is about several MHz in our design, we can substitute z=1+s/ fs in (1) to see the frequency response of (1) in S-domain. fs represents the sampling frequency.
Fig. 4 block diagram of the MEMS vibration gyroscope interface
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and low-pass filtering function. The output signal of C/V conversion stage is send to a 2-1 mash ΣΔ modulator after further filtering. The 2-1 mash ΣΔ modulator is chosen for its good performance in noise shaping and stability. Since the ΣΔ modulator can convert the signal from analog domain to digital domain with very slight SNR loss in the band of interest, we could do signal process in the digital domain, such as high performance narrow-band filtering and demodulation. A high sampling frequency at 6.4MHz is adopted to reduce noise folding and provide a high over sampling ratio (OSR) for the ΣΔ modulation. The diagram of the whole system is depicted in Fig. 4. Due to fabrication tolerance and packaging stress, the fully differential capacitance Cs1 and Cs2 may not match perfectly. The mismatch would lead to an output DC offset [5], ranging from hundreds of millivolts up to a few volts [6], which would degrade the linearity of the interface circuits, or probably even exceed the circuit’s output range. So a calibration module is necessary in high resolution interface. In this paper we present an auto-calibration module which can compensate the gyroscope mismatch to less than 2fF. IV.
Fig. 5 shematic diagram of the auto-calibration module
AUTO-CALIBRATION AND ΣΔ MODULATION
In this part, the major modules except C/V conversion stage circuits are detailed, including the Auto-calibration module and the 2-1 mash ΣΔ modulator. A. The Auto-Calibration Module In the implanted chip, an on-chip auto-calibration module is built to compensate the mismatch. The diagram of the autocalibration module is shown in Fig. 5. The fully differential capacitor bridge structure is shared by the C/V conversion module and the auto-calibration module. The auto-calibration module will adjust the value of Ca1 and Ca2 when the chip starts working, making sure that Ca1=C10, and Ca2=C20. Through this calibration we eliminate the DC offset brought by the mismatch of sensor element and parasitic capacitor generated from packaging. S2, S3 and S3B remain the same definition in Fig. 2. When T=1, the circuits calibrate Cs1. And when T=0, the circuits calibrate Cs2. Ca1 and Ca2 are realized by 14-bit binaryweighted capacitor arrays. We take T=1 as an example. During S2=1, node X resets to Vcm. During S2=1, when S3 and S3B changes states, the voltage of node X (VX) will deviate from Vcm if Cs≠Ca. The difference of VX and Vcm is amplified by 2 fully differential amplification stages, and then sent to a latch comparator, which works at the falling edge of S1. The result of comparison is processed by a 14-bit successive approximation register (SAR) logic to adjust the binary-weighted capacitor array. After calibration, this module is shut down. The least significant bit of the capacitor array is 0.72fF. Every period the circuits calibrate one bit of the binary-weighted capacitor array.
Fig. 6 Diagram of ΣΔ modulatior
linear function of the PDM [2]. Since the sampling rate of the ΣΔ modulation is much higher than the signal’s rate, the sampling noise generated by high frequency noise folding into base band is greatly reduced [7]. In this paper we adopt a 2-1 mash ΣΔ modulator to process the C/V conversion stage’s output, for its good performance in noise shaping and system stability. The ΣΔ modulator’ behavior model is built with MATLAB Simulink to calculate the coefficients. The schematic diagram is depicted in Fig. 6. The quantizers are implanted with 2-stage latch comparators. The capacitor sharing method is applied to reduce total capacitance. The bit streams from the comparators are sent to the noise cancelation logic which is implanted with field programmable gate array (FPGA).
B. The ΣΔ Modulator Discrete time ΣΔ modulation can give out very high resolution and linearity digital output, which is a pulse density modulation (PDM) signal. The electrostatic feedback force is a
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V.
gain of readout circuits is adjustable manually, or by an on-chip gain-control logic according to the gyroscope capacitance. We input an 8 kHz sinusoidal angular velocity signal, and record the waveform of C/V conversion stage’s and ΣΔ modulator’s output, then we import the waveform to MATLAB to conduct spectrum analysis. The noise cancelation logic is realized with MATLAB Simulink.
SIMULATION RESULTS
The chip is fabricated with 0.18um deep N-well process. Since there is several large capacitors, such as CF in Fig. 2, we use top metal layers as capacitor plates and place transistors under the large capacitors to reduce whole chip area. The two axis interface circuits along with 2 ΣΔ modulators occupy 1.4mm*2.3mm area. The layout is shown in Fig. 7. Part of the calibration module is under capacitor Cf of C/V conversion module, so they are overlapped in fig. 7.
Fig. 8 depicts the power spectrum density (PSD) of readout circuits’ output at -3.88dB full scale (dBFS). The residual offset is about -63.73dB, which is 1.30fF equivalent to input. In the periodic noise simulation with spectre, the input referred noise is 0.63 aF/√Hz @8KHz. The dynamic range of C/V conversion is 110.03 dB.
We use Verilog-A to describe the sensor element model in simulation. The DC value of the gyroscope capacitance ranges from 1.6pF to 10pF each end. The variable value of the gyroscope capacitance is no more than 5% of its DC value. The
The ΣΔ modulator converts the analog output of C/V conversion into bit stream. Fig. 9 shows the PSD of the ΣΔ modulator’s output. We can see that the ΣΔ modulation decrease less than 4 dB SNR of the C/V conversion’s output. With the bit stream of ΣΔ modulator’s output, we can implement high performance filtering and demodulation in digital domain. The dynamic range of the readout circuits and ΣΔ modulator is 106.32 dB. VI.
CONCLUSION
In this paper, we propose a low noise interface ASIC for application in close loop MEMS vibration gyroscopes. A novel C/V conversion stage is introduced, which is low-noise, powerefficient and high-gain. An on-chip calibration module is introduced, which can compensate the mismatch of gyroscope to less than 2fF. We utilize a 2-1 mash ΣΔ modulator to convert the analog signal into bit stream, which brought about only 4 dB SNR loss in simulation. The chip converts sensor output into bit stream with 106.32dB dynamic range.
Fig. 7. The layout of the chip (screenshot)
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[3] Fig. 8 PSD of the C/V conversion’ output [4]
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[7] Fig 9. PSD of ΣΔ modulator’s output
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