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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998

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A Multimode Digital Detector Readout for Solid-State Medical Imaging Detectors Colby D. Boles, Bernhard E. Boser, Bruce H. Hasegawa, Member, IEEE, and Joseph A. Heanue, Member, IEEE

Abstract—A multipurpose digital detector readout for medical imaging applications is presented. The readout is capable of measuring both current and charge, allowing a single detector array to perform imaging functions previously accomplished with two separate machines. The circuit employs a variable rate analog-to-digital converter (ADC) to measure current over a 130dB dynamic range in a 1 kHz band and resolve charge pulses down to 360e0 at 100 000 events/s. Detector currents of up to 7A and charge pulses as large as 25 fC can be measured. A low-noise charge sensing amplifier (CSA) is combined with digital pulse shaping to optimize the noise performance and flexibility of the charge measurements. Fabricated in an 1.2 m complimentary metal-oxide-semiconductor (CMOS), the circuit occupies 1.5 mm2 and dissipates 11 mW/channel from a 5 V supply.

TABLE I REQUIRED PERFORMANCE SUMMARY

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Index Terms— Analog-digital conversion, biomedical nuclear imaging, biomedical X-ray imaging, radiation detector circuits, sigma–delta modulation.

I. INTRODUCTION

X

-RAY computed tomography (CT) and single photon emission computed tomography (SPECT) are two medical imaging modalities that provide complementary diagnostic information. SPECT assesses physiological function by measuring the uptake of -ray emitting radio-labeled tracers as a function of time and location within the body. The ability to radio label a wide variety of pharmaceuticals allows SPECT to assess physiological function and provides clinicians with quantitative information to diagnose malignant disease, as well as dysfunction of the brain, heart, and other organs. In contrast, CT imaging systems create high resolution three-dimensional X-ray images that provide anatomical definition with a spatial resolution of 1 mm or better, but lack direct physiological information. Recently, it has been recognized that combining CT and SPECT in a single machine would improve the correlation of these two data sets [1]. In addition, spatial information from CT images can be used as a priori information in the reconstruction and analysis of SPECT images, which can greatly improve the quantitative accuracy [2] of radionuclide uptake measurements performed with SPECT. Manuscript received September 1997; revised November 28, 1997. This work was supported by Whitaker Foundation Grant M1826. C. D. Boles and B. E. Boser are with the Bioengineering Graduate Group and the Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720 USA and the University of California at San Francisco, San Francisco, CA 94143 USA (e-mail: [email protected]). B. H. Hasegawa is with the Bioengineering Graduate Group, University of California at Berkeley, Berkeley, CA 94720 USA and is also with the Physics Research Laboratory, Department of Radiology, University of California at San Francisco, San Francisco, CA 94143 USA. J. A. Heanue is with Cardiac Mariners, Inc., Lost Gatos, CA 95030 USA. Publisher Item Identifier S 0018-9200(98)02227-6.

Unfortunately, the measurements made in SPECT and CT imaging are fundamentally different and pose significant challenges to creating combined detector and detector readout electronics [3]. SPECT imaging requires that the detector channels count individual -ray events, which produce small quantities of charge in proportion to their energy. These charge pulses range from 0–20 fC and occur at rates in the range of 10–1000 photons/s/pixel. The charge (energy) from each ray must be measured with a resolution better than of 0.2 fC (1350e ) for low image noise and good contrast [4]. In comparison, CT detector channels measure X-ray events at a relatively high flux ( 10 photons/s/detector) producing a continuous current due the overlapping of individual charge pulses. This photon flux can vary over a 140 dB dynamic range, producing detector currents ranging from 1 pA–10 A and must be measured with better than 74 dB SNR (signal to noise ratio) at a 2 kHz sampling rate [3]. Table I summarizes the performance goals for the proposed combined SPECT/CT detector readout system. The combination of SPECT and CT in a single machine cannot be accomplished with the medical detectors used in current commercial imaging systems. Detectors in these systems are based on scintillation followed by light detection with photomultiplier tubes or photodiodes, an arrangement that limits their size, response speed, and energy resolution. In addition, the wide variation in dynamic range and speed requirements between SPECT and CT detector electronics has limited previous integrated solutions to only one of these applications [5], [6], or to not include analog-to-digitial (A/D) conversion on chip [7]. However, solid-state detectors are capable of measuring the X- and -ray signals produced by these two imaging systems and have adequate count-rate performance, dynamic range,

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998

Fig. 1. System overview.

and spatial resolution to incorporate both detection tasks in a single device [3]. Unlike present detector electronics that use analog processing of the detector signal, the ability to digitize the detector signal on chip would provide the flexibility needed to perform both CT and SPECT imaging while also allowing high-channel density and simplified interfacing. Therefore, our goal is to develop integrated complimentary metal–oxide–semiconductor (CMOS) detector electronics that will allow an imaging system with a single solid-state detector array to acquire both SPECT and CT images, providing increased functionality and resolution. This is accomplished by designing an integrated circuit (IC) that interfaces directly ADC that meets the to the detector and features a requirements of the SPECT and CT modes by varying the sampling rate of the converter and digital post-filtering. The 1-b digital output simplifies the interfacing of many detectors to the digital processor that performs the filtering and pulse detection.

step is detected in the filtered output and its height is measured. This step height is proportional to the detector charge that arrived at the CSA. After the step is measured, the CSA is reset to allow new pulses to be integrated without causing CSA saturation. The processor tallies the number of events as a function of their charge (energy). The SPECT image is reconstructed based on the number of events which fall within a specified energy window. 2) CT: Current produced by the detector diode is routed via an MOS switch directly into a current input node of modulator. The modulator codes the current as a the 1-b digital stream at sampling rates up to 10 MHz, which is then sent to a digital decimation filter to convert the data into a 20-b/2 kHz digital current measurement. This current is proportional to the X-ray flux on the detector which is used to reconstruct the CT image. B. SPECT Performance Considerations

II. SYSTEM DESIGN A. Principle of Operation The complete detector readout system (Fig. 1) consists of a reverse-biased diode detector, the readout IC, and digital post-processing/control electronics. The IC includes a charge sensing amplifier (CSA) and a second-order modulator modulators to trade resolution for loop. The ability of bandwidth allows this single ADC to function as both a 20b/2 kHz (CT) and a 8-b/500 kHz (SPECT) converter by simply varying the digital post-filtering. The IC functions in the two imaging modes as follows. 1) SPECT: Charge pulses produced by the detector are routed via an MOS switch to the CSA. The CSA serves to provide high signal gain by integrating the charge pulse on small capacitor to create a voltage step that is measurable by the ADC. The modulator codes the CSA output voltage as an 1-b/10 MHz digital stream which is fed to the digital processor. The processor optimally filters the voltage step to minimize the noise due to the detector, CSA, and ADC. The voltage

1) SPECT Noise Sources: Fig. 2 illustrates three significant sources of noise in the SPECT pulse-detector system, namely detector noise ( ), CSA thermal and flicker noise ( and ), and quantization noise ( ) from the modulator. To determine the overall system resolution, each of the noise sources is first analyzed individually. i) Detector shot noise due to leakage current and thermal noise from the biasing resistor . In the frequency range of interest, these noises act in parallel and are given by (1)

For the high purity germanium (HPGe) detector array intended to be used in our experimental imaging system, pA and M , making the biasing resistor the dominant source of noise. ii) Thermal and flicker noise from the MOS transistor(s) of the CSA. Assuming this noise is dominated by a single

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Fig. 2. SPECT noise sources.

device, these noises will be (2) (3) These noises can be transformed into equivalent inputreferred currents (4) (5) is the total capacitance where at the input node, comprised of the detector, integrating, and amplifier capacitances, respectively. iii) Quantization noise from the modulator. Inputreferred, this is can be modeled as (6) where is the input-referred digital-to-analog converter (DAC) step size in units of charge, is the sampling rate, and is the modulator order [8]. 2) Calculating SPECT ENC Performance: The noise performance of a charge detection system is usually specified in terms of its input-referred rms charge error, also known as the equivalent noise charge (ENC). The ENC of the SPECT system is a function of both its noise sources and the pulse-shaping filter used, making optimization difficult. The ENC can be determined using time-domain techniques by first separating the input-referred noise sources according to their dependence on frequency [9], [10]. This process is straightforward since each of the noise sources identified previously is some integral power of frequency , and its noise can be determined according to , coefficient where will be referred to as the frequency order. The ENC can then be determined by weighting each of the noise coefficients by the sensitivity of the pulse-shaping function to signals of frequency order and summing the power [9] ENC

(7)

represents a time scale independent measure of a where pulse shaper’s sensitivity to noise of frequency order . That

Fig. 3. ENC versus pulse-shaping time.

is, is the degree to which the pulse shaper amplifies noise of a given spectral characteristic . The time scale parameter is the time width of the pulse shape used and determines the maximum counting rate before pulses begin to overlap each other and cause measurement errors (referred to as pulse pileup). In our analysis, is designated as the time width at which the shaping pulse had decayed to 0.1% of its maximum value, thereby ensuring that no appreciable pulse pileup would count rate. Substituting the noise sources from occur at a our analysis in (1) and (4–6) into (7), the total noise is ENC (8) As can be seen in (8), obtaining a minimum ENC at a given pulse-counting rate requires carefully balancing the pulse shape (which determines the coefficients) and the relative contributions of the different noise sources in the design. Conversely, if the pulse shape and noise contributions are determined, there exists an optimum pulse-shaping time which minimizes noise. Fig. 3 shows a simulation of predicted ENC as a function of shaping time for the Hanning shaping filter and noise budget used in the prototype design. From Fig. 3 it can be seen that the system is designed to give the minimum ENC near the 100 000 CPS (counts per second) ( s) target specification. An intuitive explanation of the effect has on ENC as shown in (8) and Fig. 3 is as follows: A charge pulse from the

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detector lasts for only a few nanoseconds and can be viewed as a wide-band signal of fixed energy. Decreasing widens the pulse-shaper bandwidth and increases modulator and CSA thermal noise quicker than the detector signal increases, resulting in increased ENC from these sources. Increasing reduces the bandwidth and decreases the signal from the detector quicker than it reduces detector noise, resulting in an increased detector ENC. By the same analysis, it can be shown that flicker noise from the CSA changes with bandwidth in equal proportion to the detector signal and hence its ENC is independent of . Using a digital finite impulse response (FIR) filter implemented in a digital signal processor (DSP) allows the use of more optimal pulse shapes that are not realizable with analog filters used in conventional SPECT systems. These more optimum shapes provide reduced ENC and increased count rates from the same detector and electronics. The ability in software permits optimum to vary the shaping time noise performance to be achieved, even if the detector and readout IC noises deviate from those determined at design time. By reducing the shaping time from optimal, the ability to operate at increased count rates with reduced resolution is also provided. 3) Calculating Pulse-Shaper Performance: In order to determine pulse-shaper performance, its sensitivity to noise sources of different frequency orders must be calculated. The filter sensitivity coefficient for a pulse shape of pulse width can be determined by evaluating the integral [9]

Fig. 4. ENC: Analysis (solid line) versus simulations (dashed and dotted lines).

(9) where normalizes for the pulse-shaper width . This integral is difficult to evaluate in the closed form for odd values of (e.g., flicker noise) due to the presence of a fractional derivative. However, this expression can be evaluated discretely with the use of a series expansion. The pulse-shaping filter determined by analysis and simulation to give the best ENC performance was a Hanning window given by for

Hanning

(10)

that when combined with the integrate and reset function of the CSA, gives an overall pulse-shaping function Hanning

(11)

where * represents convolution and is the box function. This shaping function has the following noise sensitivity coefficients: (12) These can be substituted to evaluate ENC versus shaping time as shown in Fig. 3.

Fig. 5. CT noise sources.

4) Simulating SPECT Performance: To verify the ENC analysis above and to model additional effects due to nonlinearities, a complete discrete-time model of the SPECT system was constructed the C language and simulated for modulator. The simulator over 32 million samples of the modulator, and digital pulse models the detector, CSA, processor, including all noise sources, as well as nonidealities such as finite amplifier gain and output swing. Fig. 4 shows that these simulations (dashed and dotted lines) are in general agreement with the previous ENC analysis (solid line) except at the short shaping times where quantization noise dominates. Simulations that include detector charge events (dashed line) indicate that the quantization noise model in (6) used in the analysis (solid line) underestimates by 50% the noise produced by the modulator when large input signals ( 0.43 ) from the CSA are present. In simulations with no input to the detector (dotted line), quantization noise is matched more closely by (6). C. CT Performance Considerations modulator operating in CT A conceptual model of the mode is shown in Fig. 5. In the CT mode of operation, current from the detector diode feeds directly into the summing node

BOLES et al.: MULTIMODE DIGITAL DETECTOR READOUT FOR SOLID-STATE DETECTORS

of the first integrator of the modulator. This continuous time input avoids sampling capacitor nonlinearities and allows all circuitry to be contained within the loop to achieve low distortion. A switched capacitor feedback network has been chosen over a current source implementation due to the clock jitter sensitivity of the latter. 1) CT Noise Sources: Noise must be carefully minimized to meet the 120 dB+ dynamic range requirement of CT mode modulator and operation. The quantization noise of the thermal noises present at the input node are the dominant factors to consider. Quantization noise is reduced by increasing the oversampling ratio or modulator order, but the thermal noises present at the input are unaffected by these changes. Thermal noise from the feedback current source DAC , imposes a fundamental limit on performance. This noise is given by

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(a)

where (13) and is present in both current source and switched capacitormodulator with a 1-b DAC, the based DAC circuits. In a feedback current is always equal in magnitude to the full . With A and V, this scale value corresponds to 6.8 pA of noise in a 1 kHz bandwidth, limiting dynamic range to 120.2 dB. When a switched capacitor DAC is used, thermal and flicker noise from the input stage causes the input node to deviate from virtual ground and modulates the feedback current. This contributes current noise as

(b) Fig. 6. The effect of variable sampling rate on (a) SNR and (b) overall dynamic range with (dashed lines) and without (solid lines) amplifier noise.

given by

(14) and can further limit the dynamic range. 2) Overcoming Dynamic Range Limitations: In order to reduce DAC and amplifier noise with a fixed , the average value of must be reduced. One approach is to use a when multilevel DAC that will decrease the average the input is small [5]. This approach requires a DAC with linearity equal to the ADC resolution and increases complexity substantially. The solution adopted here is to reduce the full scale for small inputs by operating the modulator at a slower sampling rate which reduces the current delivered by the switched capacitor DAC. In CT applications, this type of multiranging is feasible because the input signal does not vary over a wide dynamic range in a short time period. This allows the digital processor time to identify changes in signal range and change the sampling rate accordingly. Since the feedback current is proportional to the sampling clock , and that clock can be easily divided by exact powers of two, good linearity can be maintained between ranges. If is reduced by a factor for small input signals, the new overall dynamic range is

DR

(15)

where denotes the value of a parameter at the original sampling rate . This equation dictates two important effects: 1) reducing the sampling rate decreases DAC and amplifier noise but increases the quantization noise of the modulator, implying that quantization noise will eventually dominate and limit the maximum dynamic range, and 2) amplifier noise decreases at a faster rate than noise from the DAC, making it possible to have relaxed amplifier noise requirements and still achieve nearly the same dynamic range. Fig. 6 illustrates these two effects and shows that it is possible gain an additional 24 dB of dynamic range by decreasing the sampling rate of the modulator even if amplifier noise exceeds DAC noise by 12 dB at the original sampling rate. These simulations are based on a second-order modulator with MHz, A, pA, and V.

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Fig. 8. CSA ENC versus input transistor size.

Fig. 7. CSA schematic.

III. CIRCUIT DESIGN A. CSA Design 1) Minimizing Noise: Much of the CSA design shown in Fig. 7 is driven by the need to minimize noise. The amplifier uses a single-ended input (M1) in a folded-cascode topology to reduce noise by a factor of 3 dB compared to a differential amplifier. A PMOS input transistor is used because of its significantly lower flicker noise coefficient compared to NMOS devices. The size of the input transistor can be optimized to yield minimum noise for a given external . By taking (4) and substituting capacitance, and , we find that thermal noise is minimized when is minimum . Similarly, using (5) we find length and that flicker noise is minimized when and is independent of the ratio. The optimal for best overall performance must lie between and and requires substituting actual device parameters and calculating the ENC as described previously. Fig. 8 shows calculated amplifier ENC as a function of for detector capacitances of 2, 7, and 15 pF. In all cases ENC is minimized with . In order to allow the CSA to give a reasonable performance with detector capacitances ranging from 2–15 pF, a compromise value of pF was chosen. To ensure that M1 is the dominant source of noise in the amplifier, current sources M2 and M5 have large to reduce and increased channel length for low flicker noise. The bias circuits for the CSA utilize large reference currents and on-chip bypass capacitors to minimize noise and crosstalk. The CSA and its bias circuits operate on a separate power supply from the modulator and digital logic to reduce

the coupling of switching transients. The detector input pad and the SPECT/CT signal routing switches are guarded by the n-well body/source of M1 to further prevent coupling to the input from the substrate. In order to maintain the same input node voltage as in the CT mode, the source of M1 is biased to 3.5 V to obtain 2.5 V at the CSA input. 2) Speed: The CSA must accurately integrate pulses in significantly less time than the 10 s nominal digital pulseshaping filter. M3 serves as a cascode device for the drain of M1 to improve both the speed and gain of the amplifier. This , due to the large drain capacitance device is sized for high of M1 and the stability requirements during the reset phase, which is described later. The high of M1 required for noise allows the CSA to have a time constant ns under the worst case conditions of pF. This is sufficiently fast to allow digital pulse-shaping times as low as 1 s to be unaffected by the CSA. However, sampling the CSA at MHz would output with a capacitor into the require that ns for complete settling. By placing a high speed buffer between the CSA output and input, fast sampling capacitor settling is achieved and the CSA output loading is reduced. 3) Reset: The CSA requires a reset circuit to keep its output from saturating due to incoming charge pulses and detector leakage current. A reset circuit is also necessary to provide a dc path to bias the gate of M1. A simple MOS shorting is not a practical reset solution, as it makes switch across the CSA difficult to stabilize. When the switch is closed, the feedback factor will increase from its maximum ( ) value of 1/200 to as large as 1, requiring that the nondominant pole of the CSA be placed at a frequency 200 times higher than is necessary for normal operation. By using the switched capacitor shown in Fig. 7 to reset , only increases is connected to . With each by a factor of 11 when successive three-phase clocking cycle of the reset switches, settles 90% closer to the value programmed by , an adjustable voltage source derived off-chip. Within four clock cycles (400 ns) the CSA input to output voltage is within 0.1% . This reset scheme also allows the CSA’s output of the voltage to be set independently from its input, allowing the

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Fig. 9. SD modulator topology.

full output swing to be utilized. The reset switches are made minimum size to reduce charge injection and are controlled by a clock driver powered by the CSA supply to help prevent supply noise from other circuits from coupling into the CSA. 4) Gain: The low feedback factor in the CSA due to the small 20 fF integrating capacitor and large detector capacitance requires that the open loop amplifier gain be significantly for accurate and linear charge integration. higher than With pF, approaches 1/1000 and the CSA requires 100 dB of gain to achieve a 1% charge gain error. Fortunately, such charge gain errors are systematic and are removed in the calibration of the detector channel. Variations in open loop gain with CSA output voltage introduce nonlinearites that are more difficult to compensate and must be minimized. The CSA has been designed to achieve 84 dB of gain with only 0.6% gain variation over a 350 mV output swing, causing a charge measurement error of only 0.04% for a 7 fC input charge. Future designs may include active cascodes to further increase gain at the expense of significant additional power consumption to guarantee stability [11]. This is due to the large load presented by the cascode device and the high worst-case feedback factor during the reset phase of the CSA. B.

Design

modulator utilizes a 1) Architecture: The second-order conventional switched-capacitor architecture with some modifications to allow both SPECT and CT mode operation (Fig. 9). In SPECT mode, the modulator operates in a fully differential configuration and samples the output of the CSA buffer ( ) and a voltage reference ( ) at MHz. In the CT mode these sampling capacitors are disabled and current from the detector is fed into one summing node of the integrator ( ) as a continuous-time input while the other node ( ) is connected to the common mode ground. The charge delivered by the DAC’s in this configuration is one-half of that in the SPECT mode and the inner loop feedback (hidden within the H(z) block) is reduced by one-half to maintain the same loop transfer function. 2) Integrators: The CT mode of operation dictates much of the design of the first integrator. With a full scale input current of 7 A at MHz, the first stage integrating capacitors must be at least 1.4 pF to prevent clipping due to overload. The first integrator must settle accurately in as little as 50 ns

Fig. 10. Die photo.

with up to 15 pF of detector capacitance at its input. Amplifier gain needs to be better than 60 dB in each integrator in order to attenuate quantization noise in the passband. Thermal and flicker noise from the first integrator must be less than 10 V in the passband to prevent a loss of dynamic range. With these considerations in mind, differential PMOS-input folded cascode amplifiers were used for both integrators, the first integrator utilizing large input transistors for low noise and high speed. Both integrators achieve over 66 dB gain and settle to 120 dB in less than 100 ns. 3) Clocking and Output: The modulator operates from a differential four-phase clock which is generated with differential logic for improved symmetry between complementary outputs [12]. These phases are derived from an off-chip clock which is connected differentially to minimize clock feedthrough to the analog circuitry. Similarly, the digital output of the dynamic comparator is driven off-chip by a differential current source driver for reduced output to input coupling.

IV. EXPERIMENTAL RESULTS A. Fabrication and Testing A prototype IC was fabricated using a 1.2 m two-poly, two-metal analog n-well CMOS process and is shown in Fig. 10. Although only one detector channel was placed on the 2.2 2.2 mm die, the design layout is modular to allow easy replication into a multichannel version that utilizes shared biasing circuits for reduced power. In order to minimize noise and AC line interference in the testing setup, the test circuit operates from battery power and the digital output is optically coupled to a computer for analysis. Table II summarizes the measured results.

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TABLE II MEASURED PERFORMANCE SUMMARY

Fig. 12. Measured CT SNR versus input level for six sampling rates.

Fig. 11.

Measured CT output FFT spectrum.

B. CT Measurements CT mode operation was tested by applying a 700 Hz sinusoidal voltage input through a 40 M resistor and processing the 1-b digital output with a fast Fourier transform (FFT). Fig. 11 shows the FFT of a 15.28 dBFS input with MHz indicating a noise floor of 108 dBFS and very low distortion at 122 dB. Flicker noise from the first integrator dominates the noise floor in this figure but is reduced by 6 dB with each halving of the sampling rate. Fig. 12 shows the SNR versus the input level for six sampling rates and verifies that flicker noise is reduced. By lowering the sampling rate from 10 MHz to 625 kHz, an additional 24 dB of dynamic range is gained giving an overall dynamic range of 130 dB in a 1 kHz bandwidth. At sampling rates below 625 kHz, the converter becomes quantization noise limited; further reduction of consequently yields no improvement of the dynamic range. These results are in close agreement with the analysis shown in Fig. 6 and indicate that the prototype comes within 3 dB of the dynamic range limit imposed by DAC and quantization noise. C. SPECT Measurements SPECT performance was tested by applying input charge via a capacitively coupled pulse-forming network. Fig. 13 shows

Fig. 13. Digitally filtered SPECT mode output of integrate test of CSA.

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during reset and

a sample of the output of the CSA after being digitized by ADC and passing through a 10 s digital pulsethe shaping filter. In this repetitive test, the CSA is first reset and fC, is applied and measured. then a test charge, The reset phase has been elongated from its 400 ns typical value in this test so that it can be clearly seen after the digital filtering. The voltage step at the end of the reset phase indicates 9 fC of charge injection from the reset switches. The detector charge is determined by the difference in CSA output before and after the pulse arrival and hence is insensitive to variations in the dc level of the CSA due to the reset circuit or other sources. Fig. 14 shows a the distribution of 16 000 such charge measurements and indicates that the ENC of the SPECT system is only 0.058 fC or 360e with a 25 fC input capacitance. This input capacitance of 25 pF is significantly

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V. CONCLUSION A prototype detector readout circuit has been demonstrated which allows two complementary medical imaging techniques to be performed with a single detector system. Its emphasis on digital-domain processing increases flexibility and performance to accommodate different system needs. A modulator is uniquely suited to combining these applications due to its ability to trade off speed for resolution. Varying the sampling rate of the modulator gained an additional 24 dB of dynamic range in the CT mode while optimized digital pulse shaping and CSA design allowed SPECT charge resolution to reach 360e . REFERENCES Fig. 14. test.

Distribution of measured charge from SPECT reset and integrate

Fig. 15. ENC: measurement (circles) versus simulation (dashed line) and analysis (solid line).

higher than the 2 pF optimum due to limitations in the test circuit layout and the pulse-forming network. Smaller input capacitances are expected to reduce the ENC accordingly. The sensitivity of the CSA is determined to be 60 mV/fC which is 20% higher than the 50 mV/fC design value and is probably due to an inaccurate estimation of the 20 fF integrating capacitance in the layout. Fig. 15 compares the measured ENC versus pulse-shaping time (circles) with simulation (dashed line) and analysis (solid line), using the same input capacitance and signal size. The pulse-forming network has negligible leakage current and hence no detector noise was present in the tests or included in the simulation or analysis. Simulation closely matches the measured performance in the quantization, thermal, and flicker noise dominated regimes of operation. In the worst case, simulation underestimated thermal and flicker noise by 25%. This error could be attributable to inaccurate measurement of the input capacitance and/or variability in the specified flicker noise coefficient.

[1] T. Lang, B. Hasegawa, S. Liew, S. Reilly, J. Brown, and E. Gingold, “Description of a prototype emission-transmission CT imaging system,” J. Nucl. Med., vol. 33, pp. 1881–1887, 1992. [2] K. Kalki, J. Brown, S. Blankespoor, and B. Hasegawa, “Myocardial perfusion imaging with a correlated X-ray CT and SPECT system: An animal study,” IEEE Trans. Nucl. Sci., vol. 43, pp. 2000–2007, 1996. [3] J. Heanue, “Detector and electronics design considerations for an emission-transmission medical imaging system,” Ph.D. dissertation, University of California at Berkeley, 1996. [4] J. Heanue, J. Brown, H. Tang, and B. Hasegawa, “A bound on the energy resolution required for quantitative SPECT,” Med. Physics, vol. 23, no. 1, pp. 169–173, 1996. [5] C. Thompson and S. Bernadas, “A digitally corrected 20b delta-sigma modulator,” in Digest Tech. Papers, 1994 Int. Solid-State Circuits Conf., pp. 194–195. [6] S. Tedja et al., “A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces,” J. Solid-State Circuits, vol. 30, pp. 110–119, 1995. [7] J. Heanue, B. Boser, and B. Hasegawa, “CMOS detector readout electronics for an emission-transmission medical imaging system,” IEEE Trans. Nucl. Sci., vol. 42, pp. 1133–1137, 1995. [8] J. Candy, “A use of double integration in sigma delta modulation,” IEEE Trans. Commun., vol. COM-33, pp. 249–258, 1985. [9] F. Goulding, “Pulse-shaping in low-noise nuclear amplifiers: A physical approach to noise analysis,” Nucl. Instrum. Methods, vol. 100, pp. 493–504, 1972. [10] W. Sansen and Z. Chang, “Limits of low noise performance of detector readout front ends in CMOS technology,” IEEE Trans. Circuits Syst., vol. 37, pp. 1375–1382, 1990. [11] K. Bult and G. Geelen, “A fast-settling CMOS op amp of SC circuits with 90-dB DC gain,” J. Solid-State Circuits, pp. 1379–1384, Dec. 1990. [12] S. Lewis, “Modeling and design of high-resolution sigma–delta modulators,” Ph.D. dissertation, Stanford University, Stanford, CA, Aug. 1993.

Colby D. Boles was born in Dunedin, New Zealand, on November 1, 1969. He received the B.S. degree in bioengineering from the University of California at Berkeley in 1991. Currently, he is working toward the Ph.D. degree in bioengineering at the University of California at Berkeley and University of California at San Francisco and the M.S. degree in electrical engineering at the University of California at Berkeley. From 1990 to 1993, he was a Development Engineer at Digital Instruments, Santa Barbara, CA, where he developed new imaging techniques for scanning probe microscopes based on intermittent surface contact. His research interests include high performance ADC design for medical imaging applications and improved signal processing techniques for neurophysiologic patient monitoring.

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Bernhard E. Boser received the Diploma in electrical engineering from the Swiss Federal Institute of Technology (ETH) in Zurich, Switzerland, in 1984 and the M.S. and Ph.D. degrees from Stanford University, Stanford, CA, in 1985 and 1988, respectively. From 1988 to 1991, he was a Member of Technical Staff at AT&T Bell Laboratories working on VLSI implementations of artificial neural networks and algorithms for automatic learning. In 1992, he joined the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley, where he is now an Associate Professor as well as an Associate Director of the Berkeley Sensor & Actuator Center. His current research interests are in the areas of integrated circuits for data conversion and communication, and on the design and fabrication of micromechanical systems.

Bruce H. Hasegawa (M’89) received the B.S. degree in physics and mathematics and the M.S. degree in mathematics from California State, Fresno, in 1973 and 1974, respectively. He also received the M.S. degree in radiological sciences from the University of Colorado Medical Center, Boulder, in 1980 and the Ph.D. degree in medical physics at the University of Wisconsin, Madison, in 1984. He is currently an Associate Professor in the Department of Radiology at the University of California at San Francisco. His research interests include combined CT/SPECT instrumentation, correlation of structural and functional diagnostic image data, and quantitative SPECT imaging.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998

Joseph A. Heanue (S’93–M’96) received the B.S. degree in physics from the Massachusetts Institute of Technology, Cambridge, in 1991 and the Ph.D. degree in electrical engineering from the University of California at Berkeley in 1996. He was a Postdoctoral Researcher at the Xerox Palo Alto Research Center, Palo Alto, CA, and he is currently working on X-ray detector instrumentation as a Member of the Technical Staff at Cardiac Mariners, Inc., Lost Gatos, CA. His research interests are in the areas of semiconductor sensors and integrated electronics for imaging applications.