A PARAMETERIZED GENETIC ALGORITHM IP CORE DESIGN AND IMPLEMENTATION K.M. Deliparaschos1, G.C. Doyamis2, S.G. Tzafestas National Technical University of Athens (NTUA), School of Electrical and Computer Engineering (ECE)
ICINCO 2007
NTUA Athens
Introduction A parameterized GA IP core is designed and implemented on hardware, achieving impressive time–speedups when compared to its software version. The parameterization stands for the number of population individuals and their bit resolution, the bit resolution of each individual’s fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in an Spartan 3-1500 FPGA chip with the use of VHDL and advanced synthesis and place and route tools. The designed GA IP core achieves a frequency rate of 92 MHz and is evaluated using the Traveling Salesman Problem (TSP) where a successful solution to it has been found, as well as several benchmarking functions.
System sub-blocks
Technological Approach
Control Module
Overall System Architecture clk clk rst_n
rst_n
run 2 mut_out run
genom_lngt
seed load ga_fin index elite_null decode valid addr_1 we1 addr_2 we2 cross_out sel_out run 1 done data_out1 data_in data_out2 datavalid next_gene run 3
clk rst_n run seed load
genom_lngt
mut_method
2
Control Module
run_ga
max_fit
RNG
out
rst_n
clk rst_n
clk rst_n
Fitness elite_indexs in_gene Evaluation gene&scr index elite_null Module rd decode valid fit_sum max_fit
log2(pop_sz)
log2(pop_sz)
genom_lngt + score_sz
RAM 1 data_in addr data_out we
clk rst_n cont
mut_offspring
out RNG
rng
mut_method
Selection Module
rd
Mutation mut_point Module
clk rst_n 2 run seed load
genom_lngt + mut_res seed_2
fit_limit_reached
in_gene
genom_lngt + score_sz
log2(2*(pop_sz-elite))
Crossover Module
ga_fin
genom_lngt + mut_res genom_lngt
max_fit
2*log2(genom_lngt) log2(pop_sz) + score_sz
Mutation Module
best_gene
score_sz
clk rst_n run seed load
clk rst_n
RNG 1 out scaling_factor_res
done
Observer clk Module fit_limit
cross_method
genom_lngt elite*log2(pop_sz)
elite_offs
ready signals (rd) from all modules
Fitness Evaluation Module
fit_sum
clk rst_n
in_gene
Selection Module
rng valid next_gene
RAM 2
sel_parent rd
genom_lngt
data_in addr data_out we
genom_lngt
cross_offspring rd clk rst_n cross_points cont in_gene1 rng in_gene2
Crossover Module
out RNG
clk rst_n 3load seed run
Observer Module seed_3
2*log2(genom_lngt)
cross_method
Random Number Generators
reached
2
seed_1
Random Access Memory (RAM)
genom_lngt scaling_factor_res
genom_lngt genom_lngt
Experimental Results
IP Core Parameters
FPGA Design Summary
TSP Evaluation: Map of the cities used, Population size vs. Generations
A GA IP core was developed with the following characteristics
Utilization of the implemented GA
Parameter name genom_lngt
generations
score_sz pop_sz
Description Chromosome length in bits
Fitness value bit resolution Population size Bit resolution of the random scaling_factor_ number used in RWS res algorithm elite Number of elite children mr Mutation rate
1000
Possible Value 16
16 32 4
2 80
Logic Utilization
GA
GA adapted to the TSP
Slice Flip Flops
681 (2%) 1045 (3%)
4 input LUT’s
1.086 (4%) 1630 (6%)
Logic distribution Occupied Slices
892 (6%) 1305 (9%)
4 input LUT’s
1.116 (6%) 1686 (6%)
Used as logic
1.086
1630
Used as route-thru
6
4
Used as 16x1 RAMs
24
52
Bonded IOBs
59 (12%) 53
(10%)
MULT 18x18s
1
(3%) 3
(9%)
GCLKs
1
(12%) 1
(12%)
100
Solution of the burma14 benchmark
10
Contacts 1,2 Contact
1 4
8
16
32 pop_sz
Software vs. Hardware GA Version Hardware (11 nsec) Software (Pentium 4 3,2 GHz 1Gb RAM )
Time(msec) 1,702 18.783
Authors:
K.M Deliparaschos,
[email protected] G.C Doyamis,
[email protected] National Technical University of Athens School of Electrical & Computer Eng. Division of Signals, Control and Robotics, Iroon Polytechniou 9, Zografou Campus, Athens GR-15773, Hellas.
