A VLSI 8x8 MIMO Near-ML Decoder Engine Geoff Knagge, Mark Bickerstaff, Brett Ninness, Steven R. Weller and Graeme Woodward
Abstract— Multiple-Input Multiple-Output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits. A particularly difficult part of these systems is the decoder, where the optimal maximum-likelihood (ML) solution is desirable, but cannot be directly implemented due to its exponential complexity. The paper presents the first published 8×8 MIMO detection engine with an integrated channel preprocessing unit, achieving near-ML BER results at 57.6Mbps, using QPSK in an extended HSDPA application. Other novelties include the high speed sorting mechanism and power saving features.
I. P ROBLEM BACKGROUND Multiple-Input Multiple-Output (MIMO) systems utilise spatial diversity between arrays of transmit and receive antennae to achieve high data rates. An existing MIMO device allows for data rates of 28.8Mbps [1] using a QPSK constellation in a 4 × 4 configuration. This paper addresses the need to achieve a higher data rate. There are two methods by which this can be done. One is to increase the constellation size [2], however [3] indicates that in a real world cellular system it would be preferable to first increase the antennae dimensionality. Both methods increase the size of the decoding problem by an exponential order. In particular, with n transmitters, each transmitting from a constellation of size 2q , the complexity of the problem becomes O (2qn ). The MIMO receiver in [1] has a search space size of 22×4 = 256 and is able to perform a brute force search, but doubling the number of antennae to 8 increases the search space to 65536, which is beyond currently feasible receiver designs. To overcome this, lattice decoding, especially the sphere search variant, is regarded as a very promising candidate for practical, high performance, near-optimal ML detection algorithms, and applications to MIMO have been studied in [4]. However, the algorithm and the associated preprocessing is still computationally intensive, and optimisations need to be found to further reduce its complexity. In [5], we proposed and analysed a simplified algorithm, similar to the “k-best” algorithm, with simulation results indicating that it greatly improved feasibility for VLSI implementation. Here, G. Knagge, B. Ninness, and S. Weller are with School of Electrical Engineering and Computer Science University of Newcastle, Callaghan NSW 2308, Australia
{gknagge,brett,steve}@ee.newcastle.edu.au M. Bickerstaff and G. Woodward are with Agere Systems, Lvl 3, 11-17 Khartoum Rd, North Ryde NSW 2113, Australia
{markb,
[email protected]}
we progress to a proof of concept device for an 8 × 8 MIMO application. II. A LGORITHM Consider a system model for a MIMO channel with t transmitters and r receivers: y = Hs + n.
(1)
Here, y is an r-vector with each element representing the received despread sample from one antenna, s is the t-vector of transmitted symbols, n is a length r noise vector, and H is an r × t matrix of channel coefficients between antennae. The MIMO detection problem is to solve (1) for s using ˜ the received symbol estimates y, and a channel estimate H, knowledge that the elements of s are from a finite set of constellation points. The maximum-likelihood (ML) detector [6] uses an exhaustive search to find ˜ 2, ˜ s = arg min ky − Hsk
(2)
s∈Λ
where Λ is the set of possible decisions over all users. This paper uses the lattice decoder approach of expressing (2) as ˜ s =
H ˜H ˜ H (s − ˆ s) . arg min (s − ˆ s) H
(3)
s∈Λ
Here, Λ is the lattice of possible decisions over all ˜ H denotes the conjugate transpose of H, ˜ and transmitters, H ˆ s indicates where the received signal vector, y, lies within the lattice of possible original transmissions. The ˆ s is the unconstrained ML estimate of s, given by a multiplication ˜ : by the pseudoinverse of H ˆ s =
˜ H y. ˜ −1 H ˜ H H) (H
(4)
A lattice decoder reduces the search space complexity via a Cholesky or QR decomposition, resulting in an upper ˜ H H, ˜ with the added triangular U such that UH U = H constraint that the diagonals of U are real and non-negative. The upper triangular nature of U allows the optimisation problem to be structured as a tree search, with each transmitter representing one level of the tree, and the branches representing a choice of one of the constellation points available for each transmitter. Each leaf then represents the entire collection of decisions, and has a cost that is the sum of the cost contributions associated with each of the branches taken to reach that leaf from the root of the tree. Fig. 1 presents an example for a t = 4 antennae problem, with binary decisions for each transmitter. The first decision is represented by level 1, which corresponds to the last row of U. Defining cost Ct+1 as 0, the cost for the node at level t + 1 − n of the tree is
C5 = 0
Level 0 Level 1
C4
Level 2
C3 C1
Level 3 Level 4
C2
Fig. 1. Example of cost allocations for tree search decisions. Note that “Level 0” does not actually exist in the search, since the first decision is represented by “Level 1”.
2 t X Cn = Cn+1 + unn (sn − sˆn ) + unj (sn − sˆn ) , (5) j=n+1
with the costs increasing monotonically as the tree is traversed. On each level of the tree all of the children of the current candidate nodes are evaluated, and the best k of these are kept as candidate nodes for the next iteration. When the leaf nodes are evaluated, the best k are selected and these can be used to generate soft information about the decision for each transmitter. In the proposed device, k = 16.
The numerical format used throughout the design is signmagnitude floating point. The main overhead cost, compared to a fixed point system, is the need to continually rescale values to a common exponent before any addition operation, and then scale the result so that the mantissa is at least 1 and less than 2. However, a restricted floating point system was found to produce better overall efficiency of hardware use with a smaller bit width. Furthermore, it offers better accuracy and numerical stability with smaller arithmetic units [7], while the sign-magnitude format aids floating point scaling and power saving optimisations. IV. P REPROCESSING The channel preprocessing functions of the algorithm involve finding the QR decomposition, and the pseudoinverse, of the channel matrix. This is a critical component that is omitted from many published 4 × 4 publications such as [8], and is even more challenging for an 8 × 8 system. Our proposed preprocessing engine is formed by the interaction of a number of smaller units, shown in Fig. 3, to perform the functions of matrix multiplication, QR decomposition, and search center calculation.
III. T OP L EVEL A RCHITECTURE Precomputation Unit
The target application is a High Speed Downlink Packet Access (HSDPA) scenario with 8 antennae using QPSK. With 15 orthogonal spreading codes in use, this gives a required data rate of 3.6 × 106 symbols per second, or 57.6Mbps. The chosen clock speed of 122.88MHz implies the need for three parallel processing engines, to achieve the average throughput of one symbol every 32 clock cycles. Additionally, to allow for fading channels, the channel may be refreshed as often as every 2048 chips, which requires the channel to be preprocessed. Since the preprocessing hardware is shared with the search center generator, this function needs to be performed as fast as possible. In this 0.13µm design, it is achieved within 3000 clock cycles. Channel Information (H,N) Preprocessor y
incoming samples buffer
U
Engine1 "U" Memory Engine2
search center Presearch calculator
Buffer
decision outputs
Engine3
Fig. 2. Top level architecture, showing three parallel search engines interfacing to preprocessor and output logic.
Fig. 2 shows an overview of the top level architecture chosen. Channel information is received by the preprocessing unit, where the channel pseudoinverse and decomposition is calculated in preparation for the decoding operations. During this process, incoming samples are held in a circular buffer and released once they are required. Once the preprocessor has finished, it is reused to perform the search center calculations. That vector is submitted to a presearch unit, with the results queued to the next available search engine in preparation for processing. Once processed, the results are reassembled into their original order, and output sequentially to an external interface.
Channel Matrix
x-0.5
Rotation Calculator
Storage
(4 real multipliers)
x-1 U
received samples
Complex Vector Multiplier Block S_hat
(8 complex multipliers)
Fig. 3.
Architecture of preprocessing unit for a 8x8 MIMO channel.
A. Vector-Matrix Multiplication The majority of operations involve multiplications between pairs of matrices, or between a vector and a matrix. These are achieved by a complex multiplier array, using floating point pipelined multipliers to achieve the majority of matrix-vector calculations. Power savings are realised by only activating the registers on various paths when the data is predicted to be valid. Additionally, paths containing zero values can be predicted by checking the most significant non-sign bit on the inputs. If zero, then the result of the multiplication can be predicted as zero and the multiplication is not necessary. B. QR Decomposition The standard QR decomposition is very complex due to its requirement for division and square root operations. This is addressed in [9], and extended by our work in [7]. The key concept is a “scaled and decoupled” QR decomposition that separates the numerators and denominators to avoid these difficult operations. For an m × n channel matrix, H, its QR decomposition is H = QR = ΦH K−1 P, − 21
− 12
(6)
where R = K P and QH = ΦH K . The resultant R is an m×n upper triangular matrix, Q is an m×m orthonormal
Algorithm IV.1 Scaled and Decoupled QR decomposition For i = 1 to min(n, m) do { For j = i+1 to n do { Part 1 - Calculate Givens Rotation Part 2 - Recalculate P(i, j + 1) to P(i, n) - Recalculate P(j, j + 1) to P(j, n) Part 3 - Recalculate Φ(i, 1) to Φ(i, n) - Recalculate Φ(j, 1) to Φ(j, n) } } In the following, our implementation of each of these parts is discussed. 1) Givens Rotation Calculation: The “rotation calculator”, shown in Fig. 4, generates a Givens matrix, G, which is an identity matrix apart from four entries, Gi,i , Gi,j , Gj,i and Gj,j . It also allows a new value of P(i, i) to be directly obtained. This part mainly consists of a series of multiplications by real numbers, and some addition and scaling operations. P(i,i)Real
P(i,i) * k(j) Cplx*real=Cplx 2 mults
P(j,i)Real
*
P(j,i)Cplx
C D
*
E F
*
Ki Kj
G H
Fig. 4.
rescale scale
I +
| P(i,i)|2 real2+real2=real 2 mults
Scale
* C(j) real*real=real C(j) (1 addition) k(j)
* k(j) real*real=real 1 mult
P(i,i)
Shift * real*real=real 1 mult
* C(i) real*real=real C(i) (1 addition) k(i)
k(i) * k(j) real*real=real 1 mult P(j,i) * k(i) cplx*real=cplx 2 mults
Fig. 5.
g_ij
g_jj
P(i,i)
P(j,i)
0
Flow of data through part 1 of the QR decomposition algorithm.
decomposed matrix, and only four real number multipliers are required. Cycle 1
Cycle 2
Cycle 3
P(i,i)|2
g_ii = P(i,i) * k(j)
X1 = |
g_ij = P(j,i) * k(i)
X2 = | P(j,i)|2
Cycle 4
X1 * k(j) W=+ X2 * k(i) P(i,i)= k(j)' = k(i) * k(j)
k(i)'= ZW = P(i,i)
Fig. 6. Timeline of calculations for part 1 of the QR decomposition algorithm.
2) Rotation of P: As seen in Fig. 7, part 2 is quite straightforward, requiring four complex multiplications and two additions per column, per iteration. With only four parallel complex multipliers, only one work unit is required for the calculation each column of P. g_ii P(i,l) X
g_ji P(i,l) X
+
Shift
P(i,l)
c_i
g_jj P(j,l) X
+
Shift
P(j,l)
c_j
g_iiReal
J K
rescale rescale
g_iiCplx
Fig. 7.
Architecture for recalculation of one column of P or Φ
g_ijReal
L
scale +
*
rescale
scale + +
* k(i) real*real=real 1 mult real + real =real
P(j,l) X +
A B
g_ji
P(j,i) * (-1)
| P(j,i)|2 real2+real2=real 2 mults
g_ij
P(i,i)Cplx
g_ii
Scale
matrix (QQH = I), and such a transformation exists for any matrix. The matrices P and Φ are dimensioned the same as R and Q respectively, and K is a real-valued n × m diagonal matrix. To obtain R and Q from these results, some square roots and divisions are necessary, but we will see that these are easily addressed. The architecture for calculating the QR decomposition breaks the algorithm into three distinct segments, as outlined in Alg. IV.1.
rescale
scale + rescale
M N
g_ijCplx
Rotation Calculator Unit for QR.
3) Rotation of Φ: On each loop of the decomposition, this part must multiply the existing Φ by the Givens matrix G that was obtained from Part 1. The architecture is almost identical to that of Part 3, except that m calculations are needed for each iteration of the decomposition. C. Search Center Calculation
The basic flow of data can be seen in Fig. 5, showing that there are several calculations that are dependent on each other, plus a few that are independent. These independent elements include the Givens rotation matrix, Gxx , and so these may be calculated first to allow parts 2 and 3 to proceed in parallel before this part has completed. The sign-magnitude floating point format can be very efficiently implemented, as the K and M outputs in Fig. 4 are known to be positive, and the amount of rescaling required is very limited. Using the work timeline provided by Fig. 6, only four work cycles will be needed, regardless of the size of the
While the channel decomposition only needs to be performed once per channel update, the unconstrained ML estimate, ˆ s, needs to be calculated for every search operation, as defined in (4). This is achieved by multiplying the incoming sample by the channel pseudoinverse, which may be expressed as : ˆ s = P−1 Φy, (7) where P−1 is calculated directly. While in principle an inverse is calculated, in practice only half of the effort is required because P is already in an upper triangular form. Direct inversions are often avoided due to concerns
result
newpointat
over numerical stability, however in [7] we demonstrated that it is no different to the commonly recommended backsubstitution method.
0.5
+
*0.5
pointat
0.5
(initial value)
*(-0.25)
x
(initial value)
*0.25
addy2
+
>0?
(initial value)
D. Scalar Reciprocal and Reciprocal Square Root While the scaled and decoupled method greatly reduces the number of square roots and divisions required, it does not completely eliminate them. In particular, to obtain R, the calculation is 1 R = K− 2 P. (8) The inversion and reciprocal square root operations are implemented by simple application of the bisection algorithm. The bisection algorithm assumes the known existence of a solution between two points, a and b. On each iteration, a midpoint c = a+b 2 is selected, and it is decided whether the solution is between a and c, or b and c, and either a or b is replaced with c as appropriate. For the case of finding the inverse of a scalar x, for any candidate point y this involves calculating :
ym
M U X
*2
0.5
ye
Fig. 9.
result
+ *0.5
(initial value)
addy
+1
Fig. 8.
0.5 (initial value)
ym *(-0.5)
*0.5 M U X
resultexp
*(-0.5)
Inverse Square Root Unit. Shaded boxes represent flip-flops.
E. Implementation A bit-accurate software model of the preprocessor reveals the effect of varying the manitissa bit size, and indicates (Fig. 10) that as little as 10 mantissa bits are necessary to obtain near-optimal performance. The final design implements a 12-bit version with 20000 standard cells and 9216 bits of memory. 8x8 channel, Full Search, Rayleigh fading Full Precision 12 bits 10 bits 8 bits 6 bits −1
BER
10
−2
10
−3
10
2
resultexp newpointat pointat
*0.25
+
(initial value)
0
Conveniently, the computational load is quite small when applied to the binary domain. For the reciprocal square root in a floating point system, the original value is xm 2xe , so the xe result will be of the form ym 2b 2 c . In a floating point system, it is known that xm is between 1.00 . . . 002 and 1.11 . . . 112 . Therefore, ym will be between 0.10 . . . 002 and 1.00 . . . 002 for both the inverse and inverse square root operations. The operation is executed by iterating once for each bit of the result. The test case C is the progressive result with a 1 added to the left as a new least significant bit. If the cost of C is positive, then the decision is kept, otherwise that bit is set to zero and the previous decision is kept. By examination of the operations involved, it can be seen that only a series of shifts and additions are required. This allows for the simple architectures shown in Fig. 8 and Fig. 9. *(-1)
*0.5
addy
10
For an appropriate a and b, costa would be positive and costb would be negative. The midpoint, costc , would replace a if it were positive, or replace b if it were negative. As the solution converges to the correct answer, both costs would converge to 0. Similarly, finding the inverse square root of x, for any candidate point y, involves calculating :
ye
adday
*(0.5)
ye(bit 0)
cost = 1 − xy
cost = 1 − xy
*(-0.5) (initial value)
+
>0?
x newx
Scalar Inverse Unit. Shaded boxes represent flip-flops.
−4
10
0
1
2
3
4
5 E /N [dB] b
6
7
8
9
10
0
Fig. 10. Performance of preprocessor under various bit widths for an 8x8 MIMO channel.
V. S EARCH E NGINES AND P RESEARCH The search engines are designed for expanding the 64 children of 16 candidate nodes and performing a sort, but the 16 candidates do not exist until after the second level of a quaternary tree. Hence, no sort is required and less calculations are required to fully expand the nodes that are present. To exploit this, a presearch unit is implemented and optimised to calculate the first two stages of the search in an efficient manner. This is done as fast as the search center estimates are made available, and so does not negatively impact on the performance. The search engines contain a three stage pipeline, which iterates to execute the final six levels of the parallel tree search. The content of these engines is illustrated in Fig. 11, and implements a series of simple node cost calculations in floating point format to evaluate (5) and expand each successive level of the tree. Once these are calculated, a sorter block is used to determine the best 16 of the 64 generated options.
Spherek common cost
u
cost searcher 1
|x|2
+
+
s cost searcher 2 precomputed costs and estimates
M U X
+
cost searcher n
2
+
|x|2
+
|x|
+
(pipeline stage 1)
Fig. 11.
Find best k
(pipeline stage 2)
(pipeline stage 3)
Architecture of a single search engine.
By including the presearch unit, two iterations are removed from the engines and this increases their throughput by 33%, reducing the total number of engines required. VI. S ORTING The most challenging aspect of the design is to build a sorter that selects the best 16 of the 64 evaluated nodes in one pipeline stage, containing 16 cycles at 122.88MHz. One of the key features exploited in our solution is that the outputs do not need to be fully sorted, as we only require the best 16 entries in any order. For this purpose, a Batcher sort [10], optimised for this application, was chosen. Fig. 12 illustrates how the sorting network is divided into stages, in which a subset of numbers is fully sorted. The first stage sorts pairs of inputs, the second stage sorts 22 inputs, the third sorts 23 , and so on. Within each stage, a series of pairwise comparisons are made to gradually reorder the elements in a set of substages. Stage 1.1 : T0 in0
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Fig. 12. 8 input sorting network configuration. The numbers indicate the matching inputs and outputs of connecting stages for clarity.
Fig. 12 also identifies the inputs by numbers, corresponding to an output of the previous substage. By tabulating these numbers, a series of patterns can be observed, providing a generalisation that allows a sorting system of any size to be designed : • For the first substage, on sorter element k and stage n, the two inputs are numbered k and 2n − k − 1. • For the second substage, the sorter elements are divided into two halves. For elements k = 0 to 2n−2 − 1, the inputs are numbered 2k and 2k + 2n−2 . For elements k = 2n−2 to 2n−1 − 1, the inputs are numbered 2n − 1 − 2k and 2n−1 − 1 − 2k. • Each substage thereafter divides the outputs into two halves, and then applies the second substage rule to each half When tabulated, it can be seen that certain patterns of connections repeat. In particular, for each stage K > 3, the first
three substages are unique and the remaining substages are the same as the corresponding final substages for the previous stage. To sort the 64 inputs, only 13 types of configurations are required to sort the numbers in 22 substages. To reduce the number of substages to 14, we first note that the final 3 substages are not needed because the set does not need to be fully sorted. The T3/T0 substages are recognised as a repeating combination and combined into one unit, and the first three substages are precomputed as the cost data is generated by the search engine. The resulting sorter architecture is an array of 16 of the 2-node sorter pairs shown in Fig. 13. output_a1 output_a2 output_an output_b1 output_b2 output_bn
M U X M U X
2node sorter in0
min
in1
max
to mux inputs
4node sorter in0
min
in1 nextmin output_c1 output_c2 output_cn output_d1 output_d2 output_dn
M U X M U X
to mux inputs
in2 nextmax in3
max
2node sorter in0
min
in1
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to mux inputs
Fig. 13. Optimised structure of the sorting elements. The 2-node elements implement the majority of the stages, using multiplexers to switch the inputs, and the 4-node unit implements the combined T3/T0 stage. The grey boxes represent registers separating the stages.
To reduce power, duplicate registers are placed on the outputs of the 2-node elements. If the next stage is a T3/T0 stage, then only the registers connecting to the 4-node element need to be clocked. This blocks logic transitions to the multiplexers and 2-node elements, which will not be used in the next stage. Otherwise, when the next stage is not the combined T3/T0 stage, power is saved by blocking logic transitions from entering the unused 4node element. VII. S CALABILITY The preprocessing architecture is easily scalable and is quite suitable for even larger matrices, but will require a longer execution time. Most of the additional effort occurs from the need to perform more iterations to complete the decomposition, with each iteration increasing only linearly in complexity. The remainder of the architecture is very modular, and so can be resized as required. If higher throughput is required, more engines may be added. If a higher constellation is required, additional search elements may be necessary, but the basic structure would remain unchanged. VIII. R ESULTS AND C OMPARISON A prototype device has been prepared and routed (Fig. 14) for a 0.13µm technology, with a core size of approximately 12mm2 . This establishes the feasibility of 8 × 8 MIMO detection, with a unique integrated preprocessing unit that is commonly omitted from simpler 4 × 4 designs. The algorithmic performance of our proposal, presented in [11], [5], indicates near-ML results.
Proposed 20K Gates 8×8 Yes QPSK > 57.6Mbps+ > 57.6Mbps+ 500K 122MHz
[8] No 4×4 No 16QAM 50Mbps < 50Mbps 117K 51MHz
[2] No 4×4 Yes 16QAM 106Mbps 106Mbps 97K 200MHz
[1] ML-APP 4×4 Yes QPSK 28Mbps 28Mbps 170K 122MHz
Preprocessor Mem 1
Preprocessor Mem 2
Reference Preprocessor Antennae List decoder Constellation Throughput, 1dB Throughput, 5dB Gates Clock Speed
TABLE I C OMPARISON OF MIMO IMPLEMENTATION PROPOSALS
Table I compares the proposed design with existing 4 × 4 MIMO implementations. However, it is difficult to achieve a fair comparison since the 8 × 8 system contains more levels in the tree, resulting in a more complex problem with more stages of decoding operation. The advantage is that, while a 4 × 4 may have identical search space and raw throughput as the proposed design, the choice of higher antennae dimensionality over higher constellation size is likely to provide better performance in practical applications [3]. Sphere based devices, such as [8], claim to have a lower cell area, but the throughput at low signal-to-noise ratios (SNRs) is significantly impaired and [8] does not provide soft decisions. Low SNRs are typical of realistic cellular channels, so the k-best style of algorithm has a clear advantage of having a constant throughput irrespective of SNR. Ref [4] estimates that the complexity increases at best in O(x3 ) with tree depth x, so if sphere decoder designs such as [8] were scaled to match the same complexity and throughput, the size would be more comparable. However, as illustrated in [5], the key advantage of this algorithm is the reduced number of calculations performed. The soft output decoder in [2] claims the capability of a very high throughput, but this is beyond the capabilities of the HSDPA standard targeted here. While their design is simplified through ordering based on SNR and channel information, this does not appear to scale well to 8 × 8 systems. Without this ordering, our design and [2] both require up to three times as many soft candidates, accounting for much of the difference in area. In [12] it is claimed that standard sphere detection provides similar bit error rate and throughput with a lower silicon area. However, it appears that this is referring to a 4 × 4 system and it is not clear what particular operating point is targeted. Our own experiments suggest that such claims are dependant on particular configurations and, when extended to an 8 × 8 system matching the performance of our proposed device, these claims would not hold. IX. C ONCLUSION This paper has presented a unique scalable device based on a k-best algorithm, establishing the feasibility of decoding data from an 8×8 MIMO system at 56Mbps for all SNRs. It includes the crucial channel preprocessing functionality, 16 candidates for soft output data, and addresses the high speed sorting challenge that is characteristic of this algorithm.
Engine Input Buffers
Data Input Buffer
Fig. 14. Plot of the final chip, indicating the relative sizes of memories and core logic.
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