Jul 15, 2011 ... Fullcustom Analog and Mixed Signal Circuit Design. ▫ Sensor circuits ... System
concept, ADC architecture, mismatch analysis,. Design ADC ... Slide 10. Design.
Implementation. P o w e r M a n a g e m e n. P o w e r M a n a g e.
Department of Electrical Engineering and Information Technology Endowed Chair for Parallel VLSI-Systems and Neural Circuits
Mixed Signal VLSI Design: Advanced Digital and Neuromorphic Circuits
Christian Mayr, 18.10.2010
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Chair Overview 1 professor 1 assistant professor 19 research associates (analog/mixed-signal/digital ASIC designers) 1 technician 5 student assistants acquired third party funds in 2009: 1,2M EUR
15.07.2011
Slide 2
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Competencies Fullcustom Analog and Mixed Signal Circuit Design Sensor circuits (photosensors) Data converters, signal conditioning Physical Implementation of Nanoscale VLSI Circuits MPSoC implementation Microchips in 40nm planned for 2011 Concepts and Methodologies for Low-Power Design Energy efficient solutions for baseband processing Neuromorphic Circuits Neural event communication and routing VLSI and Biology in the Loop 15.07.2011
Slide 3
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Project Overview ZMDI AG - TU Dresden R&D Cooperation Design and Optimization of Mixed-Signal-Circuits (AD-Converter, Signal conditioning)
BMBF-Project SyEnA: Synthesis driven design of analog circuits Infineon AG –TU Dresden R&D Cooperation Implementation of Multi Standard Baseband Processors (MuSIC2/3)
EU-FP7-financed neuromorphic projects: IP BrainScaleS, Marie Curie Network FACETS-ITN: Waferscale Neuromorphic Hardware STReP CORONET: Closed-Loop Interfaces VLSI - Biology
Cluster of Excellence CoolSilicon – CoolBaseStationICs Project Energy efficient Analog-/Mixed-Signal-Components and MPSoCs for baseband processing 15.07.2011
Slide 4
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
R&D Cooperation with ZMDI
Example: SAR-ADC Design 8x Input 14bit, 1M Sample/s 0.35µm XFAB System concept, ADC architecture, mismatch analysis, Design ADC core (Capacitance array, Trimming Methodic)
15.07.2011
Slide 5
10 Bit Delta-Sigma-Modulator (DSM) 2nd order in 65nm (03/2005, process not fully characterized) as test bed for analog circuit performance
Spannung (V)
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
2.5 2 1.5 1 0.5 0 -0.5 0
Φ1
Input signal
VCM Φ1
Φ2 Cadj
15.07.2011
CCII amplifier
1
Zeit (ms)
Instrumentation amplifier
1.5
2
2-1-1 Σ∆ modulator with preamplifier
VRef -
VRef+
MASH 2-1-1 DSM with integrated novel preamplifier for automotive applications, area advantage factor 4 compared to current literature
0.5
C0 ADJ
&
Φ2
CI
Φ1 VCM
FB
Φ2
+ OPV - +
Buffer with adapt. biasing
Test crossbar
Decimation and digital control Slide 6
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Technology Independent Design of Analog Integrated Circuits Goal: Reduction of porting and optimization effort Methodologies for automation of analog design technology migration Lookup table methods for transistor characterization Rule-based operating point porting strategies Automated feasibility analysis of design portability
15.07.2011
Slide 7
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Fullcustom Analog and Mixed Signal Circuit Design Photosensor arrays in 90/65nm CMOS technology Design and evaluation of analog circuits in leading edge digital technologies
15.07.2011
Slide 8
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
MPSoC Projects 130 nm
90 nm
Tomahawk Vendor Die area Tape-out Project Partner Flow
: UMC : 100 mm² : 05/2007 : WIGWAM (BMBF) : Vodafone Chair : ICPRO
MuSIC Vendor Die area Tape-out Project Partner Flow
Vendor Die area Tape-out Project Partner Flow
: Infineon/TSMC : 100 mm² : 2009 : Infineon : Infineon/FhG : Inway
MuSIC3
ATLAS
15.07.2011
MuSIC2 : Infineon : 64 mm² : 07/2006 : MxMobile (BMBF) : Infineon/FhG : Inway
40 nm
65 nm Vendor Die area Tape-out Project Partner Flow
65 nm
: TSMC : 16 mm² : 2010 : CoolBasestations (BMBF) : Vodafone Chair : ICPRO
Vendor Die area Tape-out Project Partner Flow
: Infineon/TSMC :? : 2011 : Infineon : Infineon : Inway
Slide 9
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
15.07.2011
MPSoC Architecture & Programming Model
Design
Implementation
• Power Management
Power Management
Low Power Design – Power Aware Design Flow
•
Power management features defined at architectural level have strong impact on hardware implementation Characteristics of implemented power management hardware determine efficiency of power management
Slide 10
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Physical Implementation of Nanoscale VLSI Circuits MuSIC2 – SIMD-Cluster 4 SIMD-Cores 4 Processing elements, 1 general purpose (GP) core each 2 GP cores 4MBit Memory 800k standard cells 65nm CMOS Partial power shut-off 1.0V supply voltage
15.07.2011
Slide 11
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
CoolBaseStationICs Goal: Power-reduction of MPSoCs for baseband processing System- und circuit concepts for power efficient NoC (Network on Chip) architectures and on-chipcommunication Investigations of concepts for adaptive power regulation (frequency and/or voltage scaling, power shut-off) Cell-based design of full-custom macros (Register Files, FIFOs, datapath elements) Analog, mixed-signal components (NoC-transceivers, voltage regulators) MPSoC demonstrator implementation (65nm CMOS)
15.07.2011
Slide 12
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
ATLAS Testchip
15.07.2011
•
GALS system based on ADPLLs
•
Implementation of Power Shut Off (PSO) and Dynamic Voltage & Frequency Scaling
•
Fast VDD switching by on chip hardware
•
Configurable low level power management CTRL
•
NoC links for distances of several mm
•
Maximum link bandwidth 72 GBit (bidirectional) Slide 13
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
EU-Project FACETS, BrainScaleS, FACETS-ITN Fast analog Computing with Emergent Transient States
15.07.2011
Slide 14
FACETS: Novel Computational Paradigms Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
The FACETS waferscale system: Neuromorphic circuits in a largescale adaptive pulse-processing application
15.07.2011
Slide 15
FACETS: Novel Computational Paradigms Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Cutout of the FACETS waferscale system focused on the digital network
15.07.2011
Slide 16
FACETS: Novel Computational Paradigms Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
Host control
power supply board with current measurement capabilities
sense cable
differential probe
Gigabit Ethernet cable
10 Gbit/s link cable
reference clock
power cable
10V – 14V power input
LVDS transmission
Digital Network ASIC (DNC)
FPGA AER board
►Setup for Layer 2 and host communication for 4 DNCs(=32 HICANNs) ►Highly Integrated 14 Layer PCB with , ready for integration Waferscale System 15.07.2011
Slide 17
CORONET: Influencing Behaviour in Animals Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
B
MicroElectrode Array (MEA)
Network States
System PCB
FPGA
Biomimetic Network (including Support System) 15.07.2011
Short Term Plasticity
Multi-Output DAC, Multiple Current Bias
High-Density Synapse Matrix with Long Term Plasticity
Short Term Plasticity AER Decoder
AER Decoder
Coupling Dynamics
AER Decoder
AER Neurons
Config
Arbiter
Biomimetic Network
Bidirectional AER Interface
Gentle Steering
Routing, Topology Configuration, Delays
Small Config.&Test Interface
Cell Culture
NeuroSoC
Configurable Poisson Generators
A
Network Stimulation and Biasing (Peripheral Components) Pulse Communication and Routing on Chip and off Chip Neuromorphic Components
NeuroSoC in CMOS VLSI
Slide 18
Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems
ASIC Design Lab • •
•
•
Common platform for chip design activities of chairs of Prof. Ellinger, Prof. Schüffny and Prof. Fettweis Available technologies nodes: - Austria-Microsystems (AMS) 0.35µm - XFAB 0.35µm, 0.18µm - UMC 0.18µm, 0.13µm, 90nm - STM 65nm, 45nm - IBM (Mosis) - IHP (GaAs, by Prof. Ellinger, CCN) - TSMC 65 nm Reusable design flow (ICPRO) – Project and Design Flow Management System for Design and Verfication of Integrated Circuits – used for all chip design project (analog, mixed-signal and digital) – EDA tools of main vendors (Cadence, Synopsys, Mentor) are integrated High-capacity Compute Hardware – Linux Compute Cluster (total 28 (2x)cores, 400GB Mem, 8TB storage)
15.07.2011
Slide 19
