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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 3, MARCH 2007

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Guest Editorial

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HE IEEE/ACM Design, Automation and Test in Europe (DATE) Conference is the main European event that addresses all topics of research on design technology for electronic and embedded systems engineering. This covers design (hardware and embedded software), verification and test, algorithms, and tools for design automation of electronic circuits and systems for applications such as wireless communications, multimedia, and automotive systems. The event provides a discussion forum on research trends at different levels, from electrical, architectural, and embedded software to design automation and test challenges of circuits and systems. DATE takes pride in the quality of its program resulting from a thorough review process. Submissions are coming from all over the world, and paper selection is highly competitive with 388 worldwide experts in the technical program committee providing peer reviews (on average 4.6 reviews per paper in 2006) based mainly on quality, novelty, and potential impact. For DATE 2006, 834 submissions were received, from which finally 233 papers (including Designer’s Forum) were selected for presentation at the conference. This special issue of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS presents extended versions of selected papers from among the top papers presented at the 9th DATE Conference, which was held on March 6–10, 2006, in Munich, Germany. Upon invitation, several authors submitted an extended paper, from which—after the standard TCAD peer-review process—eight papers were finally accepted for inclusion in this special issue. These papers provide a good cross section of topics covered at DATE 2006. The first two papers address multiprocessor systems-on-chip (MPSoC) architectural and methodological issues, and the third paper deals with the problem of accelerating embedded processor execution through instruction set extensions. The next paper focuses on techniques for optimal bit width allocation in the conversion from floating point to fixed point in arithmetic circuits for low power, while the following one proposes an algorithm to optimize circuits with tight sequential cycles. Then, a paper describing efficient methods to solve more general quantified Boolean formulas (QBFs) is proposed. The last two papers focus on soft error rate (SER) analysis for combinational circuits and the design of reconfigurable continuous-time ∆Σ modulator topologies, respectively. The eight papers are summarized in greater detail below. The first paper, “A Framework for Co-synthesis of Memory and Communication Architectures for MPSoC,” by Pasricha and Dutt, proposes an automated application-specific cosynthesis framework for memory and communication architectures in MPSoC designs, considering the memory and communication

Digital Object Identifier 10.1109/TCAD.2006.890147

architectures together in order to obtain an optimal solution for both. The primary objective is to design a communication architecture having the least number of busses, which satisfies performance and memory area constraints, while the secondary objective is to reduce the memory area cost. Experiments have been performed on different industrial designs from the networking application domain to prove the effectiveness of the proposed solution. The second paper, “A Layout-Aware Analysis of Networkson-Chip and Traditional Interconnects for MPSoCs,” by Angiolini, Meloni, Carta, Raffo, and Benini, aims at analyzing the strengths and weaknesses of different interconnection solutions for MPSoC platforms by performing a thorough analysis based upon actual chip floorplans after the interconnection place and route stages and after a clock tree has been distributed across the layout. Innovative packet-switching networkson-chip (NoCs), a more conservative approach, interleaves bandwidth-rich components (e.g., crossbars) within preexisting fabrics, and traditional bus solutions have been thoroughly compared by analyzing performance, area, and power results while keeping an eye on the scalability prospects in future technology nodes. The third paper, “Introduction of Architecturally Visible Storage in Instruction Set Extensions,” by Biswas, Dutt, Pozzi, and Ienne, deals with the problem of selecting the best instruction set extension for embedded processors to accelerate their performance. The paper presents an instruction set extension identification technique that can automatically identify stateholding application-specific functional units comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. This solution, requiring a limited hardware overhead, is shown to provide a 2.8× speedup over software solutions. The fourth paper, “Low Power Optimization by Smart Bit-Width Allocation in a SystemC Based ASIC Design Environment,” by Mallik, Sinha, Zhou, and Banerjee, focuses on methods for power consumption reduction through optimization of bit widths of fixed-point variables in a SystemCbased ASIC design environment. The algorithms defined are used in the conversion of floating-point SystemC programs into synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite-precision conversions. Experimental results show the possibility of reducing power consumption by an average of 50% by allowing roundoff errors to increase from 0.5% to 1%. The fifth paper, “Optimizing Sequential Cycles through Shannon Decomposition and Retiming,” by Soviani, Tardieu, and Edwards, deals with the optimization of sequential cycles in logic circuits and, in particular, proposes an efficient algorithm that simultaneously applies Shannon decomposition and retiming to optimize circuits with tight sequential cycles, which can be easily added to a logic synthesis flow.

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 3, MARCH 2007

The sixth paper, “Computing the Soft Error Rate of a Combinational Logic Circuit using Parameterized Descriptors,” by Rao, Chopra, Blaauw, and Sylvester, presents a fast and efficient SER analysis methodology for combinational circuits. Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs. After presenting a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit, the construction of the descriptor object is described to efficiently capture the correlation between transient waveforms and their associated rate distribution functions. The algorithm consists of operations to inject, propagate, and merge these descriptors while traversing forward along the gates in a circuit. The parameterized waveforms enable an efficient static approach to calculate the SER of a circuit. The approach is exercised on a wide variety of combinational circuits, which indicates a linear runtime of the algorithm with the size of the circuit. The runtimes for soft error estimation were observed to be in the order of about 1 s compared with several minutes or even hours for previously proposed methods. The seventh paper, “Systematic Methodology for Designing Reconfigurable ∆Σ Modulator Topologies for Multimode Communication Systems,” by Wei, Doboli, and Tang, proposes a systematic methodology for designing reconfigurable continuous-time ∆Σ modulator topologies. Topologies are optimized by minimizing the complexity of the topologies, maximizing the sharing of circuits between different modes, maximizing the topology robustness with respect to circuit nonidealities, and minimizing the total power consumption. The paper presents a case study for designing topologies for a threemode reconfigurable ∆Σ modulator and compares the obtained topologies with a state-of-the-art design and the topologies obtained using a ∆Σ toolbox.

The last paper, “Quantifier structure in search based procedures for QBFs,” by Giunchiglia, Narizzano, and Tacchella, describes a more efficient way for solving more general QBFs. The best currently available solvers for QBFs process their input in prenex form, i.e., all the quantifiers have to appear in the prefix of the formula separated from the purely propositional part representing the matrix. However, in many QBFs deriving from applications, the propositional part is intertwined with the quantifier structure. Rather than converting such QBFs in prenex form, the paper shows that current search-based solvers can be naturally extended to handle non-prenex QBFs and to exploit the original quantifier structure. To validate the claims, the ideas are implemented in the state-of-the-art searchbased solver QuBE, and an extensive experimental analysis is conducted, which shows very substantial speedups. The Guest Editors would like to thank the DATE Executive Committee and Technical Program Committee for their contributions to make DATE 2006 a truly successful conference. We also sincerely want to thank all reviewers who have kept up with the very tight schedule to complete this special section. We hope that you enjoy this selection of some of the best papers from DATE 2006. GEORGES G. E. GIELEN, Guest Editor General Chair Department of Electrical Engineering–ESAT Katholieke Universiteit Leuven 3001 Leuven, Belgium DONATELLA SCIUTO, Guest Editor Program Chair Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milan, Italy

Georges G. E. Gielen (S’86–M’91–SM’99–F’02) received the M.Sc. and Ph.D. degrees from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1986 and 1990, respectively, both in electrical engineering. In 1990, he was a Postdoctoral Research Assistant and a Visiting Lecturer with the Department of Electrical Engineering and Computer Science, University of California, Berkeley. From 1991 to 1993, he was a Postdoctoral Research Assistant with the Belgian National Fund of Scientific Research, ESAT Laboratory, Katholieke Universiteit Leuven. He was appointed as Assistant Professor with the Katholieke Universiteit Leuven in 1993, and he was promoted to full Professor in 2000. He has authored or coauthored two books and more than 300 papers in books, international journals, and conference proceedings. His research interests are in the design of analog and mixed-signal integrated circuits, especially in analog and mixed-signal CAD tools and design automation (modeling, simulation, and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is a coordinator or partner of several industrial research projects in this area. Dr. Gielen served as an elected member of the Board of Governors of the IEEE Circuits And Systems (CAS) Society and as Chairman of the IEEE Benelux CAS chapter. He served as the President of the IEEE CAS Society in 2005. He is a regular member of the Program Committees of international conferences (DAC, ICCAD, ISCAS, DATE, CICC, etc.) and served as General Chair of the DATE Conference in 2006. He regularly serves as a member of the Editorial Boards of international journals (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, International Journal on Analog Integrated Circuits, and Signal Processing). He received the 1995 Best Paper Award in the John Wiley International Journal on Circuit Theory and Applications and was the 1997 Laureate of the Belgian Royal Academy on Sciences, Literature and Arts in the discipline of engineering. He received the 2000 Alcatel Award from the Belgian National Fund of Scientific Research for his innovative research in telecommunications and won the DATE 2004 Best Paper Award.

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Donatella Sciuto (S’84–M’87) received the Laurea degree in electronic engineering from the Politecnico di Milano, Milan, Italy, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. She is currently a Full Professor with the Dipartimento di Elettronica e Informazione, Politecnico di Milano. Her main research interests cover methodologies for hardware/software codesign of embedded systems, from the specification level down to the implementation of both hardware and software components. Dr. Sciuto is a member of IFIP 10.5, SIG-HDL, and EDAA. She is or has been a member of different program committees of EDA conferences (DAC, ICCAD, DATE, ISSS/CODES, DFT, FDL) and an Associate Editor of the IEEE TRANSACTIONS ON COMPUTERS, and the Journal of Design Automation of Embedded Systems. She is on the Executive Committee of the IEEE/ACM Design, Automation and Test in Europe Conference, for which she has been Program Chair in 2006 and is Vice General Chair for 2007.