is prohibited without the prior written consent of CEA. Advanced NVM. Devices
using. Multi-Gate and 3D structures. Luca Perniola
2007
Advanced NVM Devices using Multi-Gate and 3D structures Luca Perniola
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SINANO-NANOSIL Workshop
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1
L. Perniola
September, 18th
Outline Economic market, NAND Flash issues & ITRS predictions Multigate memories 2007
Body-tied nitride finfet SOI nitride finfet
3D integration paths Conclusion
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L. Perniola
September, 18th
Memory market nowadays & trends
2007
Yole developpment April 2009
NAND is the fastest growing memory segment
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Limits of current NAND technology
S.J. Baik et al. 2007
Main issues: Device electrostatic integrity poor coupling factor (poor W/E), low Ion (enhanced access time), high Ioff (shrinked operating window), electron number fluctuation (increased dispersion) Enhanced interference between nearby cells read fail, program disturbance Process complexity strong investments to assure sufficient fault tolerance
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NAND Flash (ITRS 2008) 2008
2009
2010
2011
2012
2013
2014
2015
NAND Flash Technology [nm]
45
40
36
32
28
25
22
20
Cell type
FG
FG
FG/CT
CT
CT
CT-3D
CT-3D
CT-3D
Floating gate NAND Interpoly
ONO
ONO
ONO ONO
High-k
High-k
High-k
High-k
Interpoly thickness [nm]
10-13
10-13
10-13
9-10
9-10
9-10
9-10
Year of production
10-13
ITRS 2008 envisages High-k interpoly combined with charge trapping (CT) layers for sub-30nm nodes, then 3D + CT… 2007 Samsung TANOS (TaN / Al2O3 / Si3N4 / SiO2 / Si)
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Y. Kow, Hynix SINANO-NANOSIL Workshop
TANOS 40nm SAMSUNG VLSI’06 Confidential L. PerniolaIEDM’06, September, 18th
5
Why 3D ? Density & cost motivation
2007
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L. Perniola
September, 18th
Outline Economic market, NAND Flash issues & ITRS predictions Multigate memories 2007
Body-tied nitride finfet SOI nitride finfet
3D integration paths Conclusion
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September, 18th
Bulk or SOI Nitride Finfet devices Finfet advantages:
Increased Drive Current reduced access time Reduced Short Channel effects lower Ioff, compact device layout Increased active area better retention Compatibility with multigate SOC Control Gate
Nitride
Nitride-trapping advantages: 2007
No inter-FG interference Lower operating voltages Strong immunity to oxide defects Improved scalability
Source
Improved electrical characteristics
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September, 18th
Body-tied finfet (1/2) S.H. Lee, SAMSUNG, IEDM 2006
LG = 63 nm 32 bit string
2007
BT Finfet
&
Body-erase Better heat dissipation SINANO-NANOSIL Workshop
Confidential
TANOS enhanced write/erase reduced electron back tunneling during erase
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September, 18th
S.H. Lee, SAMSUNG, IEDM 2006
Body-tied finfet (2/2)
2007
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September, 18th
Body-tied Hemi-Cylindrical (HC) FET
D.Kwak, SAMSUNG, VLSI 2007
LG = 38 nm for 64 Gbit 32 bit string
2007
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September, 18th
J.-M. Koo, SAMSUNG, VLSI 2008
Body-tied paired finfet
2007
LG = 63 nm Sub-10 nm fin width © CEA 2009. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
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L. Perniola
September, 18th
Outline Economic market, NAND Flash issues & ITRS predictions Multigate memories 2007
Body-tied nitride finfet SOI nitride finfet
3D integration paths Conclusion
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September, 18th
LETI device fabrication (1/3) • SOI wafers, Tsi=30 nm
Si Buried oxide
• Fins patterning with Ebeam lithography and resist trimming
2007
• Sidewall oxidation to round the corners and obtain smaller fins • Boron implantation for VTH adjustment • Gate stack deposition process:
fin Buried oxide Poly-Si N+ HTO
3 nm SiO2+ 5nm Si3N4 (LPCVD) + 8 nm HTO + 100 nm Poly-Si N+ Buried oxide
+ oxide hard mask
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September, 18th
LETI device fabrication (2/3) • Gate patterning: Ebeam lithography, resist trimming and combined dry and wet etching
Gate Si fin
• Extension implants + 950°C RTA anneal • 50 nm nitride spacer + 20 nm S/D Si selective epitaxial growth Poly 2007
• S/D implants + 1050°C Spike anneal
Si
• Ni Silicidation + classical Back-end process © CEA 2009. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
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September, 18th
LETI device fabrication (3/3) SOI nitride finfet
E. Nowak et al., IEDM 2008
SONOS
WFIN down to 15 nm HFIN ~ 20 nm
SONOS / THiONOS stack
Poly N+ SiO2 Si3N4 SiO2
THiONOS
2007
Poly N+ TiN HfO2 SiO2 Si3N4 SiO2 SINANO-NANOSIL Workshop
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September, 18th
1D Model 1D potential & capacitance calculation for planar and corner regions Total programming window is weighted sum of each regions
cylindrical geometry planar geometry
RC
VG
2007
VTplan
VD VT =
VTcylin plan
plan
VS
+
cylin
plan T
V
+
cylin plan
+
cylin
VTcylin
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E. Nowak et al., NVSMW 2008 SINANO-NANOSIL Workshop
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September, 18th
Programming window: planar vs. corner regions 4
4.0
2 Si-fin 0
JJ11
planar regions corners
3.0
FG
-2
J2
-4
2.5
Control Gate
-6
2.0
J2
-8
1.5 1.0
-10 2007
-12
0.5
planar regions corners
-14 -5
3.5
0
5
10
0.0
15
20
Radial Distance [nm]
25
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
Threshold Voltage Shift ∆VTH [V]
Energy Band Diagram [eV]
L. Perniola et al., IEDM 2007
Stress Time t [s]
Finfet corners enhance the coupling between control gate and trapping medium localised stronger injection Confidential SINANO-NANOSIL Workshop L. Perniola September, 18th © CEA 2009. All rights reserved
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18
2007
5
Data Model VG=8V VG=10V VG=12V
4 3
SONOS
2 1 0 -7
10
-6
-5
-4
-3
-2
10 10 10 10 10 Stress Time t [s]
-1
10
Programming Windows ∆VT [V]
Programming Windows ∆VT [V]
Experimental Results 5 4 3
Data Model VG=8V VG=10V VG=12V
THiONOS
2 1 0 10
-7
10
-6
-5
-4
-3
10 10 10 10 Stress Time t [s]
-2
-1
10
Better programming performances for THiONOS E. Nowak et al., IEDM 2008 SINANO-NANOSIL Workshop
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Confidential
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September, 18th
WFIN 2007
Programming Windows ∆VT [V]
Fin Width dependence 4 3
Data Model WFIN=15nm WFIN=35nm
SONOS VG=12V
2
VG=10V
1
VG=8V
0 -7
10
-6
-5
-4
-3
10 10 10 10 10 Stress Time t [s]
-2
-1
10
VT increases when reducing fin width Model predicts an higher impact of trapped charges at corners for smaller devices
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September, 18th
Programming Windows VT [V]
Scaling perspectives: HC-FET TANOS 22
32
45
Memory Generation [nm]
100 ms //
6
1 ms
4
10 us
2
100ns
2007
0
10
20
30
1ns 40 50
Rc
// D. Kwak et al, VLSI 07
//
// //Plane 60
Curvature Radius Rc [nm]
Reducing cell size smaller VT at saturation faster dynamics
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E. Nowak et al., IEDM 2008 SINANO-NANOSIL Workshop
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September, 18th
Scaling limits of nitride finfet devices Y pitch not a concern: LG=30 nm functional devices X pitch is a concern: Enough space to accommodate fin/gate stack/control gate X pitch 2007
x = fin + 2d + m = 10nm + 30nm + 5nm = 45 nm F = x/2 = 20-22 nm (2014 from ITRS 2008) Thanks to C. Gerardi – STMicroelectronics
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September, 18th
Conclusion on nitride finfet devices Enhanced electrostatic integrity (Ion/Ioff, retention) & no inter-FG interference Possible multi-bit approach (paired finfet) Scaling down HC-TANOS: 2007
Lower VT at saturation Strongly enhanced write dynamics
Scaling possibilities: WL-pitch is a concern. © CEA 2009. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
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L. Perniola
September, 18th
Outline Economic market, NAND Flash issues & ITRS predictions Multigate memories 2007
Body-tied nitride finfet SOI nitride finfet
3D integration paths Conclusion
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S. –M. Jung, SAMSUNG, IEDM 2006
3D « wafer stacking »
2007
Equal electrical characteristics of both layers Wafer bonding technology (not cost effective)
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3D « Pipe-shaped Bit Cost Scalable (P-BiCS) »
2007
R. Katsumata, Toshiba, VLSI 2009
Bit cost scalable solution Polyxls channels No metal gate (gate first approach) © CEA 2009. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
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3D « Terabit Cell Array Tr (TCAT) »
2007
Bit cost scalable solution Metal gate (gate last) Polyxls channels SINANO-NANOSIL Workshop
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J. Jang, SAMSUNG, VLSI 2009
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W. Kim, SAMSUNG, VLSI 2009
3D « Vertical Gate NAND (VG-NAND) »
2007
WL connections easier than BiCS & TCAT Polyxls channel Doping requirement for enhancement mode tr
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3D Monolithic stacked SONOS
Monoxls channels Research level LETI patent
2007
T. Ernst et al., CEA-LETI, MINATEC, IEDM 2008 A. Hubert et al., IEDM 2009 SINANO-NANOSIL Workshop
Confidential
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Conclusion & forecast Nitride Finfet:
Improved electrical characteristics (Ion/Ioff & retention, program/erase dynamic enhancement thanks to corner effect) Compact layout & larger active aerea WL-pitch scaling concern
3D concept advantage:
2007
In future will be cost effective solution Further increase the density
3D CT-NVM when?
3D CT-NVM when cost-parity or performance/reliability will be achieved wrt wire-bonding technology HC-TANOS stand-alone for 2x NAND nodes, after… 3D © CEA 2009. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
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Acknowledgement
2007
E. Nowak, A. Hubert, G. Molas, T. Ernst, J. P. Colonna, C. Jahan, M. Gély, V. Vidal, A. Toffoli, R. Kies, G. Reimbold, F. Boulanger, B. De Salvo R. Clerc, G. Ghibaudo, G. Pananakakis from IMEP-LAHC, MINATEC, Grenoble, France. LETI cleanroom facilities IU.NET, Univ of Pisa, CNR-IMM Catania, Italy European commission for FINFLASH project LETI industrial partners © CEA 2009. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
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Innovation for industry 2007
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Join us for the
11th Leti Annual Review 2007
June 22-23, 2009 at Minatec For more information : www.leti.fr
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