ADVANCED PROGRAM 2009 IEEE BIPOLAR / BiCMOS CIRCUITS ...

23rd Year

1986-2009

ADVANCED PROGRAM 2009 IEEE BIPOLAR / BiCMOS CIRCUITS AND TECHNOLOGY MEETING www.ieee-bctm.org Capri Palace Hotel Capri, Italy OCTOBER 13 – 14, 2009 SHORT COURSE — OCTOBER 12, 2009

SPONSORED BY THE ELECTRON DEVICES SOCIETY OF THE INSTITUTE OF ELECTRICAL AND ELECTRONIC ENGINEERS IN COOPERATION WITH THE IEEE SOLID-STATE CIRCUITS SOCIETY

23rd Year

1986-2009

2009 BCTM SCHEDULE AT A GLANCE Monday — October 12 Registration open from 7:30 AM-8:30 AM, 3:00 PM– 8:00 PM PRIVÉE ROOM 8:30 AM — 5:45 PM

SHORT COURSE MEDITERRANEA ROOM

Tuesday — October 13 Registration open from 8:00 AM – 5:00 PM PRIVÉE ROOM 9:30 AM Opening Remarks and Announcements 9:45 AM Keynote Speaker – Dr. Thomas Skotnicki — “Does the Future of Si Reside in Other Materials” 10:30 AM MEDITERRANEA ROOM 10:30 AM Break – OLIVIO TERRACE 10:50 AM — 12:30 PM

12:30 PM — 1:55 PM 2:00 PM — 4:05 PM

4:05 PM 4:25 PM — 6:05 PM

8:00 PM — 11:30 PM 8:30 AM — 11:10 AM 11:10 AM 11:30 AM — 12:45 PM 12:45 PM — 2:20 PM 2:20 PM — 4:25 PM

1. Limits of SiGe HBTs Mediterranea Room

2. Perf. and Operating Constraints of SiGe HBTs Cavalli Room

3. Software Defined Radio Monte Solaro Room

Luncheon OLIVIO TERRACE 6. Meas. and 4. RF Building 5. Device Parameter Blocks Physics Extraction Simulations Mediterranea and Structures Monte Solaro Room Cavalli Room Room Break – OLIVIO TERRACE 7. Advanced 8. Signal Modeling and Processing Char. Mediterranea Cavalli Room Room Dinner Banquet Capri Palace Hotel Wednesday — October 14 9. Emerging Technologies Session MEDITERRANEA ROOM Break – OLIVIO TERRACE 10. High11. SiGe Speed Digital BiCMOS Platforms Mediterranea Cavalli Room Room Luncheon and Luncheon Talk: “Pompei Excavations” Dr. Claudia Palazzolo Olivares OLIVIO TERRACE – CAVALLI ROOM 12. mmW 13. Trends in BiCMOS Si and SiC Circuits Power Devices Mediterranea Cavalli Room Room END OF CONFERENCE

23rd Year

1986-2009

Welcome from the BCTM 09 Chairmen Welcome to the 2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting! The conference will be held at the Capri Palace Hotel & Spa, on the beautiful and picturesque island of Capri, Italy. This year marks the return of BCTM to Europe as part of our regular conference rotation of two years in the USA followed by one year in Europe. We are very pleased and excited to have Dr. Thomas Skotnicki as this year's keynote speaker. Dr. Skotnicki is the STMicroelectronics Fellow and Director of the Advanced Devices Program at STMicroelectronics in Crolles, France. His talk is entitled “Does the Future of Silicon Reside in Other Materials?” and promises to offer great insight into the future of semiconductors by drawing on Dr. Skotnicki’s impressive experience in inventing semiconductor methods such as the Voltage Doping Transformation (VDT), Silicon on Nothing (SON) Technology (awarded Rappaport Award for the best IEEE EDS publication in the year 2000), and much more. You should attend BCTM 2009 if you’re interested in leading edge processes, devices, and circuits used in state-of-the-art communications and power control systems. The conference starts with a one-day short course followed by two full days of contributed and invited papers, including a special session on Emerging Technologies. On Tuesday evening, there will be a four course Gala dinner held at the Capri Palace. A luncheon talk will be given on the topic of the excavation of Pompeii. Following the catastrophic eruption of Mount Vesuvius in CE 79, Pompeii was destroyed and completely buried. The nature of the volcanic ash that covered the city left it well-preserved and the ancient city is now the subject of both archeological excavation and conservation as the site becomes exposed to both nature and man. The short course features three experts discussing "RF and mmwave applications." The invited talks include: “Electronic Beam Forming/Phased Array” by Prof. Hashemi of the University of Southern California, “From mm-wave Measurement to Design: Measurement, de-embedding and design” by Marcel Tutt of Freescale Semiconductor, and “RF MEMs: Technology, Modeling, and Reliability” by Dave Howard of Jazz Semiconductor. The technical program consists of 13 sessions with 47 contributed papers, including six double-length invited papers. There are four invited papers on Emerging Technologies: “Ultra-Thin Chip Technology for Next-Generation Silicon Applications” presented by Prof. Joachim Burghartz, IMS Chips/Stuttgart; “3D Integration Technologies for MEMS/IC Systems” by Dr. Peter Ramm, Fraunhofer IZM; “Nanotera.ch: Nano-Technologies for Tera-Scale Problems” by Dr. Giovanni De Micheli, Integrated Systems Centre, EPFL, Lausanne, Switzerland; and “Gallium Nitride (GaN) High Power Devices for Advanced Commercial and Military Applications” presented by Dr. Jeff Shealy of RFMD. We thank the BCTM committee for assembling the 2009 program and especially Niccolò Rinaldi and Jan Jopke for organizing and arranging the local events. See you in Capri!

Frank Thiel

David Ngo

Conference General Chair

Technical Program Chair

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Capri Palace Hotel Layout - Ground Floor -

Privée Room Terrace Olivo

Cavalli Room

Mediterranea Room

____________________________________ - A Floor –

Monte Solaro B Room

Monte Solaro A Room

4

23rd Year

1986-2009 GENERAL INFORMATION

ADMISSION All interested persons are welcome to register and attend the BCTM; you do not have to be an IEEE member. Admission to sessions requires a BCTM badge. Please wear your badge at all times. REGISTRATION Complete registration information is contained in the centerfold of this booklet as well as on the conference’s web page (www.ieee-bctm.org). Please use the website to register. The advance registration deadline is September 18, 2009. All conference activities are included in the registration fees (technical sessions, luncheon, and banquet) as well as a CDROM and printed copy of BCTM 2009 Proceedings. Additional copies of BCTM 2009 Proceedings can be obtained at prices shown in the registration centerfold of this booklet. DINNER BANQUET The dinner banquet takes place on October 13, 2009, Tuesday evening, at Capri Palace Hotel. The Capri Palace Hotel restaurant, the only restaurant on Capri which boasts a Michelin star, serves Mediterranean cuisine interpreted with great originality. OTHER CONFERENCE SOCIAL EVENTS Several events have been arranged to promote informal social interactions between conference participants. Following the Keynote talk and Emerging Technologies sessions, coffee and cookies are available. The Monday evening reception also provides another opportunity to network with fellow conference attendees. LOCATION Located in Anacapri, a beautiful and tranquil town of the island of Capri, the Capri Palace Hotel stands 300 meters above sea level, overlooking the open Mediterranean Sea and the Gulf of Naples. SURROUNDING AREA Visited over the centuries by intellectuals, artists and writers, the island of Capri is celebrated since the days of the Roman Empire for its striking scenery, delightful climate, and luxurious vegetation, and is one of the most visited touristic sites in Italy. The low season month of October is an ideal period to visit Capri, since hot weather and the large tourist crowds of summer are avoided. More information on the area can be found by visiting the web site http://www.capritourism.com/en/home. TUTORIAL / SURVEY TALKS Tutorial talks given by invited experts are intended to give a broad overview of a given subject with a critical review of technology and applications. They are twice the length of the usual contributed talk with longer abstracts in the Proceedings. AIRLINES & LOCAL TRANSPORTATION The closet airport is the airport of Naples http://www.portal.gesac.it/portal/page/portal/internet), which has direct connections with all main towns of Europe. The harbor of Naples can be reached from the airport by taxi or bus service. Capri is served by frequent ferry (70 min) and hydrofoil (50 min) service to/from the harbor of Naples. Detailed travel information can be found at the BCTM 2009 website (http://www.ieee-bctm.org). HOTEL ACCOMMODATIONS The Capri Palace Hotel has a room block available for conference attendees. Please make your reservations early! Attendees can contact the Capri Palace Hotel directly to make their reservations, as indicated in the BCTM 2009 website (http://www.ieee-bctm.org). When making reservations by phone, be sure to inform the hotel that you are with the IEEE BCTM. Further information for accommodation in Anacapri can be found in the BCTM 2009 website. MEMBERS OF THE PRESS The press is welcome at the BCTM and is offered FREE admission. Just present your business card at the registration desk.

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FUTURE MEETINGS BCTM 2010 will be held in Austin, Texas, USA. Frank Thiel is the BCTM 2010 Conference Chair ([email protected]). A description of the conference sites and details will be posted at: www.ieee-bctm.org. RECRUITING Intensive recruiting undermines the purposes for which the BCTM was established, and is contrary to IEEE policy. BEST STUDENT PAPER AWARD BCTM presents an award for Outstanding Student Paper. To be considered for the award the student must be the lead author and speaker at the conference. The award consists of an engraved plaque and $500, and is based on the technical quality of the published manuscript, clarity of the oral presentation, and the evaluation of the Technical Program Committee. FURTHER INFORMATION BCTM is sponsored by the IEEE Electron Devices Society (EDS) in cooperation with the IEEE Solid-State Circuits Society (SSCS).

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1986-2009 BCTM Short Course

“RF and mm-Wave Applications: Design, Devices, and Characterization” Date: Monday, October 12, 2009 Time: 8:30 AM - 5:45 PM Location: MEDITERRANEA ROOM

Course Overview: Advanced bipolar circuits and technologies have found many successful applications in communications systems in the RF and microwave domain. The development of even faster transistors in recent years has opened the way towards new exciting applications at higher frequencies, including applications such as automotive radar and millimeter-wave imaging. While new applications are explored at higher frequencies, new technologies such as MEMS are being developed for RF and microwave frequencies, targeting solutions and performance that are not possible with bipolar technology alone. For this Short Course we have invited three renowned experts who will cover a wide range of topics, including: devices and technology, circuit design, characterization, modeling, and system applications. We look forward to seeing you!

From mm-Wave Measurement to Design: Measurement, De-embedding and Design Instructor: Dr. Marcel Tutt, Freescale Millimeter wave (mmW) has long been the domain of III-V devices. However, the excellent fT and fMAX now routinely demonstrated by SiGe has enabled this technology to demonstrate excellent circuit performance well into the mmW regime in a variety of circuit applications. Moreover, the availability of SiGe promises higher levels of circuit functionality compared to that seen with III-V technology. Effective utilization of this technology requires knowledge of the necessary experimental techniques and design methodologies. This presentation will cover relevant topics including: relevant signal transmission structures, power and noise measurements, S-parameter measurement and de-embedding and finally design methodologies for mmW circuits. Marcel Tutt received his Ph.D. from the University of Michigan in 1994. His research dealt with noise properties of HEMT’s and GaAs HBT’s. He has worked in the areas of microwaves and millimeterwaves (mmW) for over 20 years. At Texas Instruments he worked on III-V HBT circuit designs for low AM noise and radar applications. When he joined Freescale he developed the modeling process for their III-V HBT’s for handset PA applications. Later, he managed Freescale’s III-V device modeling and characterization group. More recently, he has supervised the development of on-wafer mmW test systems for the characterization of mmW devices and circuits at Freescale. He has published in the areas of modeling and measurement techniques.

Electronic Beam Forming and Phased Arrays Instructor: Prof. Hossein Hashemi, Univ. of Southern California The data-rate of wireless communication systems is limited by signal to noise plus interference (SNIR). Multiple antenna systems can improve the SNIR by dynamically focusing the transmit power towards the desired directions, reducing the interferences through spatial

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filtering, and improving the receiver sensitivity. Phased arrays have been around for over 50 years in high performance military radar systems. Recently, monolithic realization of these systems in silicon has enabled commercial applications such as reliable high-speed wireless communication at 60 GHz, low-cost automotive radars at 24 GHz and 77 GHz, ultra wideband imaging systems at 3-18 GHz, and millimeter-wave imaging. This course covers the basics of multi-antenna systems, narrowband phased arrays, wideband timed arrays, transceiver architectures, circuit building blocks, and several case studies spanning 1-100 GHz for various applications. Hossein Hashemi received the B.S. and M.S. degrees in electronics engineering from the Sharif University of Technology, Tehran, Iran, in 1997 and 1999, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2001 and 2003, respectively. In 2003, he joined the Department of Electrical Engineering–Electrophysics at the University of Southern California (USC), Los Angeles, where he is currently an Associate Professor and the holder of the Gordon S. Marshall Early Career Chair. Dr. Hashemi was the associate editor for the IEEE Transactions on Circuits and Systems — Part I: Regular Paper (2006–2007) and the associate editor for the IEEE Transactions on Circuits and Systems —Part II: Express Briefs (2004–2005). He was the recipient of the 2000 Outstanding Accomplishment Award presented by the von Brimer Foundation, the 2001 Outstanding Student Designer Award presented by Analog Devices, the 2003 Young Scholar Award presented by the Association of Professors and Scholars of Iranian Heritage, and a 2002 Intel fellowship. He was the recipient of the 2008 Defense Advanced Research Projects Agency (DARPA) Young Faculty Award and the National Science Foundation (NSF) CAREER Award. He was a co-recipient of the 2004 IEEE Journal of Solid-State Circuits Best Paper Award and the 2007 IEEE International Solid-State Circuits Conference (ISSCC) Lewis Winner Award for Outstanding Paper.

RF MEMS: Technologies, Modeling, and Reliability Instructor: David Howard, Jazz Semiconductor RF MEMS have been in existence for decades and are capable of performance unachievable in other systems of similar simplicity. Why is it, then, that their adoption has been limited in the multi-billion dollar semiconductor industry? Though this is not the focus of this short course, the question will be raised for each technology reviewed. A brief history of RF MEMS and applications will be presented. Then, using the 2008 ITRS Wireless Roadmap for MEMS as a guide, specific MEMS technologies will be discussed, with more detailed information about performance, modeling and reliability advances and challenges. David Howard received his Sc.B. in Mechanical Engineering, Sc.M, and Ph.D. degrees in Materials Science Engineering, all from Brown University in Providence, Rhode Island, USA. His focus has been in process and device integration for new nodes, features and devices in Si-CMOS based manufacturing, in particular integration of CMOS, interconnect, passive devices, SiGe HBTs, and MEMS. He is currently Executive Director, New Product Technology, at Jazz Semiconductor, Newport Beach, CA, managing new technology implementation for programs that include MEMS, Bi/CMOS and Aerospace. Prior to Jazz, David held positions at IMEC, Rockwell Semiconductor & Conexant Systems (1995-2002). David was a remote assignee to SEMATECH (1998), participates in DARPA programs, and is a member of the ITRS wireless working group.

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1986-2009 BCTM Short Course Schedule

“RF and mm-Wave Applications: Design, Devices, and Characterization” Date: Monday, October 12, 2009 Time: 8:30 AM - 5:45 PM Location: MEDITERRANEA ROOM 8:30-8:45

Welcome: Herbert Knapp and Léon van den Oever

8:45-9:45

From mm-wave measurement to design: Measurement, de-embedding and design Dr. Marcel Tutt, Freescale

9:45-10:05

Break

10:05-11:05

From mm-wave measurement to design: Measurement, de-embedding and design (continued)

11:05-11:25

Break

11:25-12:25

Electronic Beam Forming and Phased Arrays Prof. Hossein Hashemi, University of Southern California

12:30-1:45

Lunch – OLIVIO TERRACE

1:45-2:45

Electronic Beam Forming and Phased Arrays (continued)

2:45-3:05

Break

3:05-4:05

RF MEMS: Technologies, Modeling, Reliability Dr. David Howard, Jazz Semiconductor

4:05-4:25

Break

4:25-5:25

RF MEMS: Technologies, Modeling, Reliability (continued)

5:25-5:45

Course Evaluation

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Tuesday, October 13, 2009 WELCOME AND OPENING REMARKS 9:30–9:45 AM — MEDITERRANEA ROOM

KEYNOTE SPEECH Does the Future of Silicon Reside in Other Materials? Dr. Thomas Skotnicki, STMicroelectronics No more than 30 years ago, the CMOS transistor used to be built with only silicon and silicon-dioxide. The first intrusion of another material was that of SiN, that started to be used in the lateral isolation, in spacers, and finally in the gate dielectric. Next came the time of SiGe and Ge that were tried as gate materials. They continue to be explored for use in the channel region, and have already managed find accceptance in the source/drain regions. Even silicon, even if it still stays strong in the channel of the transistor, is no longer the same as before. It is engineered so as to be mechanically strained, or oriented differently, or both. Therefore, it behaves very differently in comparison with the old-time silicon. Its properties are improved, especially regarding the transport of carriers. This innovation helped silicon to prolong its supremacy but will again be challenged more and more by other materials, including: III-V’s, II-VI’s, graphene, and CNTs. For some specific applications, such as large scale electronics, organic materials are also being studied for the channel region of the transistor. In some other regions the battle is already lost. The use of silicon dioxide as the gate dielectric has been replaced by high-dielectric constant materials such as HfO2 and its alloys with still other materials. The use of poly-silicon as the gate material, has been replaced by some metals or their alloys. The source/drain regions, after the surrender to SiGe in pMOSFET design, now are challenged by SiC at the nMOSFET side. Some metals are also prospected to be used in these regions in the future. If all these attacks are successful, it may happen in the future that the only region where silicon survives is the substrate. Will this be still a silicon technology? Does it mean that the future of silicon is to disappear? This paper will deliberate on these questions and analyze possible scenarios. Thomas Skotnicki is the STMicroelectronics Fellow and Director of the Advanced Devices Program at STMicroelectronics in Crolles, France, where he joined in 1999. From 1985 till 1999, he was with France Telecom R&D (CNET-Centre National d’Etudes des Telecommunications). He received his Masters and EE degrees from Warsaw University of Technology in 1979, the PhD diploma from the Institute of Electron Technology, in Warsaw, Poland in 1985, and in 1993 he received the HDR (Habilitated for Directing Research) diploma from the Institut National Polytechnique de Grenoble, France. In 2007, he received the title of Professor from the President of Poland. The current focus of his program at STMicroelectronics is on Low Power / Low Variability for 22 nm and beyond CMOS, on innovative device architectures, new memory concepts and cells, and on integration of new materials for CMOS. Among his own and his team’s main scientific and R&D achievements (inventor or co-inventor) are: the VDT (Voltage-Doping Transformation) technique and MASTAR models (MASTAR served for calculating the ITRS 2003, 2005 and 2007 CMOS Roadmaps), silicon devices showing large dynamic NR (negative resistance) in room temperature, the SON (Silicon-On-Nothing) technology (awarded Rappaport Award for the best IEEE EDS

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publication of year 2000), capacitor-less Bulk DRAM cell, Totally Silicided (TOSI) metallic gate technology (today known under the name FUSI), Double Gate (DG) gate SON technology, and "dielectric pockets" technology (awarded ESSDERC 2000 Best Paper). T. Skotnicki has led projects, work packages and tasks for EU IST and French national and regional R&D programs. He oversees a vast network of collaborations with European and international universities and research labs. He holds about 50 patents on new devices, circuits and technologies. He has presented over 50 Invited Papers and Short Course lectures, co-edited one book, (co-) authored about 300 scientific papers (review based), and several book chapters in the field of CMOS devices and circuits. From 2001 to 2007, he served as Editor for IEEE Transactions on Electron Devices (received IEEE Recognition Certificate for Valued Services and Contributions). He has been teaching at EPFL (Lausanne) and INPG (Grenoble), and has supervised and led to successful defence of more than 20 PhD theses. He has been serving in numerous Conference Program and Executive Committees (IEDM, VLSI, ESSDERC, ECS, SNW, IWJT), Academia Advisory Boards, Governmental Expert Commissions, R&D Program Steering Committees, and ITRS. He is an IEEE Fellow and SEE Senior Member.

10:30–10:50 PM — Break OLIVO TERRACE 1. Exploring the Limits of SiGe HBTs Tuesday AM — MEDITERRANEA ROOM Session Chair: E. Preisler Co-Chair: D. Knoll

(1.1) 10:50–11:15 AM – A Conventional DoublePolysilicon FSA-SEG Si/SiGe:C HBT Reaching 400 GHz fMAX P. Chevalier, F. Pourchon, T. Lacave, G. Avenier, Y. Campidelli, L. Depoyan, G. Troillard, M. Buczko, D. Gloria, D. Céli, C. Gaquière, and A. Chantre This paper summarizes the work carried out to improve performances of a conventional double-polysilicon FSA-SEG SiGe:C HBT towards 400 GHz fMAX. The technological optimization strategy is discussed and electrical characteristics are presented.

(1.2) 11:15–11:40 AM – A 400 GHz fMAX Fully SelfAligned SiGe:C HBT Architecture S. van Huylenbroeck, A. Sibaja-Hernandez, R. Venegas, S. You, G. Winderickx, D. Radisic, W. Lee, P. Ong, T. Vandeweyer, D. Nguyen, K. De Meyer, and S. Decoutere An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic advancements made to the HBT device.

(1.3) 11:40–12:30 PM – Advanced Process Modules and Architectures for Half-Terahertz SiGe:C HBTs (Invited) S. Decoutere, S. van Huylenbroeck, B. Heinemann, A. Fox, P. Chevalier, A. Chantre, T. Meister, K. Aufinger, and M. Schröter

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The European project DOTFIVE addresses evolutionary scaling of selfaligned SiGe:C HBTs, investigates novel HBT architectures and develops novel process modules to push SiGe BiCMOS technology towards 500 GHz fMAX and 2.5 ps gate delay.

2. Performance SiGe HBTs

and

Operating

Constraints

of

Tuesday AM – CAVALLI ROOM Session Chair: P. Zampardi Co-chair: M. Tutt

(2.1) 10:50–11:15 AM – Experimental Study of the SOA of SiGe HBTs on SOI (Student) P. Cheng, S. Seth, C. Grens, T. Thrivikraman, M. Bellini, J.D. Cressler, J. Babcock, T. Chen, J. Kim, and A. Buchholz The safe-operating-area of a variety of both bulk and thick-film SOI SiGe HBTs has been investigated using DC and pulsed-mode output characteristics, as well as RF gain and linearity measurements. RF operation of SiGe HBTs on SOI beyond the traditionally-defined safeoperating-area showed only minor degradation, and actually improved RF linearity.

(2.2) 11:15–11:40 AM – Electrothermal Behavior of Highly-Symmetric Three-Finger Bipolar Transistors (Student) L. La Spina, V. d'Alessandro, S. Russo, N. Rinaldi, and L.K. Nanver Design guidelines are established for improving the electrothermal stability of multi-finger bipolar transistors. A threefold rotationalsymmetric topography is proposed to achieve a significant enlargement of the safe operating area as compared to the more conventional parallel-finger designs.

(2.3) 11:40–12:05 AM – Theoretical Analysis and Modeling of Bipolar Transistor Operation Under Base Current Reversal M. Costagliola and N. Rinaldi A two-dimensional theoretical analysis of bipolar transistor operation under reversal base current conditions is presented. This model describes the current crowding effect occurring when the device is biased above the open-base breakdown voltage BVCEO, also known as the “pinch-in” effect.

(2.4) 12:05–12:30 PM – Comparing RF Linearity of npn and pnp SiGe HBTs (Student) S. Seth, P. Cheng, C. Grens, J.D. Cressler, J. Babcock, Y. Liu, J. Kim, and A. Buchholz Linearity characteristics of complementary SiGe HBTs are investigated. At low bias, both devices exhibit similar linearity and gain. The pnp’s offers advantages over the npn’s in high bias, however, and linearity of both devices improves with frequency. The underlying mechanisms are addressed.

3. Software Defined Radio Tuesday AM — MONTE SOLARO ROOM Session Chair: J.B. Begueret

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Co-Chair: D. Teeter

(3.1) 10:50–11:40 AM – Future Needs in RF Reconfiguration From a System Point of View (Invited) D. Morche and S. Pruvost This paper presents the new reconfiguration requirements in RF chipset from a system point of view. It will first concentrate on application constraints by considering opportunistic radio and will then study the constraints arising from technology evolution and particularly the variability issue.

(3.2) 11:40–12:05 AM – An Integrated 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and 20-28 GHz Frequency Synthesizer for Software-Defined Radio Applications (Student) S.A. Osmany, F. Herzel, and J.C. Scheytt We present an integrated frequency synthesizer which is able to provide in-phase / quadrature phase signals over the frequency bands of 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and in-phase signals over 20-28 GHz, for software-defined radio applications. An integrated voltage controlled oscillator (VCO) with 34% tuning range and a set of high speed dividers are used to accomplish all the frequencies.

(3.3) 12:05–12:30 PM – A Two-Channel, Ultra-LowPower, SiGe BiCMOS Receiver Front-end for X-Band Phased Array Radars (Student) T. Thrivikraman, W.-M.L. Kuo, and J.D. Cressler We present an ultra-low-power SiGe BiCMOS receiver for X-band phased-array radars. The receiver contains two LNAs and 3-bit phase shifter, consuming 4 mW of dc power with 10 dB of gain and 5 dB NF.

Luncheon 12:30–1:55 PM — OLIVO TERRACE 4. RF Building Blocks Tuesday PM – MEDITERRANEA ROOM Session Chair: L. van den Oever Co-Chair: D. Lie

(4.1) 2:00–2:25 PM – Large- and Small-Signal Broadband 60 GHz Power Amplifier (Student) A. Hamidian and G. Boeck This paper presents a fully integrated 60 GHz single stage power amplifier (PA) with a cascode topology. The PA achieves the 1 dB bandwidth of more than 9 GHz, from 57 GHz to 66 GHz, and a 3 dB bandwidth of more than 18 GHz (30%), from 51 GHz to 69 GHz, with a power added efficiency (PAE) better than 9% from 57 GHz to 65 GHz.

(4.2) 2:25–2:50 PM – A SiGe:C BiCMOS LNA for 60 GHz Band Applications (Student) R. Severino, T. Taris, Y. Deval, D. Belot, and J.-B. Begueret A new differential LNA dedicated to 60 GHz band has been implemented in a 130 nm BiCMOS technology intended for millimeter-

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wave applications. The two stage cascode LNA achieves a 21.1 dB maximum gain at 61.5 GHz, a P1dB of -21.2 dBm, a minimum (simulated) noise figure of 4.3 dB, at 10.2 mW power consumption.

(4.3) 2:50–3:15 PM – A Low Power, 1.8-2.6 dB Noise Figure, SiGe HBT Wideband LNA for Multiband Wireless Applications (Student) D. Howard, X. Li, and J.D. Cressler We present a wideband, very low power, SiGe LNA, covering the frequency range of 5-11 GHz, achieving a peak gain of 19.2 dB and 66% fractional bandwidth. The LNA exhibits a Noise Figure (NF) of 1.82.6 dB across band and consumes only 9 mW of power.

(4.4) 3:15–3:40 PM – Low-power K-band PseudoStacked Mixer with Linearity Enhancement Technique N. Shiramizu, T. Masuda, T. Nakamura, and K. Washio A low-power transmitter mixer and a receiver mixer operating in the Kband frequency region have been developed. The transmitter mixer achieves a conversion gain of -0.1 dB, and input P1dB of -11 dBm, and the receiver mixer achieves a conversion gain of 11.2 dB and input P1dB of –23 dBm.

(4.5) 3:40–4:05 PM – An 8.7-13.8 GHz Transformercoupled Varactor-less Quadrature Currentcontrolled Oscillator RFIC (Student) X. Geng and F. Dai This paper presents an 8.7-13.8 GHz transformer-coupled varactorless quadrature current-controlled oscillator (QCCO) RFIC. The prototype QCCO achieves a 45.3% tuning range, draws 8-18 mA current under a 1.8 V power supply. The measured phase noise is 86.8 dBc/Hz at 1 MHz offset and -110 dBc/Hz at 10 MHz offset with 11.02 GHz quadrature outputs.

5. Device Physics: Simulation and Structures Tuesday PM – CAVALLI ROOM Session Chair: J.-S. Rieh Co-Chair: M. Tutt

(5.1) 2:00–2:50 PM – Electron Transport in Extremely Scaled SiGe HBTs (Invited) S.-M. Hong and C. Jungemann Transport and noise in a THz-SiGe HBT are investigated using classical TCAD tools and full solutions of the more physics-based Boltzmann equation. The transport is quasi-ballistic and the classical models fail to yield accurate results.

(5.2) 2:50–3:15 PM – A Novel Superjunction Collector Design for Improving Breakdown Voltage in HighSpeed SiGe HBTs (Student) J. Yuan and J.D. Cressler A novel superjunction collector design is proposed for improving the speed / breakdown voltage trade-off in SiGe HBTs. A SiGe HBT with simulated fT = 101 GHz, fMAX = 351 GHz, and BVCEO = 3.0 V is achieved.

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(5.3) 3:15–3:40 PM – A Novel Device Structure using a Shared-Subcollector, Cascoded Inverse-Mode SiGe HBT for Enhanced Radiation Tolerance (Student) T. Thrivikraman, A. Appaswamy, S. Phillips, A. Sutton, E. Wilcox, and J.D. Cressler We present a novel device structure using an inverse-mode, cascoded (IMC) SiGe HBT for improved heavy-ion irradiation tolerance. The cascoded SiGe device consists of a forward-mode, common-emitter HBT cascoded with a common-base inverse-mode HBT.

6. State-of-the-art Measurements and Parameter Extraction Tuesday PM — MONTE SOLARO ROOM Session Chair: F. Pourchon Co-Chair: R. van der Toorn

(6.1) 2:00–2:25 PM – SiGe HBT Noise Parameter Extraction using In-Situ Silicon Integrated Tuner in the mmW Range of 60 – 110 GHz (Student) Y. Tagro, D. Gloria, S. Boret, and G. Dambrine A silicon integrated tuner is presented for use in extracting millimeterwave noise parameters through a multi-impedance method. This tuner is directly integrated with on-wafer transistor test structures. A gamma of 0.70 has been achieved and an NFmin of 2.6 dB has been extracted on SiGe HBTs at 60GHz.

(6.2) 2:25–2:50 PM – Investigation of High Frequency Coupling Between Probe Tips and Wafer Surface (Student) J. Bazzi, C. Raya, A. Curutchet, and T. Zimmer This paper presents an investigation of the coupling between probes tips and the wafer surface through EM-simulation, and compares the simulation results to measurements. It is pointed out that the results are very dependent on the adjacent structures lying under the probe tips. Different solutions are analyzed to master and/or reduce the coupling and assure reproducibility of measurements.

(6.3) 2:50–3:15 PM – Distributed De-embedding Technique For Accurate On-chip Passive Measurements Based on Open-Short Structures H. Veenstra, M. Notten, D. van Goor, and J. Mills A technique is introduced to derive a distributed model for standard Open-Short de-embedding structures. A significant improvement in accuracy is obtained above 10 GHz if long de-embedding lines are unavoidable, as demonstrated for a 470 pH inductor.

(6.4) 3:15–3:40 PM – Evaluating the Self-Heating Thermal Resistance of Bipolar Transistors by DC Measurements: a Critical Review and Update (Student)

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S. Russo, V. d'Alessandro, L. La Spina, N. Rinaldi, and L.K. Nanver A comprehensive comparative analysis of the most relevant DC measurement techniques developed to determine the self-heating thermal resistance of bipolar devices is presented. An improved, but still simple extraction approach, is proposed for silicon BJTs with nonnegligible Early effect, where use of traditional HBT-devised methods may entail significant inaccuracies.

4:05–4:25 PM — Break OLIVO TERRACE 7. Advanced Modeling and Characterization Tuesday PM – MEDITERRANEA ROOM Session Chair: D. Weiser Co-Chair: B. Ardouin

(7.1) 4:25–4:50 PM – Compact Model of Zener Tunneling Current in Bipolar Transistors, Featuring a Smooth Transition to Zero Forward Bias Current (Student) V. Milovanovic, R. van der Toorn, P. Humphries, D.l Vidal, and A. Vafanejad We present a physics-based compact model of Zener tunneling current, as it may occur in highly-doped, reverse-biased, base-emitter junctions of bipolar transistors. Our model features an infinitely differentiable transition, at zero bias, to zero tunneling current in the forward-bias regime. A verification of the model on typical modern industrial bipolar technology is presented.

(7.2) 4:50–5:15 PM – SiGe Bipolar ESD Modeling for a Full Chip ESD Simulation S. Parthasarathy, G. Coram, J.-J. Hajjar, and J. Salcedo A new SPICE-compatible compact model is developed to simulate the current and voltage characteristics of SiGe bipolar devices beyond their breakdown. The enhanced bipolar models are benchmarked versus device-level TLP (transmission line pulsing) measurements and used in full-chip ESD simulation to optimize the circuit design for ESD robustness.

(7.3) 5:15–6:05 PM – Matching is Key to Better Processes (Invited) H. Tuinhout Systematic and random parametric mismatches are major performance limiters as well as causes of re-designs for mixed-signal circuits. Therefore it is extremely important to measure, analyze, understand and document parametric mismatch mechanisms. This paper summarizes the main requirements and techniques for proper mismatch characterization of active and passive IC devices.

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2009 BCTM SPONSORS SILVER SPONSOR

SPONSORS

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IEEE International LLC, c/o IEEE BCTM

BCTM 2009 REGISTRATION Please use the web site to register: http://www.ieee-bctm.org Prices include a 20% VAT paid on fees. Advance registration deadline is September 18, 2009. (1) Conference Registration Cost: ADVANCE ON-SITE IEEE Members $830 (≈ €590) …OR ....$900 (≈ €640) Non-Members $900 (≈ €640) …OR ….$970 (≈€690) Students $420 (≈ €300) …OR … $470 (≈€320) (2) Guest Fee for Dinner Banquet: ADVANCE (limited) ……………………..$100/person(≈ €75) ON-SITE……………………………….. $180/person(≈ €130) (3) Extra 2009 Proceedings w/ CD: Members $150 (≈€110) .. Non-members$180(≈ €130) (4) Previous Proceedings w/ CD (if available): Members $130 (≈€95) Non-members $160 (≈ €115) (5) Archive CD (1986-2000 Proceedings): Members $130 (≈€95) Non-members $160(≈ €115)

Registration Fees: SHORT COURSE (1) Course cost: $770 (≈€550) $320 (≈€230)

MEMBERS/NON-MEMBERS STUDENTS

(2) SHORT COURSE NOTES (included for those attending the Short Course) $190) (≈€135)

All charges will be made in USD. The Euro equivalents shown above are approximate and the actual transaction amount (if not in USD) will depend on the current exchange rate at the time of the transaction.

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Deadline for Advance Reservation is September 18, 2009

Single or Double Occupancy rate per night…€280

Please check hotel information on the BCTM 2009 website (http://www.ieee-bctm.org/)

HOTEL REGISTRATION & INFORMATION

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8. Signal Processing Tuesday PM – CAVALLI ROOM Session Chair: H. Knapp Co-Chair: K. Murata

(8.1) 4:25–5:15 PM – BiCMOS High-Performance ICs: From DC to mm-Wave (Invited) B. Smolders, H. Gul, E. van der Heijden, P. Gamand, and Geurts

M.

Progress with Si and SiGe-based BiCMOS technologies over the past few years has been very impressive. This has enabled the implementation of traditional microwave and emerging mm-wave applications in silicon. This paper gives an overview of several highperformance ICs that have been implemented in a state-of-the-art BiCMOS technology (QUBIC4). Examples of high-performance ICs are described, ranging from basic building blocks for mobile applications to highly integrated receiver and transmitter ICs for applications up to the mm-wave range.

(8.2) 5:15–5:40 PM – A Precision Monolithic Waveform Generator With 2,000,000:1 Exponential Sweep Range E. Modica and D. Bowers The circuit described is a monolithic waveform generator with a 2,000,000:1 control range, facilitated by means of simultaneous linear and exponential control ports. The generator outputs square waves and low-distortion triangle and sinusoidal waveforms.

(8.3) 5:40–6:05 PM – Current and Voltage ADC Using a Differential Pair of Single Electron Bipolar Avalanche Transistors M. Lany and R. Popovic \

Single-electron bipolar avalanche transistors (SEBATs) enable current sensing by electron counting at room temperature. Here, differential SEBAT circuits combining the functions of amplification and analog-todigital (A/D) conversion are proposed and characterized for two applications: Low-current A/D conversion and differential voltage A/D conversion.

6:05–8:00 PM Break

8:00–11:30 PM Dinner Banquet

CAPRI PALACE HOTEL

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Wednesday, October 14, 2009 9. Emerging Technologies Wednesday AM – MEDITERRANEA ROOM Session Chair: B. Hecht

(9.1) 8:30–9:10 AM — Ultra-Thin Chip Fabrication for Next-Generation Silicon Processes (Invited) J. Burghartz Extremely thin silicon chip layers are expected to enable emerging 3D IC, system-in-foil, power and other technologies. The Chipfilmtechnology presented and discussed in this talk utilizes local porous silicon formation, sintering and epitaxial overgrowth to manufacture wafer substrates with buried cavities for an a priori definition of the chip's thickness, which has been demonstrated down to 6 µm. Chipfilm complements the established wafer back-thinning techniques in particular where such extremely small chip thickness and excellent mechanical stability is required.

(9.2) 9:10–9:50 AM — 3D Integration Technologies for MEMS/IC Systems (Invited) P. Ramm 3D integration is a key solution to the predicted performance problems of future ICs, and offers extreme miniaturization and cost-effective fabrication of so-called More-than-Moore products (e.g., MEMS + IC systems). Through-Silicon-Via (TSV) technologies enable high interconnect performance at relatively high fabrication cost compared to 3D packaging. In general, there is no single 3D integration technology suitable for the fabrication of the large variety of envisioned 3D integrated systems. Moreover, even one single product may need several different technologies for a cost-effective fabrication. Wireless ® sensor systems (e.g., e-CUBES ) are an excellent example of this need for a suitable mixture, as will be described.

(9.3) 9:50–10:30 AM — Nano-tera.ch: NanoTechnologies for Tera-Scale Problems (Invited) G. De Micheli This talk will address the aim and scope of the nano-tera.ch program, a publicly-funded research program focusing on the applications of nano-technologies to distributed embedded systems. In particular, some projects address nanoelectronic design with silicon nanowires and carbon nanotubes, as well as the integration of sensors and MEMS. The use of these technologies offers unprecedented opportunities in the areas of biosensing for health and environmental management.

(9.4) 10:30–11:10 AM — Gallium Nitride (GaN) High Power Devices for Advanced Commercial and Military Applications (Invited) J. Shealy Next generation commercial and military systems require high power amplifiers (HPAs) with superior performance such as higher efficiency, improved thermal performance, wider bandwidth and higher output power. Using a 0.5 µm, 48 V GaN-on-SiC process, a family power GaN amplifiers (from 8 W to 300 W) have been developed for applications in

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the frequency range of 30 MHz to 4 GHz. Such devices clearly demonstrate superior power-bandwidth product of GaN for military applications such as radar, military communications and electronic warfare. For commercial applications, a family of linear amplifiers targeting 3GPP, LTE and WiMax cellular base stations offer high efficiency operation. Finally, amplifier modules for emerging applications, such as RF lighting and CATV distribution, offer differentiated performance using GaN technology.

11:10–11:30 AM — Break OLIVO TERRACE 10. High-Speed Digital Wednesday AM – MONTE SOLARO ROOM Session Chair: H. Veenstra Co-Chair: B. Hecht

(10.1) 11:30–11:55 AM – A Cable Equalizer with 31 dB of Adjustable Peaking at 52 GHz (Student) A. Balteanu and S. Voinigescu A 70 Gbps equalizer in 0.13 µm SiGe BiCMOS with peak gain of 12.2 dB at 52 GHz and 31 dB of adjustable gain control is presented. Equalization is shown at 70 Gbps for 7.2 dB of channel loss.

(10.2) 11:55–12:20 PM – A SiGe BiCMOS Burst-mode Transimpedance Amplifier Using Fast and Accurate Automatic Offset Compensation Technique for 1G/10G Dual-rate Transceiver S. Nishihara, M. Nakamura, T. Ito, T. Kurosaki, Y. Ohtomo, and A. Okada This paper describes a SiGe BiCMOS burst-mode transimpedance amplifier featuring fast gain switching and accurate automatic offset compensation with feed-forward configuration, to constitute a 1G/10G dual-rate optical receiver for next-generation optical access systems.

(10.3) 12:20–12:45 PM – High-Speed, Low-Power Phase Accumulators for DDS Applications in SiGe Bipolar Technology (Student) B. Laemmle, C. Wagner, H. Knapp, L. Maurer, and R. Weigel Two phase accumulators for use in direct digital synthesis (DDS), with 10 and 8 bit resolution, 7 and 15 GHz maximum clock rate, and power dissipation of 237 W and 303 mW, respectively, are presented. The accumulators are designed to retain phase coherence while a frequency switch is performed and integrated in a DDS to simplify measurement.

11. SiGe BiCMOS Platforms and Devices Wednesday AM – CAVALLI ROOM Session Chair: P. Chevalier Co-Chair: K. Yonemura

(11.1) 11:30–11:55 AM – A 0.13 µm SiGe BiCMOS Technology Featuring fT / fMAX of 240 / 330 GHz and Gate Delays Below 3 ps

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H. Rücker, B. Heinemann, W. Winkler, R. Barth, J. Borngräber, J. Drews, G. Fischer, A. Fox, T. Grabolla, U. Haak, D. Knoll, F. Korndörfer, A. Mai, S. Marschmeyer, D. Schmidt, J. Schmidt, K. Schulz, B. Tillack, D. Wolansky, and Y. Yamamoto A 0.13 µm SiGe BiCMOS technology is presented, featuring highspeed SiGe HBTs along with high-voltage SiGe HBTs. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers operating at 122 GHz, and LC oscillators above 200 GHz, are demonstrated.

(11.2) 11:55–12:20 PM – Integration of SiGe NPN Devices with Tunable Collector Profiles Using a Single Mask P. Hurwitz, E. Preisler, and M. Racanelli An alternate local collector masking scheme is demonstrated in 0.18 µm SiGe BiCMOS technology to create a set of tunable breakdown devices with a single mask. The method relies on a resist post in the emitter window.

(11.3) 12:20–12:45 PM – SiGe HBT npn Device Optimization for RF Power Amplifier Applications A. Joseph, M. McPartlin, L. Hughes, J. Forsyth, P. Candra, R. Previti-Kelly, and M. Doherty This paper describes the optimization approach of npn SiGe HBTs for RF power amplifier performance. Minimizing the collector resistance and barrier effects in a power device are important for optimization of RF characteristics. We demonstrate that a PA with 66.5% PAE, 14.1 dB of gain, 14.1 P1dB, and 15.4 dBm output power can be achieved in SiGe.

12:45–2:20 PM — Luncheon and Luncheon Talk “Pompei Excavations” Dr. Claudia Palazzolo Olivares

OLIVO TERRACE 12. mmW BiCMOS Circuits Wednesday PM – MEDITERRANEA ROOM Session Chair: P. Garcia Co-Chair: P. Davis

(12.1) 2:20–2:45 PM – A 140 GHz Double-Sideband Transceiver with Amplitude and Frequency Modulation Operating Over a Few Meters (Student) E. Laskin, P. Chevalier, B. Sautreuil, and S. Voinigescu A 140 GHz double-sideband transceiver with amplitude and frequency modulation is demonstrated in SiGe BiCMOS technology. The first Doppler experiment above 100 GHz is described, and data transmission at 4 Gb/s over air is shown at 140 GHz. An amplifier with 21 dB of gain at 160 GHz in SiGe HBT is also presented.

(12.2) 2:45–3:10 PM – A 122 GHz Receiver in SiGe Technology

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K. Schmalz, W. Winkler, J. Borngräber, W. Debski, Heinemann, and C. Scheytt

B.

A 122 GHz sub-harmonic receiver for imaging and sensing applications has been realized, which consists of a single-ended LNA, a push-push VCO with 1/32 divider, a polyphase filter, and a subharmonic mixer. The down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure is 11 dB. The 3-dB bandwidth reaches from 125 GHz to 129 GHz. The input 1-dB compression point is at -40 dBm. The receiver consumes 139 mA at a supply voltage of 3.3 V.

(12.3) 3:10–3:35 PM – A 77 GHz 3.3 V Three-Channel Transceiver S. Trotta, B. Dehlink, A. Ghazinour, D. Morgan, and J. John We present a 77 GHz three channel transceiver for automotive radar application designed in a 200 GHz SiGe BiCMOS technology. The chip features a Tx channel, a prescaler by 1536, and three Rx channels. The Rx channels show a typical conversion gain of 19 dB while the NFssb lower than 13 dB at 100 kHz. The phase noise is 74 dBc/Hz at 100 kHz offset. The output power is 9 dBm. At a 3.3 V supply, the chip consumes 533 mA.

(12.4) 3:35–4:00 PM – 168 GHz Dynamic Frequency Divider in SiGe:C Bipolar Technology H. Knapp, T.F. Meister, W. Liebl, K. Aufinger, H. Schaefer, J. Boeck, S. Boguth, and R. Lachner This paper presents a SiGe bipolar dynamic frequency divider operating up to a maximum frequency of 168 GHz. The circuit is based on a first regenerative divider stage which is followed by a static divider and an output buffer and consumes 320 mW.

(12.5) 4:00–4:25 PM – High-Q Passives for mm-Wave SiGe Applications M. Kaynak, C. Wipf, R. Scholz, B. Tillack, W.-G. Lee, Y.S. Kim, J.J. Yoo, and J.W. Kim Backside deep-silicon etching technique is used for achieving high-Q inductors in a standard 0.25 µm SiGe process. Inductors with different values were designed and evaluated. For low value inductances, a significant increase of the quality factor and self-resonance frequency are observed.

13. Trends in Si And SiC Power Devices Wednesday PM – CAVALLI ROOM Session Chair: P. Tounsi Co-Chair: P. Mawby

(13.1) 2:20–3:10 PM – Overview of MOS-Bipolar Power Device Needs for an Energy Sustainable S. Society (Invited) Ekkanath Electricity is the most common form of energy used in all walks of life, and energy consumption is growing at a rate of 2.6% worldwide. MOSBipolar power semiconductor devices are essential control elements used in electricity generation, transmission and delivery. Worldwide, extensive research is underway to develop technologies based on MOS-Bipolar devices (e.g., IGBTs, CSTBTs, IEGTs and CIGBTs) in silicon and wide bandgap semiconductors to achieve ultra-low power

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losses. This paper will be provide an overview of developments in silicon-based power device technologies and will attempt to provide a wider perspective and identify the challenges for the future.

(13.2) 3:10–3:35 PM – Deep Trench Isolation Integrated in a 0.13 µm BiCD Process Technology for Analog Power ICs H. Kitahara, T. Tsukihara, M. Sakai, J. Morioka, K. Deguchi, K. Yonemura, K. Watanabe, T. Kikuchi, S. Onoue, K. Shirai, and K. Kimura Deep trench isolation (DTI) is successfully integrated in a 0.13 µm BiCD process. The DTI technology contributes to increased density of high voltage devices and reduced parasitic bipolar action.

(13.3) 3:35–4:00 PM – Numerical Simulations of Al Implanted 4H-SiC Diodes and Modeling an Explicit Carrier Trap Effect Due to the Non-substitutional Doping Concentration F. Pezzimenti, F. Della Corte, and R. Nipoti The experimental characteristics of Al implanted 4H-SiC p-i-n diodes are interpreted through numerical simulations focused on a deep defects profile related to the non-substitutional Al doping and the Al acceptor energy level within the material.

(13.4) 4:00–4:25 PM – Analytical Model for the Forward Current in Al-Implanted 4H-SiC p-i-n Diodes Over a Wide Range of Temperatures F. Pezzimenti, L.F. Albanese, S. Bellone, and F. Della Corte The forward J-V characteristics of 4H-SiC p-i-n diodes are studied in a wide range of currents and temperatures by means of an analytical model which describes in detail the role of the various physical parameters.

End of Conference

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BCTM EXECUTIVE COMMITTEE Frank Thiel (Zarlink, USA, General Chair) David Ngo (RFMD, USA, Technical Program Chair) Alvin Joseph (IBM, USA, Vice-Technical Program Chair) John D. Cressler (Georgia Tech, USA, Publications Chair) Bruce Hecht, (Analog Devices, USA, Emerging Technologies Chair) Paul C. Davis (Consultant, USA, Finance Chair) Herbert Knapp (Infineon, Germany, Short Course Chair) Leon van den Oever (Radio Semiconductor Corp., The Netherlands, Short Course Vice-Chair) Nic Rinaldi (Univ. of Naples, Italy, Local Arrangements Chair) Doug Teeter (RFMD, USA, Publicity Chair) Don Lie (Texas Tech. Univ., USA, JSSC Guest Editor) Janice Jopke (CCS Events, Conference Manager) Herbert Knapp (Infineon, Germany, Analog/Digital Chair) Marcel Tutt (Freescale Semiconductor, USA, Device Physics Chair) Thomas Zimmer (Univ. of Bordeaux, France, Modeling Chair) Jean-Baptiste Begueret (Univ. of Brodeaux, France, RF Chair) Phil Mawby (University of Warwick, UK, Power Devices Chair) Pascal Chevalier (STMicroelectronics, France, Process Technology Chair) Marise Bafleur (LAAS/CNRS, France, Past General Chair) Yih-Feng Chyan (Broadcom, USA, Distant Past General Chair) ANALOG/DIGITAL DESIGN SUBCOMMITTEE Herbert Knapp (Infineon, Germany, Chair) Jim Haslett (University of Calgary, Canada) Bruce Hecht (Analog Devices, USA) Koichi Murata (NTT Photonics Lab, Japan) Hugo Veenstra (Philips Research, The Netherlands) Sorin Voinigescu (University of Toronto, Canada) MODELING/SIMULATION SUBCOMMITTEE Thomas Zimmer (University of Bordeaux, France, Chair) Bertrand Ardouin (XMOD Technologies, France) Adam DiVergillo (Tektronix, USA) Ramana Malladi (IBM, USA) Ramses van der Toom (TU Delft, The Netherlands) James Victory (Sentinel IC Tech, USA) Doug Weiser (Texas Instruments, USA) Franck Pourchon (STMicroelectronics, France) DEVICE PHYSICS SUBCOMMITTEE Marcel Tutt (Freescale Semiconductor, USA, Chair) Jeff Babcock (National Semiconductor, USA) Kyushik Hong (Samsung, Japan) Lis Nanver (TU Delft, the Netherlands) Guofu Niu (Auburn University, USA) Jayasimha Prasad (Maxim, USA) Jae-Sung Rieh (Korea University, Korea) Nic Rinaldi (University of Naples, Italy) Pete Zampardi (Skyworks, USA) PROCESS TECHNOLOGY SUBCOMMITTEE Pascal Chevalier (STMicroelectronics, France, Chair) Wibo van Noort (National Semiconductor, USA) Dieter Knoll (IHP, Germany) Jim Kirchgessner (Freescale Semiconductor, USA) Katsuya Oda (Hitachi, Japan) Edward Preisler (Jazz Semiconductor, USA) Rob Rassel (IBM, USA) Koji Yonemura (Toshiba, Japan)

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RF SUBCOMMITTEE Jean-Baptiste Begueret (Univ. of Bordeaux, France, Chair) Paul Davis (Consultant, USA) Foster Dai (Auburn University, USA) Patrice Garcia (STMicroelectronics, France) Gary Yan-Kit Hau (Anadigics, USA) Donald Lie (Texas Tech University, USA) John Rogers (Alereon, USA) Doug Teeter (RFMD, USA) Leon van den Oever (Radio Semiconductor Corp., The Netherlands) POWER-DEVICES SUBCOMMITTEE Phil Mawby (University of Warwick, UK, Chair) Mohamed Darwish (Fultec Semiconductor, USA) Saurabh Desai (National Semiconductor, USA) Gary Dolny (Fairchild Semiconductor, USA) Tom Krutsick (Legerity, USA) Akio Nakagawa (Toshiba, Japan) Sameer Pendharker (Texas Instruments, USA) Patrick Tounsi (LAAS/CNRS, France)

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IEEE BCTM 6611 Countryside Drive Eden Prairie MN 55346 USA

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