2014 IEEE 28th International Parallel & Distributed Processing Symposium Workshops
An ILP-based Optimal Circuit Mapping Method for PLDs Keisuke Inoue Hiroki Nishiyama, Masato Inagi, Mineo Kaneko Shin’ichi Wakabayashi, Shinobu Nagayama Graduate School of Information Sciences Global IT Department School of Information Science Hiroshima City University Kanazawa Technical College JAIST Hiroshima, 731–3194 JAPAN Kanazawa, 921–8164 JAPAN Kanazawa, 923–1211 JAPAN {nishiyama, inagi, wakaba, s naga}@hiroshima-cu.ac.jp
[email protected] [email protected]
Abstract—In this paper, we discuss an ILP-based method for simultaneous optimal technology mapping, placement and routing for programmable logic devices, such as FPGAs, as a fundamental research for architecture and algorithm evaluation. In general, heuristic methods are used for technology mapping, placement and routing, and many such methods have been developed. Although they are used to obtain high quality solutions within a practical time period, high quality is not guaranteed. In addition, the separated design processes make the final solutions not optimal. Simultaneous and optimal methods are useful for evaluating and developing heuristic methods, even if optimal methods take a long time. Furthermore, they can be used to evaluate reconfigurable architectures. In experiments, we confirmed that the optimal total wire length and critical path length of small circuits were obtained using our method. Critical path lengths were reduced by 28.6% on average when optimized.
size). Thus, direct placement of the circuit (without technology mapping) can substitute technology mapping if multiple logic elements are allowed to be placed to the same logic block (e.g., [9], [10], [11]). We employ such an approach for technology mapping. Note that the existing methods proposed in [9] and [10] are examples of exact methods for simpler simultaneous technology mapping and placement problems. In this paper, we first model a circuit netlist and the architecture of a PLD as graphs, and define the placement and routing of the circuit to the PLD as a kind of graph embedding problem. Then, we formulate such a graph embedding problem as an ILP problem, and optimally solve the problem by using ILP solvers such as CPLEX[8]. Because our proposed method can obtain exactly optimal solutions for small circuits, it can help the evaluation and development of heuristic methods and reconfigurable architectures, as well as the generation of placement and routing libraries of small modules. In experiments, we confirmed that our proposed method obtained optimal solutions for small circuits. The rest of this paper is organized as follows. In Section II, a few definitions and our ILP formulation of a simple graph embedding problem are shown. In Section III, the definitions of graphs modeling a circuit netlist and the architecture of a PLD are shown, and an extended graph embedding problem is defined to handle the graphs. Section IV presents our ILP formulation of the extended problem. Section V shows experimental results, and finally Section VI concludes this study.
I. I NTRODUCTION In circuit design for programmable logic devices (PLDs,) such as a field programmable gate array (FPGA), technology mapping, placement and routing are important processes. These processes can be considered as combinatorial optimization problems, and heuristic methods are used to solve these problems because of their huge solution space. Heuristic methods are used to obtain good solutions within a practical time period, and they have been proposed to solve these problems (e.g., [1], [2] for technology mapping, [3], [4] for placement and routing). However, heuristic methods are not meant for obtaining optimal solutions, and it is difficult to absolutely evaluate solutions by comparing with heuristic methods. Furthermore, because technology mapping, placement, and routing are performed separately in general circuit design processes for PLDs and different objective functions are used in different processes (even in a state-of-the-art FPGA mapping tool [5], [6]), it is more difficult to evaluate all three processes in total. Therefore, we propose a simultaneous technology mapping, placement and routing method based on integer linear programming (ILP) [7], for which efficient solvers have been provided (e.g., [8]). Technology mapping for PLDs is a process to create small groups of logic elements of the target circuit to help place the circuit on a PLD (by reducing the problem 978-1-4799-4116-2/14 $31.00 © 2014 IEEE DOI 10.1109/IPDPSW.2014.33
II. P RELIMINARIES A. Directed Steiner Tree Given a directed graph, a specified vertex r, and a set of specified vertices (not including r), a directed Steiner tree is defined as a subgraph, which is a minimal directed tree that includes all the specified vertices, in particular, the vertex r as its root. Given a directed graph H = < N, A >, a specified vertex r ∈ N , and a set of other specified vertices NL ⊂ N , the set of all the possible directed Steiner trees is defined as ST (NL , r). Nst and Ast denote the sets of all the vertices and edges included in st ∈ ST (NL , r), respectively. That is, st = < Nst , Ast >. 251
Fig. 1. An example of a directed graph H (the entire graph) and a directed Steiner tree st ∈ ST (NL , r) (shown in heavy lines)
Fig. 2. An example of graph embedding
An example of a directed graph H and a directed Steiner tree st ∈ ST (NL , r) in H is shown in Fig.1. Here, a directed Steiner tree st ∈ ST (NL , r) when NL = {n1 , n6 , n8 } and r = n1 is shown in heavy lines.
Fig. 3. Examples in which conditions (b -1)-(b -4) are satisfied for el = (vp , vq ) ∈ E.
B. Graph Embedding and Its ILP Formulation. In this section, first, we formulate the graph embedding from one simple (i.e., non-directed) graph G = < V, E > called the guest graph to the other H = < N, A > called the host graph. Then, we derive an ILP-based formulation of the graph embedding. 1) Formulation of Graph Embedding: Take two simple graphs G =< V, E > and H =< N, A >, where V = {v0 , v1 , ..., vP }, E = {e0 , e1 , ..., eL }, N = {n0 , n1 , ..., nI }, and A = {a0 , a1 , ..., aS }. Then, let φV be a mapping from V to N and φE be a mapping from E to P (A), where P (A) denotes the power set of A. Here, the set of all paths that have endpoints ni ∈ N and nj ∈ N is defined as P (ni , nj ). The set of edges that make a path p ∈ P (ni , nj ) is defined as Ap . Then, the pair of mappings (φV , φE ) is defined as graph embedding (from G to H), if the mappings satisfy the conditions (a) and (b) shown below. (a) ∀vp ∈ V, ∃ni ∈ N : φV (vp ) = ni (b) ∀el ∈ E where el = (vp , vq ) : condition (b-1) or (b-2) is satisfied. (b-1) φV (vp ) = φV (vq ) ∧ φE (el ) = Ap ∃p ∈ P (φV (vp ), φV (vq )). (b-2) φV (vp ) = φV (vq ) ∧ φE (el ) = ∅. The problem of obtaining a graph embedding that optimizes an objective function is called the graph embedding problem. Condition (a) just demonstrates that the mapping of vertices is feasible. Condition (b-1) shows that each edge (vp , vq ) ∈ E is mapped to a set Ap , where p ∈ P (φV (vp ), φV (vq )) when vp and vq are mapped to different vertices ni and nj (∈ N ). In addition, by condition (b-2), each edge (vp , vq ) ∈ E is mapped to the empty set when vp and vq are mapped to the same vertex n(∈ N ). An example of graph embedding is shown in Fig. 2. Because it is difficult to describe linear expressions that directly represent conditions (b-1) and (b-2), we transform them into local conditions (b -1)-(b -4) for each vertex of H and substitute condition (b ) shown below for condition (b). (b ) ∀el ∈ E, where el = (vp , vq ), ∀ni ∈ N : condition (b -1), (b -2), (b -3) or (b -4) is satisfied.
(b -1) φV (vp ) = ni ∧ φV (vq ) = ni ∧ (Deg = 0 ∨ Deg = 2), (b -2) φV (vp ) = ni ∧ φV (vq ) = ni ∧ Deg = 1, (b -3) φV (vp ) = ni ∧ φV (vq ) = ni ∧ Deg = 1, (b -4) φV (vp ) = ni ∧ φV (vq ) = ni ∧ Deg = 0, where ΓH (ni ) is the set of edges incident to a vertex ni ∈ N , and Deg = |φE (el ) ∩ ΓH (ni )|. Conditions (b -2) and (b -3) denote that one embedded edge connects to each endpoint vertex of a pass. Condition (b -1) denotes two edges connect to each non-endpoint vertex on the pass, and no edges connect to any vertex off the pass. In addition, condition (b -4) denotes that no embedded edges connect to the vertex ni mapped to both the endpoints vp and vq . (In other words, el is embedded inside ni .) When condition (b ) is satisfied, a pass is created, as shown in Fig. 5. 2) Linear Expressions for Graph Embedding: In this section, we define variables to represent mappings and derive linear equations for graph embedding. Let xp,i ∈ {0, 1} be a binary integer variable for each combination of G’s vertex vp ∈ V and H’s vertex ni ∈ N , and let yl,s ∈ {0, 1} be a binary integer variable for each combination of G’s edge el ∈ E and H’s edge as ∈ A. We set xp,i = 1 when φV (vp ) = ni ; otherwise xp,i = 0. Likewise, we set yl,s = 1 when as is included in φE (el ); otherwise yl,s = 0. That is to say, the set of xp,i represents a vertex mapping and that of yl,s represents an edge mapping. To satisfy conditions (a) and (b), we impose linear equations as follows. First, the linear equation to satisfy condition (a) can be written as xp,i =1, ∀vp ∈V. (1) n ∈N i
Second, we derive the linear equation to satisfy conditions (b -1)-(b -4). |φE (el ) ∩ ΓH (ni )| represents the number of edges mapped from el that connect to ni , and is equal to as ∈ΓH (ni ) yl,s . When a triple of numbers Tl,i is defined as ( as ∈ΓH (ni ) yl,s , xp,i , xq,i ), (0,0,0) and (2,0,0) satisfy condition (b -1), (1,1,0) satisfies condition (b -2), (1,0,1) satisfies condition (b -3), and (0,1,1) satisfies condition (b -4), where
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el = (vp , vq ). An equation that holds iff Tl,i is equal to one of the values listed above can be written as yl,s +xp,i +xq,i =2·ci,l , (2) as ∈Γ (n ) H
∀ni ∈N,
i
∀el ∈E,
el =(vp ,vq ),
where ci,l ∈ {0, 1} is a binary integer variable to limit the right side value of the equation to 0 or 2. III. D IRECTED H YPERGRAPH E MBEDDING P ROBLEM , AND PLD P LACEMENT AND ROUTING P ROBLEM A. Definitions of Graphs Handled in a PLD Placement and Routing Problem To represent a circuit with multi-terminal nets, we define the guest graph as a hypergraph GD = < VD , ED >, where VD (= {v0 , v1 , ..., vP }) is the set of vertices and ED (= {e0 , e1 , ..., eL }) is the set of hyperedges. Each vertex in GD represents an element in the circuit (e.g., gate, cell, and primary I/O). The vertices in VD are categorized as follows. Let VIO , VLE , and VF F (⊂ VD ) be the sets that represent I/O terminals, logic elements, and Flip-Flops (FFs), respectively. Thus, VD = VIO ∪ VLE ∪ VF F . Each hyperedge in ED represents multi-terminal nets in the circuit (including two-terminal nets). To represent the signal direction of a net corresponding to el ∈ ED , the vertex corresponding to the signal source to el is defined as vs(el )(∈ el ) and the set of all vertices corresponding to the signal destinations is defined as V t(el )(⊂ el ). An example of the guest graph representing a circuit netlist is shown in Fig. 4. Second, to represent the architecture of a PLD that includes wires with signal directions, we define the host graph as a directed graph HD = < ND , AD >, where ND (= {n0 , n1 , ..., nI }) is the set of vertices and AD (= {a0,0 , a0,1 , a1,0 , ..., aS,0 , aS,1 }) is the set of directed edges. Each vertex in ND represents blocks (e.g., I/O, logic, switch, and connection blocks). Then, we categorize the vertices in ND , like VD . Let NIOB , NLB and NSCB (⊂ ND ) be the sets that represent I/O blocks, logic blocks, and switch blocks, respectively. Thus, ND = NIOB ∪ NLB ∪ NSCB . (In this paper, connection blocks are substituted by switch blocks.) Each directed edge represents the signal direction of the wire corresponding to the edge. When as,1 exists, a pair of as,0 and as,1 represents a bidirectional wire, which has no signal direction. Otherwise, as,0 represents a wire with signal direction. That is, the directed edges with the same index s correspond to the same wire in the PLD. An example of a PLD architecture graph representing an FPGA is shown in Fig. 5. In addition, let Γ− HD (ni ) ⊂ AD be the set of the incoming edges to ni ∈ ND , and let Γ+ HD (ni ) ⊂ AD be the set of the outgoing + edges from ni . That is, ΓHD (ni ) = Γ− HD (ni ) ∪ ΓHD (ni ).
Fig. 4. An example of a circuit netlist GD
Fig. 5. An example of a PLD architecture graph HD (representing an FPGA) and a directed hypergraph embedding
Let φVD be a mapping from VD to ND , and lest φED be a mapping from ED to P (AD ), where P (AD ) is the power set of AD . Then, the pair of mappings (φVD , φED ) is defined as a directed hypergraph embedding (from GD to HD ) if the mappings satisfy the conditions (c) and (d) shown below. (c) ∀vp ∈ VD , ∃ni ∈ ND : φV (vp ) = ni (d) ∀el ∈ ED : φED (el ) = Ast ∃st ∈ ST ({φVD (vp ) | vp ∈ el }, φVD (vs(el ))) Condition (c) just demonstrates that the mapping of vertices is feasible. Condition (d) represents that el (∈ ED ) is mapped to the set of all the edges in a directed Steiner tree which connects the vertices el . (Note that a hyperedge is a set of vertices.) An example of a circuit netlist GD is shown in Fig. 4 and that of a directed hypergraph embedding from GD (as shown in Fig. 4) to HD is shown in Fig. 5. The directed hypergraph embedding problem is formulated in the same way as the graph embedding problem. The problem of obtaining a directed hypergraph embedding that optimizes an objective function is called the directed hypergraph embedding problem. C. Formulation of a PLD Placement and Routing Problem In this section, we formulate a PLD placement and routing problem, and we discuss it based on a directed hypergraph embedding. 1) Constraints: PLD placement and routing can be realized by adding constraints to the directed hypergraph embedding problem. The necessary constraints are those for block types and the number of resources of the PLD as follows: (i) The type of block (ii) The number of wires between two adjacent blocks (iii) The maximum number of input signals of a logic block (iv) The maximum number of output signals of a logic block (v) The number of FFs of a logic block By PLD resource constraint (i), each I/O terminal and logic element of the circuit needs to be mapped to the appropriate type of block. (e.g., an I/O terminal must be mapped to an I/O block.) In a directed hypergraph embedding, these five
B. Definition of Directed Hyper Graph Embedding To handle a circuit netlist and a PLD architecture graph on graph embedding, we define a directed hypergraph embedding with the constrained mapping of vertices, extending the definition of a graph embedding. (Hereinafter, it is simply called a directed hypergraph embedding).
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resource constraints can be considered by adding the four conditions 1-1) – 1-4) and bounding the four quantities 2) – 5) shown below. 1-1) ∀vp ∈ VIO , ∀ni ∈ N − NIOB : φVD (vp ) = ni 1-2) ∀vp ∈ VLE , ∀ni ∈ N − NLB : φVD (vp ) = ni 1-3) ∀vp ∈ VF F , ∀ni ∈ N − NLB : φVD (vp ) = ni 1-4) ∀vp ∈ VIO , ∀vq ∈ VIO : vp = vq =⇒ φVD (vp ) = φVD (vq ) vp = vq =⇒ φVD (vp ) = φVD (vq ) 2) ∀as,t ∈ AD : el ∈ED |φED (el ) ∧ as,t | 3) ∀ni ∈ NLB : el ∈ED |φED (el ) ∩ Γ+ HD (ni )| 4) ∀ni ∈ NLB : el ∈ED |φED (el ) ∩ Γ− HD (ni )| 5) ∀ni ∈ NLB : vp ∈VF F |φVD (vp ) ∧ ni | PLD resource constraint (i) corresponds to conditions 1-1) – 1-4). Conditions 1-1) – 1-3) show that VIO is mapped to only NIOB , VLE is mapped to only NLB , and VF F is mapped to only NLB , respectively. In addition, in PLD placement and routing, an IO block can be mapped at most one I/O terminal to. Thus, the mapping from VIO to NIOB is constrained by condition 1-4). Also, PLD resource constraints (ii) – (v) correspond to quantities 2) – 5), respectively; e.g., if there are four wires between each of the two adjacent blocks in the PLD, then quantity 2) is limited to four or less. 2) Objective Functions: As indices to evaluate PLD placement and routing, the total wire length and the critical path length are in common. Thus, we define two objective functions for the PLD placement and routing problem that correspond to the indices. Each of them can be expressed by a linear expression and linear inequalities as shown in Section IV. IV. ILP
Fig. 6. An example of overlapping mappings of edges when el ∈ E and El = {e 0 , e1 }
The left side of Fig. 6 illustrates an embedding from GD to HD . We consider that the embedding from GD to HD represents the embedding from GD to HD , illustrated on the right side of Fig. 6. Thus, we define constraints and objective functions in which an edge el ∈ ED is considered to be embedded to a ∈ AD if at least one edge e ∈ El is embedded to a ∈ AD . If the constraints and objective functions are formulated in linear expressions, the optimal embedding from GD to HD can be obtained by solving the graph embedding problem from GD to HD . The directions of edges can be handled by adding some constraints introduced in the following. B. Deriving Linear Formulation of Directed Graph Embedding Here, we derive an ILP formulation of the constrained graph embedding problem from GD to HD , extending the ILP formulation of the graph embedding defined in Section II. Because the equation for representing the embedding of vertices in a directed hypergraph embedding can be defined in a similar way to equation (1) in Section II-B2, we omit its derivation. To handle directed edges, we add some constraints to the graph embedding problem. Suppose conditions (a) and (b-1)– (c-1) are satisfied (i.e., a path is formed), and let us focus on each vertex of HD as we did when deriving conditions (b-1)– (c-1). Then, the conditions where the path corresponding to er = (vp , vq ) ∈ E is not a directed path are categorized as follows. Case 1) er is mapped to an incoming edge to φV (vp ). Case 2) er is mapped to an outgoing edge from φV (vq ). Case 3) er is mapped to two incoming edges to ni . Case 4) er is mapped to two outgoing edges from ni . An example of each case is shown in Fig. 7. In Case 1, an edge is mapped so that φV (vp ) is the last vertex of a path (it should be the first vertex). Case 2 is a similar case. In Cases 3 and 4, the mapped edges incident to each vertex have different directions on the path, and thus they do not form a directed path. To restrict Cases 1 to 4, we add conditions (e) – (g) as follows. ∀er (= (vp , vq )) ∈ E, ∀ni ∈ N :
FORMULATION OF A PLD P LACEMENT AND ROUTING P ROBLEM
In this section, we first reduce the directed hypergraph embedding problem into the graph embedding problem with some constraints and then formulate the graph embedding problem by linear inequalities. Finally, we add some other linear inequalities to realize the PLD placement and routing. A. Reduction of Directed Hypergraph Embedding into Constrained Graph Embedding Assume an instance I of the PLD placement and routing problem. The inputs are a circuit graph GD = < VD , ED > and a PLD architecture graph HD = < ND , AD >. Then, we define a directed graph GD = < VD , E > corresponding to GD =< VD , ED >, where E = E0 ∪E1 ∪...∪EL and El = {(vsl , vq )|vq ∈ V t(el )} ((vp , vq ) ∈ El denotes a directed edge from vp to vq ). El is considered as a decomposition of a directed hyperedge el into directed edges. Ignoring the direction of edges, the graph embedding problem from GD to HD is represented by inequalities (1) and (2) shown in Section II-B. Here, we define φE as a mapping from E to the power set of AD . Then, φE (el ) can be represented by overlapping φE (er ) for all er ∈ El . Fig. 6 illustrates an example of the overlapped edges corresponding to a hyperedge.
254
yr,s,0 ≤Congs , ∀as,0 ∈A.
e r ∈E
Fig. 7.
PLD resource constraints (iii) and (iv): First, we define some linear inequalities necessary to derive the linear form of the PLD resource constraints (iv). Let zl,s,t (∈ {0, 1}) be a binary integer for each combination of el ∈ ED and as,t ∈ AD . Then, the following linear inequality makes zl,s,t = 1 iff as,t is included in φE (el ).
Examples of Case 1, 2, 3 and 4
zl,s,t ≤
(e) φV (vp ) = ni ∧ φV (vq ) = ni =⇒ (|φE (er ) ∩ Γ+ HD (ni )| ≤ 1 ∧ |φE (er ) ∩ Γ− HD (ni )| ≤ 1), (f) |φE (er ) ∩ Γ+ HD (φV (vq ))| = 0, (g) |φE (er ) ∩ Γ− HD (φV (vp ))| = 0. Let yr,s,t (∈ {0, 1}) be a binary integer for each combination of er ∈ E of GD and as,t ∈ A of HD . yr,s,t = 1 means that as,t is included in φE (er ) and vice versa. Then, the number of edges outgoing from vertex ni ∈ ND and mapped er ∈ E is represented as as,t ∈Γ+ (ni ) yr,s,t . The HD number of edges incoming to vertex ni and mapped er is represented as as,t ∈Γ− (ni ) yr,s,t . Let Qr,i be a quadruple HD ( as,t ∈Γ+ (ni ) yr,s,t , as,t ∈Γ− (ni ) yr,s,t , xp,i , xq,i ). When HD HD the variables satisfy Equations (1) and (2), the values of Qr,i that do not satisfy conditions (e)–(g) are only (1,0,0,1) and (0,1,1,0). To restrict the values, we add the following linear constraints. yr,s,t +xp,i ≤1, (3) − (ni ) as,t ∈Γ HD yr,s,t +xq,i ≤1, (4) + (n ) a ∈Γ s,t
∀ni ∈N,
HD
(7) (8)
∀vp ∈ VF F , vp ∈VIO
∀ni ∈ N − NLB . xp,i ≤1,
∀ni ∈NIOB .
(11)
∀as,t ∈A.
zl,s,t ≤ LOU T ,
(12)
zl,s,t ≤ LIN ,
(13)
− as,t ∈Γ (ni ) HD
∀ni ∈NLB .
In a similar manner, PLD resource constraint (iii) is represented as PLD resource constraint (v): is omitted because of space limitation. 2) Objective Functions: (i) the total wire length: The total wire length can easily be represented as
el ∈E
as,t ∈A
zl,s,t .
(14)
(ii) the FF-to-FF maximum delay: Let αr be an integer variable that represents the net delay of er ∈ E , and let βr be an integer variable that represents the logic block delay of er ∈ E . Then, the following linear equations hold. ar =
br =w·
as,t ∈A
yr,s,t ,
ni ∈NLB
∀e r ∈E .
− (ni ) as,t ∈Γ HD
yr,s,t ,
(15) ∀e r ∈E .
(16)
Let us focus on an directed edge er (= (vp , vq )) ∈ E . The maximum delay from the FF vertices to the outputs of vq is greater than or equal to the sum of the maximum delay from the output of the FF vertices to the outputs of vp , the net delay between vp and vq , and the logic block delay between vp and vq (including the delay that vq causes). Let dq be the maximum delay to the outputs of vq . Then, it is represented as the following linear inequality.
PLD resource constraint (ii): Let Congs be the upper limit of the number of embedded edges to a bidirectional signal line as,0 , as,1 ∈ AD or a directed signal line as,0 ∈ AD (note that a bidirectional line is represented by a pair of directed edges (as,0 , as,1 )). The constraint on the parameter is represented in a linear form as follows. • For each bidirectional line as,0 , as,1 ∈ A, yr,s,0 +yr,s,1 ≤Congs , ∀as,t ∈A. (9) e ∈E
dp +αr +βr ≤dq , ∀e r (=(vp ,vq ))∈E ,
(17)
vq ∈VLE .
In addition, if vq is an FF vertex, the delay to the inputs of vq is an FF-to-FF delay and the maximum delay to the outputs of vq is zero (because vq is an FF vertex). Let O be an integer
r
•
el ∈E
1) Linear Formulations of a PLD Placement and Routing Problem’s Constraints: We formulate the constraints for the PLD placement and routing problem given in Section III-C1. PLD resource constraint (i): Conditions 1-1) – 1-4) are easily represented as follows.
xp,i = 0,
∀el ∈E,
+ (ni ) as,t ∈Γ HD
C. Deriving Additional Linear Constraints and Objective Functions for a PLD Placement and Routing Problem
(5) (6)
yr,s,t ≤ |El |·zl,s,t ,
e r ∈El
el ∈E
e r =(vp ,vq ).
xp,i = 0, ∀vp ∈ VIO , ∀ni ∈ N − NIOB . xp,i = 0, ∀vp ∈ VLB , ∀ni ∈ N − NLB .
Let LOU T and LIN be constants that represent the upper limits of the number of embedded output and input signals of each logic block vertex, respectively. Then, PLD resource constraints (iii) and (iv) are represented as
i
∀e r ∈E ,
(10)
For each directed line as,0 ∈ A,
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variable greater than or equal to the maximum FF-to-FF delay. Then, the following linear inequality holds.
∀e r (=(vp ,vq ))∈E ,
dp +αr +βr ≤O,
(18)
dq =0,
(19)
vq ∈VIO ∪VF F .
The minimization of the FF-to-FF delay can be realized by minimizing O. V. E XPERIMENTAL R ESULTS We performed experiments to evaluate our ILP-based method. In the experiments, we automatically generated expressions for each pair of a given circuit and the PLD architecture graph of a given PLD by a Perl script. Then, we obtained the optimal solution of the PLD placement and routing problem by using a well-known ILP solver CPLEX[8]. CPLEX was executed on a PC equipped with two Intel Xeon X5482 3.3 GHz CPUs (eight cores in total) and 48 GB memory. In the experiments, we gave 2- to 4-bit adders with feedback loops as GD . In addition, we gave the PLD architecture graphs representing FPGAs with different sizes as HD . We assumed that each logic block has a 4-input and 2-output LUT to set the parameters mentioned in (iii) and (iv) in Section IV.C.1 as LIN = 4 and LOU T = 2. Furthermore, we assumed that the number of wires between two adjacent blocks is four and the number of FFs of a logic block is one. The results of the minimization of the total wire length are shown in Table I, and those of the critical path lengths (i.e., maximum FF-to-FF path lengths) are shown in Table II. When minimizing the critical path length, the total wire length was handled as the secondary objective function. Note that LB num denotes the number of logic blocks in the PLD.
Fig. 8.
solutions in terms of total wire length and critical path length. The critical path lengths were reduced by 28.6% on average when it was optimized. Fig. 8 shows an example of our well packed placement and routing results. VI. C ONCLUSIONS In this paper, we proposed the ILP formulation of placement and routing problem for PLDs, and confirmed that our ILPbased method obtained the optimal solutions for small circuits in experiments. Our future work includes the development of new heuristic methods for PLD placement and routing utilizing the obtained optimal solutions. R EFERENCES [1] Robert J. Francis, “Technology Mapping for Lookup-Table Based FieldProgrammable Gate Arrays,” Proc. ACM/IEEE 27th Design Automation Conf, pp. 613–619, June 1990. [2] J. Cong and Y. Ding, “Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,” IEEE Trans. CAD, vol. 13, no. 1, pp. 1–12, Jan. 1994. [3] C. Mulpuri and S. Hauck, “Runtime and quality tradeoffs in FPGA placement and routing,” Proc. ACM/SIGDA FPGA ‘01, pp. 12–20, Feb. 2001. ´ [4] Manuel Rubio del Solar, Juan Antonio Gomez Pulido, Juan Manuel Sa´nchez Pe´rez, and Miguel A´ngel Vega Rodri´guez, “Genetic Algorithms for Solving the Placement and Routing Problem of an FPGA with Area Constraints,” Proc. IEEE ISDA, pp. 31–35, Aug. 2004. [5] V. Betz, J. Rose, and A. Marquardt, “Architecture and CAD for DeepSubmicron FPGAs,” Springer, 1999. [6] J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. M. Fang, and J. Rose, “VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling,” Proc. ACM/SIGDA FPGA ‘09, pp. 133–142, Feb. 2009. [7] Alexander Schrijver, “Theory of Linear and Integer Programming,” Wiley, 1998. [8] CPLEX，http://www-01.ibm.com/software/integration/ optimization/cplex-optimizer/ [9] M. Munch, N. Wehn, and M. Glesner, “Optimum Simultaneous Placement and Binding for Bit-Slice Architectures,” Proc. ASP-DAC ’95, pp. 735– 740, Aug. 1995. [10] J. Lou, A. H. Salek, and M. Pedram, “An Exact Solution to Simultaneous Technology Mapping and Linear Placement Problem,” Proc. ACM/IEEE ICCAD ’97, pp. 671–675, Nov. 1997. [11] N. Togawa, M. Yanagisawa, and T. Ohtsuki, “Maple-opt: a performanceoriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs,” IEEE Trans. CAD, Vol. 17, No. 9, pp. 803–818, Sep. 1998.
TABLE I R ESULT 1 ( MINIMIZATION OF THE TOTAL WIRE LENGTH ) GD 2-bit
3-bit 4-bit
HD (LB num) 4 9 16 4 9 4
Time (s) 5.73 39.30 135.29 26.16 275.25 58.68
Total Wire Len.
Critical Path Len.
13 14 14 19 20 25
8 9 8 12 12 14
TABLE II R ESULT 2 ( MINIMIZATION OF THE CRITICAL PATH LENGTH ) GD 2-bit
3-bit 4-bit
HD (LB num) 4 9 16 4 9 4
Time (s) 6.03 39.13 112.02 85.35 3236.13 496.59
Total Wire Len.
Critical Path Len.
14 15 15 23 24 29
6 6 6 8 8 11
Input netlist (left) and P&R result (right)
In the experiments, though our proposed method took a long time to obtain the optimal solutions, we confirmed that for small circuits, our method successfully obtained optimal
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